CN102044438A - MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof - Google Patents
MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof Download PDFInfo
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- CN102044438A CN102044438A CN2009101976138A CN200910197613A CN102044438A CN 102044438 A CN102044438 A CN 102044438A CN 2009101976138 A CN2009101976138 A CN 2009101976138A CN 200910197613 A CN200910197613 A CN 200910197613A CN 102044438 A CN102044438 A CN 102044438A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000007924 injection Substances 0.000 claims abstract description 34
- 238000002347 injection Methods 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 37
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 19
- 230000008569 process Effects 0.000 abstract description 18
- 230000036632 reaction speed Effects 0.000 abstract description 5
- 229940090044 injection Drugs 0.000 description 24
- 150000002500 ions Chemical class 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- -1 LDD ion Chemical class 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
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- 230000009931 harmful effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Abstract
The invention relates to an MOS (Metal Oxide Semiconductor) transistor and a manufacturing method thereof. The manufacturing method comprises the following steps of: providing a semiconductor substrate, wherein a gate dielectric layer and a gate electrode are sequentially formed on the semiconductor substrate, the gate electrode is provided with a first side and a second side, the semiconductor substrate at the first side of the gate electrode is a source region, and the semiconductor substrate at the second side of the gate electrode is a drain region; carrying out light doped injection on the drain region, and carrying out source electrode injection on the source region to respectively form a light doped drain electrode and a source electrode; forming side walls at two sides of the gate electrode on the gate electrode dielectric layer; and carrying out drain electrode injection on the drain region to form a drain electrode. In the invention, an LDD (Light Doped Drain) structure is formed only on the drain electrode through the local adjustment of a standard MOS transistor standard process, thereby the resistance of a conducting channel is reduced, the length of the conducting channel is lengthened, the short channel effect is lightened, and the reaction speed and the overall electrical property of the device are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of MOS transistor and manufacture method thereof.
Background technology
With the raising of integrated circuit integrated level, device size is progressively scaled, and characteristic size has reached the 32nm magnitude at present.Metal oxide semiconductor field effect tube (MOS) is modal semiconductor device, is the elementary cell that constitutes various complicated circuits.MOS transistor basic structure comprises three main region: source electrode (source), drain electrode (drain) and gate electrode (gate).Wherein source electrode and drain electrode according to the type of device difference, can be divided into n type doping (NMOS) and p type doping (PMOS) by highly doped formation.
In the scaled process of device, drain voltage does not reduce thereupon, this just causes the increase of the channel region electric field between source/drain electrode, under the highfield effect, electronics can accelerate to the speed than much higher times of heat movement speed between twice collision, be called as hot electron owing to kinetic energy is very big, thereby cause thermoelectronic effect (hot electron effect).This effect belongs to the small-size effect of device, can cause that hot electron injects to gate dielectric layer, forms gate electrode electric current and substrate current, influences the reliability of device and circuit.
In order to overcome thermoelectronic effect, have multiplely to the improving one's methods of mos transistor structure, for example two injecting structure, buried channel structure, discrete grid structures, bury drain structure etc.; Wherein study morely and practical value is bigger a kind of be lightly doped drain (lightly doped drain:LDD) structure.The effect of lightly doped drain structure is to reduce electric field, can significantly improve thermoelectronic effect.
Although the LDD structure has significant effect to reducing thermoelectronic effect, also there are some shortcomings.Such as causing the resistance between source/drain electrode to increase, saturation current is reduced, and then cause that the device reaction speed descends.In addition, the LDD structure also makes the MOS transistor manufacturing process more complicated.
In the existing integrated technique, as Fig. 1～shown in Figure 4, the manufacturing of MOS transistor mainly comprises following flow process: with reference to figure 1, at first form gate electrode dielectric layer 110 and gate electrode 120 on Semiconductor substrate 100; With reference to figure 2, then the injection of LDD ion is carried out in source region 130 and drain region 140, and the injection ion is spread in substrate by annealing process; With reference to figure 3, form side wall 150 afterwards, carry out source/drain electrode again and inject, form device architecture as shown in Figure 4 at last.In above technology, the LDD structure is formed at source region and drain region respectively, and because the annealing effect makes the physical width of length of effective channel much smaller than gate electrode, causes short-channel effect easily.
Publication number is that 20040150014 U.S. Patent application has been cancelled the LDD structure avoiding its every side effect in mos transistor structure, but need do bigger adjustment to technical process and parameter, cause certain difficulty to actual production.
Be to improve the performance of MOS transistor, need a kind of new manufacturing process of exploitation, under the situation that does not improve process complexity, alleviate or eliminate every side effect that the LDD structure causes.
Summary of the invention
The problem that the present invention solves provides a kind of MOS transistor and manufacture method thereof, reduces the harmful effect that the LDD structure is brought, and improves the electric property of MOS transistor.
For addressing the above problem, the invention provides a kind of manufacture method of MOS transistor, comprise the following step:
Semiconductor substrate is provided, is formed with gate dielectric layer and gate electrode on the described Semiconductor substrate successively, described gate electrode has first side and second side, and the Semiconductor substrate of described gate electrode first side is the source region, and the Semiconductor substrate of second side is the drain region;
Light dope is carried out in described drain region inject, the source electrode injection is carried out in described source region, form lightly doped drain and source electrode respectively;
The both sides of gate electrode form side wall on described gate dielectric layer;
To the injection that drains of described drain region, form drain electrode.
Optionally, describedly light dope is carried out in the drain region inject and to comprise: on described Semiconductor substrate, form first photoresist layer; Graphical described first photoresist layer defines the drain region shape; With described first photoresist layer is that mask carries out the light dope injection, removes described first photoresist layer afterwards.
Optionally, the source electrode injection being carried out in described source region comprises: form second photoresist layer on described Semiconductor substrate; Graphical described second photoresist layer defines the source region shape; With described second photoresist layer is that mask carries out the source electrode injection, removes described second photoresist layer afterwards.
Optionally, described drain region is drained to inject comprise: on described Semiconductor substrate, form the 3rd photoresist layer; Graphical described the 3rd photoresist layer defines the drain region shape; With described the 3rd photoresist layer is the mask injection that drains, and removes described the 3rd photoresist layer afterwards.
Optionally, described light dope ion implantation dosage is 10
12～10
13/ cm
2The order of magnitude.
Optionally, the dosage of described source electrode injection is 10
14～10
15/ cm
2The order of magnitude.
Optionally, the dosage of described drain electrode injection is 10
14～10
15/ cm
2The order of magnitude.
Optionally, the ionic type that described light dope injects, source electrode injects, drain electrode is injected is arsenic or antimony.
Optionally, the ionic type that described light dope injects, source electrode injects, drain electrode is injected is a boron.
Optionally, the material of described gate dielectric layer is a silicon dioxide.
For addressing the above problem, the present invention also provides a kind of MOS transistor, comprising:
Semiconductor substrate;
Gate dielectric layer and gate electrode are formed on the described Semiconductor substrate successively;
Side wall is formed at the both sides of described gate electrode;
Source electrode is formed in the Semiconductor substrate of described gate electrode one side;
Drain electrode is formed in the Semiconductor substrate of described gate electrode opposite side;
The lightly doped drain structure, described lightly doped drain structure only is formed in the described drain electrode.
Optionally, described light dope ion implantation dosage is 10
12～10
13/ cm
2The order of magnitude.
Optionally, the dosage of described source electrode injection is 10
14～10
15/ cm
2The order of magnitude.
Optionally, the dosage of described drain electrode injection is 10
14～10
15/ cm
2The order of magnitude.
Compared with prior art, technique scheme has the following advantages: adjust by the part on MOS transistor standard technology basis, only form the LDD structure in drain electrode, do not form the LDD structure at source electrode, reduced the resistance of conducting channel thus, the conducting channel length that extended has alleviated short-channel effect, has improved device reaction speed and whole electrical property.
In addition, technique scheme is only done local the adjustment to technological process, and production capacity and cost are not had considerable influence.
Description of drawings
Fig. 1 to Fig. 4 is the cross-sectional view of existing technology MOS transistor manufacture method;
Fig. 5 is the schematic flow sheet of the MOS transistor manufacture method of embodiment of the present invention;
Fig. 6 to Figure 11 is the cross-sectional view of the nmos pass transistor manufacture method of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Method provided by the invention is not only applicable to the manufacturing of MOS transistor, is applicable to integrated MOS transistor circuit, the particularly characteristic size MOS transistor circuit below 130nm yet.Described MOS transistor can be PMOS transistor or the nmos pass transistor among the CMOS.
Existing MOS transistor manufacturing process all forms the LDD structure at source electrode and drain electrode, because the doping content of LDD structure is low, resistance is higher relatively, therefore the resistance of conducting channel is higher, cause RC to postpone to increase, reduced the reaction speed of MOS transistor, influenced device performance.In addition, because all there is the LDD structure in source/drain electrode, its horizontal proliferation meeting causes the shortening of length of effective channel, causes short-channel effect, causes bad results such as puncture voltage reduction, channel leakage increase.
The inventor finds that source electrode institute making alive is all not too high generally speaking, is generally ground connection, and therefore the electric field strength of one side is limited in the source region, there is no need to form the LDD structure.As only forming the LDD structure, can reduce channel resistance to a certain extent, and increase channel length in drain electrode.
Because in the present integrated technique, the process that forms the LDD structure is ion to be carried out in source/drain electrode simultaneously inject, so the LDD structure all exists at source-drain electrode.For this reason,, it is done local adjustment, only form the LDD structure,, improve the device performance of formed MOS transistor so that under the not obvious situation that influences process complexity in drain electrode based on existing MOS transistor technological process.
About the technological process adjustment to the MOS standard technology, Fig. 5 has indicated the schematic flow sheet of a specific embodiment of the present invention.As shown in Figure 5, execution in step S510 provides Semiconductor substrate, be formed with gate dielectric layer and gate electrode on the described Semiconductor substrate successively, described gate electrode has first side and second side, and the Semiconductor substrate of described gate electrode first side is the source region, and the Semiconductor substrate of second side is the drain region; Execution in step S520 carries out light dope to described drain region and injects, and source electrode is carried out in described source region inject, and forms lightly doped drain and source electrode respectively; Execution in step S530, the both sides of gate electrode form side wall on described gate dielectric layer; Execution in step S540 to the injection that drains of described drain region, forms drain electrode.
Method provided by the invention is applicable to the manufacturing of MOS single tube device in the integrated circuit, but method of the present invention should be limited in the manufacturing process of MOS single tube device, form the MOS transistor integrated device or in the situation of one-sided formation LDD structure, method of the present invention also can well be suitable for if in other technologies, relate to.
Fig. 6 to Figure 11 is the cross-sectional view of the nmos pass transistor manufacture method of first embodiment of the invention, is elaborated below in conjunction with Fig. 5.
With reference to Fig. 5 and Fig. 6, execution in step S510 provides Semiconductor substrate, be formed with gate dielectric layer and gate electrode on the described Semiconductor substrate successively, described gate electrode has first side and second side, and the Semiconductor substrate of described gate electrode first side is the source region, and the Semiconductor substrate of second side is the drain region.Specifically comprise: P type semiconductor substrate 600 is provided, certain isolation structure (not shown) is arranged on the described Semiconductor substrate 600, as silica etc.Silicon or SiGe that described Semiconductor substrate 600 can be monocrystalline, polycrystalline or non crystalline structure also can be silicon-on-insulators (SOI).The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.
Form gate dielectric layer 610 on described Semiconductor substrate 600 surfaces, its material is a silica, thickness is tens of to the hundreds of dust, its deposition process can be conventional vacuum coating technology, for example boiler tube thermal oxidation, ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, present embodiment adopts the boiler tube thermal oxidation technology.
On gate dielectric layer 610, form the gate electrode layer (not shown) then, described gate electrode layer can be polysilicon or metal, select n type doped polycrystalline silicon in the present embodiment for use, its formation method is low-pressure chemical vapor phase deposition (LPCVD), dopant ion is a phosphorus, this method is a knowledge known in those skilled in the art, and the thickness of described gate electrode layer is between hundreds of extremely several thousand dusts.Then described gate electrode layer is carried out graphically, form the gate electrode 620 of nmos pass transistor.So far, the device architecture of formation as shown in Figure 6.Above technological process is all consistent with existing MOS transistor technological process.
After described gate electrode 620 forms, described Semiconductor substrate 600 is divided into three parts, wherein first is positioned at the part of gate electrode below 620, channel region for MOS transistor, second and third part for being positioned at the part of described gate electrode 620 both sides, is respectively source region and drain region shown in I district among Fig. 6 and II district, from structure source region and drain region is equivalent, can distinguish source region and drain region but vary in size according to applied voltage polarity in physical circuit.The I district is the source region in the present embodiment, and the II district is the drain region.
Shown in Fig. 5 and Fig. 7,8, execution in step S520 carries out light dope to described drain region and injects, and source electrode is carried out in described source region inject, and forms lightly doped drain and source electrode respectively.The light dope that at first carries out the drain region in the present embodiment injects, and as shown in Figure 7, specifically comprises: form first photoresist layer on described Semiconductor substrate 600, then described first photoresist layer is carried out graphically, one side forms photoresist figure 630 in the source region.Be mask with described photoresist figure 630 then, light dope carried out in the drain region inject.For the NMOS of present embodiment, injection be n type ion, for example phosphorus (P), arsenic (As).Ion implantation dosage is 10
12～10
13/ cm
2The order of magnitude injects ion energy and is 10 to 100keV, and it injects degree of depth is tens of to the hundreds of dust.After described light dope injects and finishes, remove described photoresist figure 630, described Semiconductor substrate 600 is heat-treated, the injection ion in the drain region is taken place vertically and horizontal diffusion, its part is diffused in the Semiconductor substrate 600 of gate electrode 620 belows, form lightly doped drain 640.The difference of this step and existing MOS technology is that light dope injects only carries out at the drain region, and the source region is not related to.
After forming lightly doped drain 640, source electrode is carried out in described source region inject, with reference to Fig. 8, form second photoresist layer on described Semiconductor substrate 600 surfaces, and patterned, one side forms photoresist figure 650 in the drain region.Subsequently, be that mask carries out the ion injection to the source region with described photoresist figure 650, promptly source electrode injects.To nmos device, injecting ionic type is the n type, and as arsenic (As), antimony (Sb), it is 10 that described source electrode injects ion dose
14～10
15/ cm
2The order of magnitude injects ion energy and is 10 to 100keV, and it injects ion dose and injects high two orders of magnitude than described light dope.Source electrode is removed described photoresist figure 650 after injecting, and one side forms the source electrode 660 of higher-doped concentration in the source region.This moment device architecture as shown in Figure 8, compared with prior art, the source electrode of the technical program only injects through source electrode and forms, the light dope injection process does not relate to the source region, the inventor is through discovering, the ion dose that source electrode is injected is chosen to be 10
14～10
15/ cm
2The order of magnitude injects ion energy and is chosen to be 10 to 100keV, and the MOS electric properties of devices is not produced obvious influence.
Need to prove that the light dope that present embodiment carries out the drain region earlier injects, in other embodiments, the source electrode that also can carry out the source region earlier injects.
With reference to Fig. 5 and Fig. 9, execution in step S530, the both sides of gate electrode form side wall on described gate dielectric layer.Specifically comprise: on the gate dielectric layer of described Semiconductor substrate 600, form the dielectric layer (not shown), present embodiment is a silica material, generation type can be low-pressure chemical vapor phase deposition (LPCVD), thickness is higher than the height of described gate electrode 620, and described dielectric layer also can be selected oxide layer-silicon nitride-oxide layer (ONO) structure for use.Described dielectric layer is returned (etch back) technology at quarter, form side wall (spacer) 670 in described gate electrode 620 both sides, re-use wet etching afterwards and remove described side wall 670 gate dielectric layer 610 in addition.As shown in Figure 9.It act as grill-protected electrode 620.
With reference to figure 5 and Figure 10, execution in step S540 to the injection that drains of described drain region, forms drain electrode.Specifically comprise: on described Semiconductor substrate 600, form the 3rd photoresist layer, and patterned, one side forms photoresist figure 680 in the source region, is that mask carries out the ion injection to the drain region with described photoresist layer 680, i.e. drain electrode is injected, and forms drain electrode 640b.The ionic type that described drain electrode is injected is identical with the source electrode injection, and the type of MOS transistor is NMOS in the present embodiment, and injecting ionic type at this is the n type, and as arsenic (As), antimony (Sb), it is 10 that ion dose is injected in described drain electrode
14～10
15/ cm
2The order of magnitude injects ion energy and is 10 to 100keV.Because the existence of side wall 670, make in the Semiconductor substrate 600 of side wall 670 belows and do not inject ion, the low concentration doping ion that forms when therefore below the described side wall 670 in drain region, only having light dope to inject, this zone is the LDD structure 640a of drain electrode 640b.The difference of above correlation step and existing technological process is: existing technology is carried out ion simultaneously to source/drain electrode and is injected, source/drain electrode all contains the LDD structure, the Twi-lithography technology of then utilizing present embodiment realizes the selectivity of source/drain region is injected, and only forms the LDD structure in drain electrode.
After described drain electrode injection is finished, described photoresist figure 680 is removed, just form the nmos device of gained, its structure comprises Semiconductor substrate 600 as shown in figure 11; Gate dielectric layer 610 and gate electrode 620, described gate dielectric layer 610 and gate electrode 620 form successively with described Semiconductor substrate 600 on; Source electrode 660 is formed in the Semiconductor substrate 600 of described gate electrode 620 1 sides; Side wall 670 is formed at the both sides of described gate electrode 620; Drain electrode 640b is formed in the Semiconductor substrate 600 of gate electrode 620 1 sides relative with described source electrode 660; LDD structure 640a, described LDD structure 640a only is formed in the described drain electrode 640a.Should scheme with prior art gained nmos pass transistor more as can be known, ion concentration when the ion implantation concentration in the present embodiment below source region side wall 670 is the source electrode injection, do not form the LDD structure, its implantation dosage injects high two orders of magnitude than light dope, can significantly reduce the resistance of conducting channel.In addition, the source electrode 660 of present embodiment source region below inject ions not horizontal proliferation to gate electrode 620 belows, and have the LDD structure owing to source electrode in the prior art, and annealed technology diffuses to the gate electrode below, its length of effective channel is less than the physical width of gate electrode, the length of effective channel of the MOS transistor that present embodiment forms is relatively large, the easier short-channel effect of avoiding.
More than first embodiment be the manufacturing process of nmos pass transistor, the transistorized manufacture method of brief description PMOS is as the second embodiment of the present invention.The transistorized manufacture method of PMOS and first embodiment are similar, only inject ionic type and source electrode, drain electrode in Semiconductor substrate type, light dope and inject aspect the ionic type difference to some extent.For the PMOS transistor, select the N type semiconductor substrate for use; Light dope is carried out when injecting in the drain region, injection be p type ion, for example boron; Source electrode injects, drain electrode is injected the ionic type of selecting for use and is p type, for example boron.
According to the design rule of integrated circuit, the size of the every structure of device can be scaled.The MOS transistor device that provides the integrated method of a kind of technology to have one-sided LDD structure with formation is provided main purpose of the present invention, therefore the concrete process of device is not too much related to.
The above is two specific embodiments of the present invention, forms nmos pass transistor and PMOS transistor respectively.The present invention adjusts by the part on MOS standard technology basis, only forms the LDD structure in drain electrode, does not form the LDD structure at source electrode, reduced the resistance of conducting channel thus, the conducting channel length that extended has alleviated short-channel effect, has improved device reaction speed and whole electrical property.
The technical program is only done local the adjustment to technological process, and production capacity and cost are not had considerable influence.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (11)
1. the manufacture method of a MOS transistor is characterized in that, comprising:
Semiconductor substrate is provided, is formed with gate dielectric layer and gate electrode on the described Semiconductor substrate successively, described gate electrode has first side and second side, and the Semiconductor substrate of described gate electrode first side is the source region, and the Semiconductor substrate of second side is the drain region;
Light dope is carried out in described drain region inject, the source electrode injection is carried out in described source region, form lightly doped drain and source electrode respectively;
The both sides of gate electrode form side wall on described gate dielectric layer;
To the injection that drains of described drain region, form drain electrode.
2. the manufacture method of MOS transistor according to claim 1 is characterized in that, describedly light dope is carried out in the drain region injects and to comprise: form first photoresist layer on described Semiconductor substrate; Graphical described first photoresist layer defines the drain region shape; With described first photoresist layer is that mask carries out the light dope injection, removes described first photoresist layer afterwards.
3. the manufacture method of MOS transistor according to claim 1 is characterized in that, the source electrode injection is carried out in described source region comprised: form second photoresist layer on described Semiconductor substrate; Graphical second photoresist layer defines the source region shape; With described second photoresist layer is that mask carries out the source electrode injection, removes described second photoresist layer afterwards.
4. the manufacture method of MOS transistor according to claim 1 is characterized in that, described drain region is drained to inject to be comprised: form the 3rd photoresist layer on described Semiconductor substrate; Graphical described the 3rd photoresist layer defines the drain region shape; With described the 3rd photoresist layer is the mask injection that drains, and removes described the 3rd photoresist layer afterwards.
5. the manufacture method of MOS transistor according to claim 1 is characterized in that, described light dope ion implantation dosage is 10
12～10
13/ cm
2The order of magnitude.
6. the manufacture method of MOS transistor according to claim 1 is characterized in that, the dosage that described source electrode injects is 10
14～10
15/ cm
2The order of magnitude.
7. the manufacture method of MOS transistor according to claim 1 is characterized in that, the dosage that described drain electrode is injected is 10
14～10
15/ cm
2The order of magnitude.
8. MOS transistor comprises:
Semiconductor substrate;
Gate dielectric layer and gate electrode are formed on the described Semiconductor substrate successively;
Side wall is formed at the both sides of described gate electrode;
Source electrode is formed in the Semiconductor substrate of described gate electrode one side;
Drain electrode is formed in the Semiconductor substrate of described gate electrode opposite side;
The lightly doped drain structure;
It is characterized in that described lightly doped drain structure only is formed in the described drain electrode.
9. the manufacture method of MOS transistor according to claim 1 is characterized in that, described light dope ion implantation dosage is 10
12～10
13/ cm
2The order of magnitude.
10. the manufacture method of MOS transistor according to claim 1 is characterized in that, the dosage that described source electrode injects is 10
14～10
15/ cm
2The order of magnitude.
11. the manufacture method of MOS transistor according to claim 1 is characterized in that, the dosage that described drain electrode is injected is 10
14～10
15/ cm
2The order of magnitude.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197613A CN102044438B (en) | 2009-10-23 | 2009-10-23 | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197613A CN102044438B (en) | 2009-10-23 | 2009-10-23 | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102044438A true CN102044438A (en) | 2011-05-04 |
| CN102044438B CN102044438B (en) | 2012-10-03 |
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| CN105206216A (en) * | 2015-10-23 | 2015-12-30 | 武汉华星光电技术有限公司 | Display device and display device shift register circuit applied to gate drive circuit |
| CN110943129A (en) * | 2018-09-25 | 2020-03-31 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN111446298A (en) * | 2020-04-10 | 2020-07-24 | 上海华虹宏力半导体制造有限公司 | Medium-high voltage CMOS device and manufacturing method thereof |
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| US6483157B1 (en) * | 1997-06-20 | 2002-11-19 | Advanced Micro Devices, Inc. | Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in the drain-side junction area |
| CN100369266C (en) * | 2003-09-29 | 2008-02-13 | 友达光电股份有限公司 | Controlled film transistor, its preparation method and electroluminescent display apparatus containing same |
| CN101345257A (en) * | 2007-07-10 | 2009-01-14 | 联华电子股份有限公司 | Asymmetric metal-oxide-semiconductor transistor and production method and element using the same |
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| CN105206216A (en) * | 2015-10-23 | 2015-12-30 | 武汉华星光电技术有限公司 | Display device and display device shift register circuit applied to gate drive circuit |
| CN110943129A (en) * | 2018-09-25 | 2020-03-31 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN113299554A (en) * | 2020-02-24 | 2021-08-24 | 微龛(广州)半导体有限公司 | Asymmetric MOSFET (Metal-oxide-semiconductor field Effect transistor), manufacturing method thereof and semiconductor device |
| CN111446298A (en) * | 2020-04-10 | 2020-07-24 | 上海华虹宏力半导体制造有限公司 | Medium-high voltage CMOS device and manufacturing method thereof |
| CN111446298B (en) * | 2020-04-10 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Medium-high voltage CMOS device and manufacturing method thereof |
| CN111785774A (en) * | 2020-06-15 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | CMOS device in BCD process and manufacturing method thereof |
| CN111785774B (en) * | 2020-06-15 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | CMOS device in BCD process and manufacturing method thereof |
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