CN102097320B - NMOS (N-channel Metal Oxide Semiconductor) device and forming method thereof - Google Patents

NMOS (N-channel Metal Oxide Semiconductor) device and forming method thereof Download PDF

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CN102097320B
CN102097320B CN 200910201193 CN200910201193A CN102097320B CN 102097320 B CN102097320 B CN 102097320B CN 200910201193 CN200910201193 CN 200910201193 CN 200910201193 A CN200910201193 A CN 200910201193A CN 102097320 B CN102097320 B CN 102097320B
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nmos device
semiconductor substrate
formation method
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CN102097320A (en
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甘正浩
吴永坚
郭锐
廖金昌
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Abstract

The invention relates to a forming method of an NMOS (N-channel Metal Oxide Semiconductor) device, comprising the following steps of: providing semiconductor substrates; sequentially forming a grid dielectric layer and a gate electrode on the surfaces of the semiconductor substrates, wherein the semiconductor substrates arranged at two sides of the gate electrode are a source region and a drain region respectively; sequentially injecting indium ions and boron ions into the source region and the drain region to form a pocket area; and injecting phosphorus ions into the source region and the drain region that are arranged above the pocket area to form a lightly doped region. In the method, the doping amount of the indium ions is (0.5E13-2E13)/cm<2>, the doping amount of the phosphorus ions is (1E14-2.5E14)/cm<2>, and the doping amount of the boron ions is (0.5E13-4E13)/cm<2>. The invention also provides an NMOS device formed by using the forming method of the same.

Description

Nmos device and forming method thereof
Technical field
The present invention relates to semiconductor and form technique, particularly a kind of nmos device and forming method thereof.
Background technology
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor is called for short MOS).Integrated circuit is since invention, and its progress on performance and function is advanced by leaps and bounds, and the physical dimension of MOS device constantly dwindling always, and its characteristic size has entered nanoscale at present.
In the scaled process of MOS device, drain voltage does not reduce thereupon, this just causes the increase of the channel region electric field between source electrode, drain electrode, under the highfield effect, electronics can accelerate to the speed than high times of heat movement speed between twice collision, so kinetic energy is very large, and these electronics are called as hot electron, described hot electron can inject to gate dielectric layer, thereby causes thermoelectronic effect (hot electroneffect).This effect belongs to the small-size effect of device, and described effect can cause gate electrode electric current and Semiconductor substrate electric current, affects the reliability of device and circuit.
Above-mentioned thermoelectronic effect is a key factor that affects MOS device lifetime (TTF): thermoelectronic effect is more weak, and device lifetime is longer; Otherwise thermoelectronic effect is more obvious, and device lifetime is shorter.In order to improve MOS device lifetime, need to suppress thermoelectronic effect.For nmos device, thermoelectronic effect is particularly outstanding.Because the charge carrier of NMOS is electronics, and the charge carrier of PMOS is the hole, with the hole relatively, the electronics interface potential barrier between Semiconductor substrate and the gate dielectric layer of more easily jumping over, thus so that the easier injection grid dielectric layer of electronics causes the injury to gate dielectric layer.
A kind of nmos device with pocket (pocket) doped structure that provides in the Chinese patent of the patent No. for ZL02106726.0 has suppressed thermoelectronic effect to a certain extent.Described structure comprises as shown in Figure 1: Semiconductor substrate 001 is provided, and B Implanted ion on described Semiconductor substrate 001 forms P type trap 002 and channel region (not indicating among the figure); Form successively gate dielectric layer 003 and gate electrode 004 on described Semiconductor substrate 001 surface, the Semiconductor substrate of described gate electrode 004 both sides is source region and drain region; In described source region and drain region, inject indium ion, to form pocket area 005; Continuation is injected phosphonium ion in described source region and drain region, form light doping section 006; Both sides at gate dielectric layer 003 and gate electrode 004 form sidewall 007; At last, mixed deeply in described source region and drain region, to form source electrode 008 and drain electrode 009.
In the such scheme, form pocket region with fractional condensation and the diffusion of the boron ion of channel region below the obstruction grid, to suppress further thermoelectronic effect by injecting.But the indium ion volume is larger in this technical scheme, and the damage to substrate during injection is larger.
Prior art also discloses a kind of method that suppresses thermoelectronic effect, by nmos device doped indium ion and boron ion formation bag structure are improved, the common scope of the drain saturation current value of described nmos device is 0.49mA/ μ m～0.59mA/ μ m, and doping ion and the dosage range of the doping ion of corresponding formation bag structure and dosage range, formation light doping section are respectively: indium ion dosage range: 3.5E13～5E13/cm 2Boron ion dose scope: 2E13～6E13/cm 2Phosphonium ion dosage range: 3E14～5.5E14/cm 2
But above-mentioned arts demand optimization is with further raising device lifetime.
Summary of the invention
The problem that the present invention solves provides a kind of nmos device and forming method thereof, with the establishment thermoelectronic effect, improves the life-span of device.
For addressing the above problem, the invention provides a kind of formation method of nmos device, described method comprises:
Semiconductor substrate is provided;
Form successively gate dielectric layer and gate electrode on described semiconductor substrate surface, wherein, the Semiconductor substrate that is positioned at described gate electrode both sides is respectively source region and drain region;
In described source region and drain region, inject successively indium ion and boron ion, form pocket area;
Wherein, described indium ion dopant dose is 0.5E13～2E13/cm 2Described boron ion doping dosage is 0.5E13～4E13/cm 2
Optionally, described nmos device is used for imput output circuit.
Optionally, the drain saturation current of described nmos device is 0.49mA/ μ m～0.59mA/ μ m.
Optionally, during described pocket area formed, the Implantation Energy of indium ion was 50Kev～70Kev, and the Implantation Energy of boron ion is 7Kev～15Kev.
Optionally, the implant angle scope of described indium ion and boron ion is: with perpendicular to 0 °～45 ° of the normal direction angles of semiconductor substrate surface.
Optionally, the implant angle of described indium ion and boron ion is: with perpendicular to 30 ° of the normal direction angles of semiconductor substrate surface.
Optionally, described NMOS formation method also comprises, injects phosphonium ion in the source region and the drain region that are positioned at above the described pocket area, forms light doping section.
Optionally, during described lightly doped region formed, the Implantation Energy of phosphonium ion was 10Kev～15Kev.
Optionally, described gate dielectric layer is silicon dioxide.
The present invention also provides a kind of and forms each formed nmos device in the method by described nmos device.
Compared with prior art, such scheme has the following advantages: the technical program is by optimizing the doping ion dose scope that forms bag structure and light doping section, respectively the dosage range of doping ion is adjusted, from the indium ion dosage range of prior art: 3.5E13～5E13/cm 2, boron ion dose scope: 2E13～6E13/cm 2, phosphonium ion dosage range: 3E14～5.5E14/cm 2Be reduced to indium ion dosage range: 0.5E13～2E13/cm 2Boron ion dose scope: 0.5E13～4E13/cm 2Phosphonium ion dosage range: 1E14～2.5E14/cm 2Described inventive method can suppress thermoelectronic effect, improves the life-span of nmos device, with existing dopant dose scope relatively, formed nmos device Service life 1.4～2.5 times.
Description of drawings
Fig. 1 is the nmos device schematic diagram that has bag structure in the prior art;
Fig. 2 is that nmos device of the present invention forms the method flow schematic diagram;
Fig. 3 to Fig. 8 is the cross-sectional view of the nmos device formation method of one embodiment of the invention;
Fig. 9 and Figure 10 are that the nmos device Performance Ratio of one embodiment of the invention and prior art gained is than schematic diagram.
Embodiment
Inventor's discovery, in existing manufacture craft, the nmos device in input and output (I/O) circuit, thermoelectronic effect is obvious especially.Reason is, thin gate dielectric layer than core circuit region, thick gate dielectric layer in the imput output circuit more easily is subject to thermionic injury, because hot electron is generally direct tunnelling (direct tunneling) when passing through thin gate dielectric layer, and direct tunnelling can not cause the electrical variation of gate dielectric layer, and thermoelectronic effect is little on the impact of device.And hot electron can be caused the electrical variation of gate dielectric layer, thereby damage the nmos device of thick gate dielectric layer by gate dielectric layer institute trap when passing through thick gate dielectric layer, affects the device performance in input and output (I/O) circuit.
The bag structure of the nmos device in existing formation input and output (I/O) circuit and the doping ion dose scope of light doping section are excessive, are necessary to be optimized, with further raising device lifetime.Experiment showed, that the dopant dose by reducing by three kinds of ion indiums, phosphorus and boron arrives certain optimization range, can suppress better thermoelectronic effect, and then improve device lifetime.
The inventive method significantly suppresses thermoelectronic effect by optimizing the ion doping dosage range, has improved the nmos device life-span.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention.Therefore the present invention is not subjected to the restriction of following public implementation.
Method provided by the invention is not only applicable to nmos device, is applicable to integrated nmos device circuit yet, is particularly suitable for imput output circuit.
Fig. 2 is the formation method flow schematic diagram of the nmos device of one embodiment of the invention, as shown in Figure 2, comprising:
Execution in step S101 provides Semiconductor substrate;
Execution in step S102, B Implanted ion in described Semiconductor substrate forms P type trap and channel region;
Execution in step S103 forms gate dielectric layer and gate electrode successively on described semiconductor substrate surface, wherein, the Semiconductor substrate that is positioned at described gate electrode both sides is respectively source region and drain region;
Execution in step S104 injects indium ion and boron ion successively in described source region and drain region, form pocket area;
Execution in step S105 injects phosphonium ion in the source region and the drain region that are positioned at above the described pocket area, forms light doping section;
Execution in step S106 forms side wall at gate dielectric layer and gate electrode both sides;
Execution in step S107 mixes deeply to described source region and drain region, forms source electrode and drain electrode.
Wherein, the nmos device in the technical solution of the present invention is for being used for the nmos device of imput output circuit, and the scope of the drain saturation current of described nmos device is 0.49mA/ μ m～0.59mA/ μ m.
Fig. 3 to Fig. 8 is the cross-sectional view of the nmos device formation method of one embodiment of the present of invention, is elaborated below in conjunction with accompanying drawing.
Continuation is with reference to figure 2, and execution in step S101 as shown in Figure 3, provides Semiconductor substrate 101.Wherein, be formed with isolated groove in the described Semiconductor substrate 101, and with the insulating material of silica and so on isolated groove filled.Be deposited on silicon semiconductor substrate 101 lip-deep unnecessary insulating material with methods such as chemico-mechanical polishings (CMP), to form isolation trench structure 102.
Also can adopt the selective oxidation method (LOCOS) of Semiconductor substrate 101 to replace isolation trench structure 102, can play equally the effect of isolation.
Described Semiconductor substrate 101 can be silicon or SiGe, also can be silicon-on-insulator (SOI), perhaps can also comprise other material, such as III-V compounds of group such as GaAs.
Execution in step S102 at described Semiconductor substrate 101 interior B Implanted ions, forms P type trap and channel region.Continuation is with reference to figure 3, at the acceleration energy and about 3.0 * 10 of 300Kev 13/ cm 2Dosage under, the boron ion is injected in the Semiconductor substrate 101, thereby forms P type trap 103; Then, at the acceleration energy and about 5.0 * 10 of 30Kev 12/ cm 2Dosage under, the B Implanted ion is at channel region (among the figure indicate), with adjusting threshold voltage.
Execution in step S103 forms gate dielectric layer and gate electrode successively on described semiconductor substrate surface, wherein, the Semiconductor substrate that is positioned at described gate electrode both sides is respectively source region and drain region.
Concrete process is: as shown in Figure 4, at first, surface in described Semiconductor substrate 101 forms gate dielectric layer 104, described gate dielectric layer 104 is silicon dioxide, thickness is tens of to the hundreds of dust, and its deposition process can be conventional vacuum coating technology, for example boiler tube thermal oxidation, ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technique, the present embodiment adopts the boiler tube thermal oxidation technology.
Then, make gate electrode layer 105 at gate dielectric layer 104, described gate electrode layer 105 is for being polysilicon, and to several thousand dusts, its formation method is low-pressure chemical vapor phase deposition (LPCVD) to the thickness of described gate electrode layer 105 between hundreds of.
At last, utilize the resist mask, gate dielectric layer 104 and gate electrode layer 105 are carried out graphically, to form gate dielectric layer 104 and gate electrode 105.So far, the nmos device structure of formation as shown in Figure 4.
After gate electrode 105 forms, be positioned at the Semiconductor substrate part of described gate electrode 105 both sides, be respectively source region and drain region.
Execution in step S104 injects indium ion and boron ion successively in described source region and drain region, form pocket area.
Specifically comprise, as shown in Figure 5, utilize gate electrode 105 as mask, at acceleration energy and the about 0.5E13～2E13/cm of 50Kev～70Kev 2Dosage under, in described source region and drain region, inject indium ion, the pocket area 106 of mixing to form indium; Then, continue to utilize gate electrode 105 as mask, under the acceleration energy of 7Kev～15Kev and approximately 0.5E13～4E13/cm 2Dosage under, B Implanted ion in described source region and drain region is to form boron doped pocket area 107.So far, formation has two kinds of ions, the pocket area of indium ion and boron ion doping.
The angular range of described injection indium ion and boron ion is: with perpendicular to 0 °-45 ° of the normal direction angles of semiconductor substrate surface, be preferably 30 ° direction.
Because implant angle can be, therefore forming pocket area may be to the extension under the gate dielectric layer 104, and pocket area flushes with gate dielectric layer 104 only for illustrating explanation among Fig. 5.The periphery that general pocket area is positioned at described lightly doped region namely surrounds described lightly doped region.
The indium ion dosage that the present embodiment adopts is 1.5E13/cm 2, the boron ion dose is 2.0E13/cm 2, the dosage 2.0E13/cm of phosphonium ion 2
Execution in step S105 injects phosphonium ion in the source region and the drain region that are positioned at above the described pocket area, forms light doping section.
Specifically comprise: as shown in Figure 6, utilize gate electrode 105 and gate dielectric layer 104 as mask, at acceleration energy and the about 1E14～2.5E14/cm of 10Kev～15Kev 2Dosage under, in described source region and drain region, inject phosphonium ion, to form the pocket area 108 of phosphorus doping, it injects degree of depth is tens of to the hundreds of dust.
As an embodiment, the implantation dosage of the phosphonium ion of choosing is 2.0E14/cm 2
At last, after described lightly doped region 108 forms, described Semiconductor substrate 101 is heat-treated, the phosphonium ion of lightly doped region is occured vertically and horizontal diffusion, its part is diffused in the Semiconductor substrate 101 of gate electrode 105 belows, form light dope source electrode and lightly doped drain.
Execution in step S106 forms side wall at gate dielectric layer and gate electrode both sides.As shown in Figure 7, silicon oxide deposition is with covering grid electrode 105 and Semiconductor substrate 101.
Specifically comprise: form the silicon oxide layer (not shown) in described Semiconductor substrate 101, the present embodiment is silica material, generation type can be low-pressure chemical vapor phase deposition (LPCVD), thickness is higher than the height of described gate electrode 105, and described dielectric layer also can be selected oxide layer-silicon nitride-oxide layer (ONO) structure.Described dielectric layer is returned (etch back) technique at quarter, form side wall 109 in described gate electrode 105 both sides.Described side wall act as grill-protected electrode 105.
Execution in step S107 mixes deeply to described source region and drain region, forms source electrode and drain electrode.
Specifically comprise: as shown in Figure 8, on described Semiconductor substrate 101 surfaces, take gate electrode as mask, Implantation is carried out in source region and drain region, form source electrode 111 and drain electrode 112.The ion type is N-shaped in the embodiment of the invention, such as phosphorus, arsenic, antimony.The ion dose that described source electrode, drain electrode are injected is 10 14～10 15/ cm 2The order of magnitude, ion energy are 10 to 100Kev.
Formation method based on above-mentioned nmos device has formed nmos device of the present invention, comprising: Semiconductor substrate; Be formed at successively gate dielectric layer and gate electrode on the described Semiconductor substrate; Be formed at respectively source electrode and drain electrode in the described gate electrode semiconductor substrates on two sides; Be formed at the side wall of described gate electrode both sides; Be formed at the lightly doped region in described source region and the drain region, the doping ion is phosphonium ion; Be positioned at the pocket area under the described lightly doped region, described pocket area is by doped indium ion, boron ion form successively.Wherein, the dosage of phosphonium ion doping is 1E14～2.5E14/cm 2, the dosage that indium ion mixes is 0.5E13～2E13/cm 2, the dosage of boron ion doping is 0.5E13～4E13/cm 2
The technical program is adjusted the dosage range of doping ion respectively, from the indium ion of prior art: 3.5E13～5E13/cm by optimizing the scope of doping ion dose 2Boron ion: 2E13～6E13/cm 2Phosphonium ion: 3E14～5.5E14/cm 2Be reduced to indium ion: 0.5E13～2E13/cm 2Boron ion: 0.5E13～4E13/cm 2Phosphonium ion: 1E14～2.5E14/cm 2Described inventive method can suppress thermoelectronic effect, improves the life-span of nmos device, with existing dopant dose scope relatively, formed nmos device Service life 1.4～2.5 times.
Below take experimental data as example, technical solution of the present invention is described further.
Choose three kinds of formed nmos devices of different dopant amount, measure corresponding drain saturation current value (Idsat) and the ratio (Isub/Id) of substrate current and leakage current, and to the above-mentioned data Mathematical Fitting of being correlated with, obtain such as Fig. 9 and corresponding relation schematic diagram shown in Figure 10, described three kinds of dopant doses are:
1. indium ion dosage: 5E13/cm 2, phosphonium ion dosage: 5E14/cm 2, the dopant dose of expression prior art is interval, represents with circle in the schematic diagram;
2. indium ion dosage: 3.5E13/cm 2, phosphonium ion dosage: 5E14/cm 2, the dopant dose of expression prior art is interval, represents with square in the schematic diagram;
3. indium ion dosage: 2E13/cm 2, phosphonium ion dosage: 2.5E14/cm 2, the dopant dose of expression the inventive method is interval, represents with triangle in the schematic diagram.
Concrete, abscissa is expressed as boron ion doping dosage among Fig. 9, and corresponding ordinate is expressed as drain saturation current; Abscissa is expressed as boron ion doping dosage among Figure 10, and corresponding ordinate is expressed as the ratio of substrate current and leakage current.
Wherein, the ratio of substrate current and leakage current (Isub/Id) is as the parameter of weighing device lifetime (TTF), and the corresponding relation that is inversely proportional to of relation between the two is expressed as follows:
TTF～A*(Isub/Id) -3
Continuation at first, is chosen same drain saturation current value with reference to figure 9 and Figure 10, can obtain three kinds of corresponding dopant doses, comprises the dosage of boron ion; Then, the value of the Isub/Id of the relatively more corresponding nmos device that forms, the i.e. device lifetime of more described device; At last, can find, the Isub/Id of the interval nmos device that obtains of the dopant dose at place of the present invention all is lower than the Isub/Id of the nmos device that the dopant dose interval of prior art obtains, and namely the dopant dose at the place of the present invention interval nmos device life-span that obtains all is higher than the nmos device life-span that the dopant dose interval of prior art obtains.
As an embodiment, choosing the drain saturation current value is 0.52mA/ μ m, and dopant dose is respectively with corresponding Isub/Id value:
A. indium ion dosage: 5E13/cm 2, phosphonium ion dosage: 5E14/cm 2, boron ion dose: 2.8E13/cm 2, Isub/Id:2.7E-3;
B. indium ion dosage: 3.5E13/cm 2, phosphonium ion dosage: 5E14/cm 2, boron ion dose: 3.7E13/cm 2, Isub/Id:2.5E-3;
C. indium ion dosage: 5E13/cm 2, phosphonium ion dosage: 5E14/cm 2, boron ion dose: 2.5E13/cm 2, Isub/Id:2.4E-3.
In summary, the Isub/Id of the dopant dose nmos device that c obtains at place of the present invention is 2.4E-3, all be lower than the Isub/Id (2.7E-3,2.5E-3) of the nmos device that the dopant dose interval of prior art obtains, i.e. nmos device life-span of obtaining of the dopant dose interval that all is higher than prior art of the interval nmos device life-span that obtains of the dopant dose at place of the present invention.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.

Claims (9)

1. the formation method of a nmos device, described method comprises:
Semiconductor substrate is provided;
Form successively gate dielectric layer and gate electrode on described semiconductor substrate surface, the Semiconductor substrate that is positioned at described gate electrode both sides is respectively source region and drain region;
In described source region and drain region, inject successively indium ion and boron ion, form pocket area;
It is characterized in that, described indium ion dopant dose is 0.5E13 ~ 2E13/cm 2, the Implantation Energy of indium ion is 50Kev～70Kev; Described boron ion doping dosage is 0.5E13 ~ 4E13/cm 2, the Implantation Energy of boron ion is 7Kev～15Kev.
2. the formation method of nmos device according to claim 1 is characterized in that, described nmos device is used for imput output circuit.
3. the formation method of nmos device according to claim 2 is characterized in that, the drain saturation current of described nmos device is 0.49mA/ μ m ~ 0.59mA/ μ m.
4. the formation method of nmos device according to claim 1 is characterized in that, the implant angle scope of described indium ion and boron ion is: with perpendicular to 0 ° ~ 45 ° of the normal direction angles of semiconductor substrate surface.
5. the formation method of nmos device according to claim 4 is characterized in that, the implant angle of described indium ion and boron ion is: with perpendicular to 30 ° of the normal direction angles of semiconductor substrate surface.
6. the formation method of nmos device according to claim 1 also is included in the source region and the drain region that are positioned at described pocket area top and injects phosphonium ion, forms light doping section.
7. the formation method of nmos device according to claim 6 is characterized in that, during described lightly doped region formed, the Implantation Energy of phosphonium ion was 10Kev ~ 15Kev.
8. the formation method of nmos device according to claim 1 is characterized in that, described gate dielectric layer is silicon dioxide.
9. one kind such as each formed nmos device in the claim 1 to 8.
CN 200910201193 2009-12-15 2009-12-15 NMOS (N-channel Metal Oxide Semiconductor) device and forming method thereof Active CN102097320B (en)

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