CN102044434A - Method for manufacturing MOS transistor - Google Patents
Method for manufacturing MOS transistor Download PDFInfo
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- CN102044434A CN102044434A CN2009101974556A CN200910197455A CN102044434A CN 102044434 A CN102044434 A CN 102044434A CN 2009101974556 A CN2009101974556 A CN 2009101974556A CN 200910197455 A CN200910197455 A CN 200910197455A CN 102044434 A CN102044434 A CN 102044434A
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Abstract
The invention discloses a method for manufacturing a metal oxide semiconductor (MOS) transistor. The method comprises the following steps of: providing a semiconductor substrate; forming a gate dielectric layer and a gate on the semiconductor substrate in turn; forming a side wall on the two sides of the gate; performing source/drain injection; forming a source and a drain in the semiconductor substrate; and forming a lightly doped drain (LDD) structure in the semiconductor substrate below the side wall. In the invention, the standard process of the MOS transistor is locally adjusted, so that low concentration doping is realized in a related region while the source/drain injection is performed, the LDD structure is formed and process complexity is reduced.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of manufacture method of MOS transistor.
Background technology
With the raising of integrated circuit integrated level, device size is progressively scaled, and characteristic size has reached the 32nm magnitude at present.Metal oxide semiconductor field effect tube (MOS) is modal semiconductor device, is the elementary cell that constitutes various complicated circuits.MOS transistor basic structure comprises three main region: source electrode (source), drain electrode (drain) and gate electrode (gate).Wherein source electrode and drain electrode according to the type of device difference, can be divided into n type doping (NMOS) and p type doping (PMOS) by highly doped formation.
In the scaled process of device, drain voltage does not reduce thereupon, this just causes the increase of the channel region electric field between source/drain electrode, under the highfield effect, electronics can accelerate to the speed than much higher times of heat movement speed between twice collision, be called as hot electron owing to kinetic energy is very big, thereby cause thermoelectronic effect (hot electron effect).This effect belongs to the small-size effect of device, can cause that hot electron injects to gate dielectric layer, forms gate electrode electric current and substrate current, influences the reliability of device and circuit.
In order to overcome thermoelectronic effect, have multiplely to the improving one's methods of mos transistor structure, for example two injecting structure, buried channel structure, discrete grid structures, bury drain structure etc.; Wherein study morely and practical value is bigger a kind of be lightly doped drain (lightly doped drain:LDD) structure.The effect of LDD structure is to reduce electric field, can significantly improve thermoelectronic effect.
Although the LDD structure has significant effect to reducing thermoelectronic effect, also there are some shortcomings.Such as causing the resistance between source/drain electrode to increase, saturation current is reduced, and then cause that the device reaction speed descends.In addition, the LDD structure also makes the MOS transistor manufacturing process more complicated.
In the existing integrated manufacturing technology, to the metal-oxide-semiconductor of channel length less than 1.25 μ m, its manufacturing process mainly may further comprise the steps, as shown in Figures 1 to 4: with reference to figure 1, form gate dielectric layer 110 and grid 120 successively on Semiconductor substrate 100; With reference to figure 2, lightly doped LDD injection is carried out in source region 130 and drain region 140, and the injection ion is spread in described Semiconductor substrate 100 by annealing process; As shown in Figure 3, form side wall 150 in described grid 120 both sides; As shown in Figure 4, carry out heavily doped source/drain electrode and inject, form heavily doped region 170,180, because the barrier effect of described side wall 150, the lightly doped region that forms when the zone of described side wall 150 belows is still injected for LDD constitutes LDD structure 130a and 140a.The LDD injection is injected to separate with source/drain electrode and is carried out in the said method, is to form the LDD structure, has increased following processing step at least: the process that a photoetching, primary ions are injected and once removed photoresist.
About the in the industry cycle existing many discussions of the generation type of LDD structure, publication number is that 20080217693 U.S. Patent application has proposed a kind of new MOS transistor device architecture, improve puncture voltage by adjusting device architecture, and reduced the quantity of required mask in the technology.But wherein the formation of LDD structure still need be carried out once independently ion injecting process, fails production process is made simplification.
For reducing the complexity of manufacturing process, reduce production cost, need a kind of new manufacturing process of exploitation, easier formation LDD structure.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of MOS transistor, to reduce the process complexity that forms the LDD structure.
For addressing the above problem, the invention provides a kind of manufacture method of MOS transistor, comprise following key step:
Semiconductor substrate is provided, on described Semiconductor substrate, forms gate dielectric layer and grid successively;
Form side wall in described grid both sides;
Carry out source/drain electrode and inject, in Semiconductor substrate, form source electrode and drain electrode, form the LDD structure in the Semiconductor substrate below side wall simultaneously.
Optionally, the distribution of described LDD structure and doping content are controlled by the thickness of regulating described side wall.
Optionally, forming side wall in described grid both sides comprises: form first dielectric layer at described gate dielectric layer and gate surface; On described first dielectric layer, form second dielectric layer; Return and carve described first dielectric layer and second dielectric layer, form side wall; Remove the second dielectric layer part in the side wall.
Optionally, forming side wall in described grid both sides comprises: form first dielectric layer at described gate dielectric layer and gate surface; Return and carve described first dielectric layer, form side wall.
Optionally, the thickness of described first dielectric layer is 100 to 1000 dusts.
Optionally, the material of described first dielectric layer is silicon nitride or silica.
Optionally, the material of described second dielectric layer is the insulating material different with the dielectric layer material, is selected from silica or silicon nitride.
Optionally, the material of described second dielectric layer is a silica, removes described second dielectric layer and adopts wet etching, and the solution that uses in the described wet etching is hydrofluoric acid.
Optionally, the material silicon nitride of described second dielectric layer is removed described second dielectric layer and is adopted wet etching, and the solution that uses in the described wet etching is phosphoric acid.
Optionally, the dosage that injects of described source/drain electrode is 10
14～10
15/ cm
2The order of magnitude.
Optionally, the type of described MOS transistor is NMOS.
It is optionally, described that the source/drain electrode injection ionic type is arsenic or antimony.
Optionally, the type of described MOS transistor is PMOS.
It is optionally, described that the source/drain electrode injection ionic type is a boron.
Compared with prior art, such scheme has the following advantages: adjust by the part to MOS crystal standard technology, form the LDD structure when source/drain electrode is injected, reduced process complexity.
Can also control the concentration and the distribution of dopant ion in the LDD structure by the thickness of regulating side wall, realize the technique effect identical with existing technology.
Description of drawings
Fig. 1 to Fig. 4 is the cross-sectional view of the manufacture method of prior art MOS transistor;
Fig. 5 is the schematic flow sheet of manufacture method of the MOS transistor of embodiment of the present invention;
Fig. 6 to Figure 10 is the cross-sectional view of the nmos pass transistor manufacture method of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Method provided by the invention is not only applicable to the manufacturing of MOS transistor single tube device, is applicable to integrated MOS transistor circuit, the particularly characteristic size MOS transistor integrated circuit below 130nm yet.Described MOS transistor can be PMOS transistor or the nmos pass transistor among the CMOS.
As mentioned before, when the conducting channel contraction in length to a certain degree, be the electric field strength that reduces the gate edge zone, existing MOS transistor manufacturing process forms the LDD structure in source region and drain region.Because the doping content of LDD structure and the doping content of source-drain area differ greatly, and are generally two orders of magnitude, so LDD injects and source/drain electrode is injected and need be carried out respectively, has increased process complexity thus.
For this reason, based on existing MOS transistor manufacturing process flow, it is done local adjustment, make it realize that when source/drain electrode is injected LDD injects, form the LDD structure in the specific region,, reduce the complexity of existing technology so that under the prerequisite that does not influence device performance.
About the technological process adjustment to the MOS standard technology, Fig. 5 has indicated the process chart of the specific embodiment of the present invention.Method provided by the invention is applicable to the manufacturing of MOS single tube device in the integrated circuit, but method of the present invention should be limited in the manufacturing process of MOS single tube device, if relate to the situation that forms MOS transistor integrated device or needs formation LDD structure in other technologies, method of the present invention also can well be suitable for.
As shown in Figure 5, execution in step S510 provides Semiconductor substrate, forms gate dielectric layer and grid on described Semiconductor substrate successively; Execution in step S520 forms side wall in described grid both sides; Execution in step S530 carries out source/drain electrode and injects, and forms source electrode and drain electrode in Semiconductor substrate, forms the LDD structure in the Semiconductor substrate below side wall simultaneously.
Fig. 6 to Figure 10 is the cross-sectional view of the nmos pass transistor manufacture method of first embodiment of the invention.
With reference to figure 5 and Fig. 6, execution in step S510 provides Semiconductor substrate, forms gate dielectric layer and grid on described Semiconductor substrate successively.The Semiconductor substrate 600 of P type at first is provided, certain isolation structure (not shown) is arranged on the described Semiconductor substrate 600, as silica etc.Silicon or SiGe that described Semiconductor substrate 600 can be monocrystalline, polycrystalline or non crystalline structure also can be silicon-on-insulators (SOI).The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.
Form gate dielectric layer 610 on described Semiconductor substrate 600 surfaces, the material of gate dielectric layer described in the present embodiment 610 is a silica, thickness is tens of to the hundreds of dust, its formation method can be conventional vacuum coating technology, for example boiler tube thermal oxidation, ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, present embodiment adopts the boiler tube thermal oxidation technology.
On described gate dielectric layer 610, form the grid layer (not shown) then, the material of described grid layer can be polysilicon or metal, select n type doped polycrystalline silicon for use at this, its formation method is low-pressure chemical vapor phase deposition (LPCVD), dopant ion is a phosphorus, this method is those skilled in the art's a common practise, and grid layer thickness is between hundreds of extremely several thousand dusts.Then described grid layer is graphically formed the grid 620 of nmos pass transistor.So far, the device architecture of formation as shown in Figure 6.Above technological process is all consistent with existing MOS technological process.
With reference to figure 5 and Fig. 7 to Fig. 9, execution in step S520 forms side wall in described grid both sides.In the present embodiment, at first, form first dielectric layer 630 as shown in Figure 7 on described Semiconductor substrate 600 and grid 620, described first dielectric layer 630 covers the surface of whole Semiconductor substrate 600 and grid 620.The material of described first dielectric layer 630 can be silicon nitride or silica, and its formation method is low-pressure chemical vapor phase deposition (LPCVD), plasma enhanced CVD (PECVD).The thickness of described first dielectric layer 630 is adjustable, generally between hundreds of between 1,000 dusts.Described first dielectric layer 630 injects at follow-up ion and serves as the barrier layer.
With reference to figure 8, on described first dielectric layer 630, form the second dielectric layer (not shown), its material is the insulating material that is different from described first dielectric layer 630.Select silica for use as first dielectric layer 630, second dielectric layer then can be selected silicon nitride for use; Select silicon nitride for use as first dielectric layer 630, second dielectric layer then can be selected silica for use.The formation method of described second dielectric layer is identical with first dielectric layer 630, and its thickness is higher than gate height.Afterwards described first dielectric layer 630 and second dielectric layer are returned (etch back) technology at quarter, form side wall 640a in described grid 620 both sides, in the present embodiment, described side wall 640a comprises L shaped first dielectric layer 630 of described grid 620 both sides and second dielectric layer on first dielectric layer 630.At this moment, all remove with second dielectric layer, first dielectric layer 630 and the gate dielectric layer 610 of exterior domain, expose described Semiconductor substrate 600 at grid 620 and side wall 640a.The process and the existing technology that form side wall are similar, have only increased the forming process of described first dielectric layer 630.
With reference to figure 9, utilize wet-etching technology to remove second dielectric layer among the described side wall 640a, form side wall 640b.If the material of second dielectric layer is a silicon nitride, etching solution is selected phosphoric acid for use so; If the material of second dielectric layer is a silica, etching solution is selected hydrofluoric acid for use so.Because described first dielectric layer 630 is different with the material of second dielectric layer, utilize the high selectivity of wet etching, the second remaining dielectric layer can be removed fully, and first dielectric layer 630 is not caused damage substantially.After wet-etching technology is finished, device architecture as shown in Figure 9, the mos transistor structure that forms with routine is difference to some extent, the thickness of side wall 640b (being the first remaining dielectric layer 630 in the present embodiment) is less than the thickness of prior art side wall, carrying out can not stopping fully when ion injects that dopant ion enters in the Semiconductor substrate 600 below the side wall 640b, the technical program also utilizes this point to form the LDD structure just.In other embodiment of the technical program, the step that forms side wall also can be only to form first dielectric layer 630 at described gate dielectric layer 610 and grid 620 surfaces, and do not form second dielectric layer, pass through back afterwards carving technology and form side wall in grid 620 both sides, described side wall is made of the first L shaped dielectric layer.
As Fig. 5 and shown in Figure 10, execution in step S530 carries out source/drain electrode and injects, and forms source electrode and drain electrode in Semiconductor substrate, forms the LDD structure in the Semiconductor substrate below side wall simultaneously.Specifically comprise: described Semiconductor substrate 600 is carried out source/drain electrode inject, form source electrode 660s, drain electrode 660d respectively in described grid 620 both sides, described source electrode 660s comprises the LDD structure 650s that is positioned at described side wall 640b below, and described drain electrode 660d comprises the LDD structure 650d that is positioned at described side wall 640b below.Be nmos pass transistor in the present embodiment, the ionic type of injection is the n type, and as arsenic (As) or antimony (Sb), injecting ion dose is 10
14～10
15/ cm
2The order of magnitude.Because side wall 640b zone comprises the gate dielectric layer 610 and first dielectric layer, and thickness is suitable, the injection ion can be arrived in the substrate 600 of below, side wall 640b zone, but because the effect on the gate dielectric layer 610 and first dielectric layer barrier layer of performance when injecting, the dopant ion that therefore low concentration is only arranged below side wall 640b zone, this zone is positioned at grid 620 both sides, the LDD structure of formation source/drain electrode.The difference of above correlation step and existing technological process is: in the existing technology, LDD injects and source/drain electrode injection is carried out in two steps, present embodiment then only carries out source/drain electrode and injects, utilize the gate dielectric layer 610 and first dielectric layer 630 as the low concentration doping of barrier layer realization simultaneously to the relevant range, form the LDD structure, simplified technological process.
In the source/and processing step that drain ion is injected, for forming desirable LDD structure, the thickness of described side wall (being first dielectric layer in the present embodiment) is a key factor.Although in the source/barrier layer when drain electrode is injected served as jointly by the gate dielectric layer 610 and first dielectric layer 630, but because the threshold voltage of 610 pairs of MOS transistor of gate dielectric layer has material impact, its thickness can not regulated at will, generally speaking the thinner thickness of gate dielectric layer 610 in addition, very limited to the barrier effect that injects ion, therefore main barrier layer is first dielectric layer 630.In addition, owing to will form the source/drain electrode of target doping content and distribution, the dosage that described source/drain electrode is injected can not regulated at will.And as previously mentioned, the thickness of described first dielectric layer 630 can be regulated, and its thickness range is 100 to 1000 dusts, its thickness is big more, barrier effect to the injection ion is strong more, and the degree of depth of injecting ion in Semiconductor substrate 600 is shallow more, and corresponding doping content is then lower; Its thickness is more little, and the degree of depth of injecting ion in Semiconductor substrate 600 is dark more, and corresponding doping content is then higher.Therefore, first dielectric layer 630 that is positioned at the LDD superstructure is equivalent to the mask that source/leakage is injected, and described first dielectric layer, 630 thickness are regulated doping content and the distribution situation that can effectively control the LDD structure.
After the source/drain electrode injection is finished, as operations such as cleanings, just form the nmos device of gained through necessary subsequent treatment.
The above first embodiment is the manufacturing process of nmos pass transistor, and the transistorized related procedure of brief description PMOS is with as the second embodiment of the present invention.The transistorized typical process flow of PMOS is consistent with first embodiment, only in substrate type and source/and drain electrode injects aspect such as ionic type difference to some extent.For the PMOS transistor, select the N type semiconductor substrate for use; The ionic type of selecting for use when source/drain electrode is injected is the p type, for example boron (B).
According to the design rule of integrated circuit, the size of the every structure of device can be scaled.Main purpose of the present invention is to provide the integrated method of a kind of technology to simplify the technological process that forms LDD structure metal-oxide-semiconductor device, therefore the concrete process of device is not too much related to.
The above is two specific embodiments of the present invention, forms nmos pass transistor and PMOS transistor respectively.The present invention adjusts by the part to the MOS standard technology, increase the deposit and the wet etching of a dielectric layer, cancel LDD and injected required photoetching, ion processing step such as inject, remove photoresist, simplified technological process, by dielectric layer in the source/barrier function when drain electrode is injected realizes low concentration doping in the relevant range, form the LDD structure, reduced process complexity.
But also can realize the technique effect identical by the thickness of side wall being regulated doping content and the distribution of controlling the LDD structure with existing technology.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. the manufacture method of a MOS transistor is characterized in that, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, forms gate dielectric layer and grid successively;
Form side wall in described grid both sides;
Carry out source/drain electrode and inject, in Semiconductor substrate, form source electrode and drain electrode, form the LDD structure in the Semiconductor substrate below side wall simultaneously.
2. the manufacture method of MOS transistor according to claim 1 is characterized in that, the distribution of described LDD structure and doping content are controlled by the thickness of regulating described side wall.
3. the manufacture method of MOS transistor according to claim 1 is characterized in that, forms side wall in described grid both sides and comprises: form first dielectric layer at described gate dielectric layer and gate surface; On described first dielectric layer, form second dielectric layer; Return and carve described first dielectric layer and second dielectric layer, form side wall; Remove the second dielectric layer part in the side wall.
4. the manufacture method of MOS transistor according to claim 1 is characterized in that, forms side wall in described grid both sides and comprises: form first dielectric layer at described gate dielectric layer and gate surface; Return and carve described first dielectric layer, form side wall.
5. according to the manufacture method of claim 3 or 4 described MOS transistor, it is characterized in that the thickness of described first dielectric layer is 100 dust to 1000 dusts.
6. according to the manufacture method of claim 3 or 4 described MOS transistor, it is characterized in that the material of described first dielectric layer is silicon nitride or silica.
7. the manufacture method of MOS transistor according to claim 3 is characterized in that, described second dielectric layer is different with the first dielectric layer material, is selected from silica or silicon nitride.
8. the manufacture method of MOS transistor according to claim 6 is characterized in that, the material of described second dielectric layer is a silica, and second dielectric layer of removing in the side wall partly adopts wet etching, and the solution that uses in the described wet etching is hydrofluoric acid.
9. the manufacture method of MOS transistor according to claim 6 is characterized in that, the material silicon nitride of described second dielectric layer, and second dielectric layer of removing in the side wall partly adopts wet etching, and the solution that uses in the described wet etching is phosphoric acid.
10. the manufacture method of MOS transistor according to claim 1 is characterized in that, the dosage that described source/drain electrode is injected is 10
14～10
15/ cm
2The order of magnitude.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104064462A (en) * | 2013-03-19 | 2014-09-24 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104064462A (en) * | 2013-03-19 | 2014-09-24 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
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