CN101789447A - Metal oxide semiconductor (MOS) transistor and formation method thereof - Google Patents
Metal oxide semiconductor (MOS) transistor and formation method thereof Download PDFInfo
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- CN101789447A CN101789447A CN200910045900A CN200910045900A CN101789447A CN 101789447 A CN101789447 A CN 101789447A CN 200910045900 A CN200910045900 A CN 200910045900A CN 200910045900 A CN200910045900 A CN 200910045900A CN 101789447 A CN101789447 A CN 101789447A
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Abstract
The invention provides a metal oxide semiconductor (MOS) transistor and a formation method thereof. The formation method of the transistor comprises the following steps of: forming an isolated well on a semiconductor substrate through repeated ion injection; carrying out reversed-phase ion injection on the isolated well; and forming a grid electrode, a source region and a drain region of the MOS transistor on the isolated well. The invention reduces the doping concentration nearby the interface of the source and the drain regions and the isolated well so as to weaken the junction capacitance and further reduce the influence of the parasitic junction capacitance on transistor devices, and also keeps the doping concentration on the surface of the isolated well and nearby the interface of the isolated well and the substrate so as to avoid affecting the original properties of the transistor device.
Description
Technical field
The present invention relates to a kind of MOS transistor, relate in particular to a kind of MOS transistor of carrying out the reversed phase ion injection and forming method thereof.
Background technology
The most basic device during MOS transistor is made as semiconductor is widely used in the various integrated circuits, and the doping type difference during according to main charge carrier and manufacturing is divided into PMOS and NMOS.As shown in Figure 1 to Figure 3, be the main forming process of a typical PMOS.
At first, on Semiconductor substrate 100, inject N trap 101 of formation by ion earlier as Fig. 1;
As Fig. 2, form oxide layer 102 and polysilicon layer 103 on the surface of N trap 101, and etched portions is as grid then;
Last as Fig. 3, formation p type island region territory 104 in the N trap 101 of the both sides of grid is respectively as source region and the drain region of PMOS.
And in actual applications, the MOS device is when forming isolation well, the single ion injects the doping content distribution curve that obtains and trends towards a Gaussian Profile, usually way is to carry out repeatedly the ion injection to obtain a concentration profile with the doping depth variation as shown in Figure 4, crest A point, B point corresponding respectively near surface and N trap near position, substrate place, trough C point is then corresponding to the interface of p type island region territory 104 and N trap 101.The doping content that crest A is ordered directly determines the threshold voltage of PMOS; The doping content that B is ordered is higher relatively then to be for fear of some transistorized second-order effects, such as when making isolation, can reduce the possibility that the N trap is punctured by electric current.
In addition, for the PMOS transistor, between P type source, drain region and the N trap, it is C point institute correspondence position, there is an equivalent junction capacitance, the big young pathbreaker who reduces junction capacitance as much as possible helps to improve the performance of transistor device circuit, and the size of this junction capacitance depends on when forming the N trap concentration of ion doping herein.In existing transistorized forming process, though repeatedly ion injects the waveform doping content distribution that can obtain the N trap, the N type doping content that C is ordered is lower relatively on every side, general order of magnitude of gap, yet the junction capacitance that this place constitutes still can't be ignored, and can influence the performance of transistor device circuit.
Summary of the invention
The problem that the present invention solves is existing transistor formation method, can't further reduce the influence of formed junction capacitance between source, zone, drain region and the isolation well, and influence the performance of transistor device circuit.
For addressing the above problem, the invention provides a kind of MOS transistor, comprising:
Semiconductor substrate with isolation well, described isolation well were carried out reversed phase ion and were injected;
Grid oxic horizon is positioned on the described isolation well;
Polysilicon gate is positioned on the described grid oxic horizon;
Source, drain region are in isolation well and lay respectively at the both sides of described polysilicon gate.
In addition, the present invention also provides a kind of formation method of MOS transistor, and concrete steps comprise:
On Semiconductor substrate, pass through repeatedly ion and inject the formation isolation well;
Described isolation well is carried out reversed phase ion to be injected;
Form grid oxic horizon and polysilicon layer on the isolation well surface;
Described grid oxic horizon of etched portions and polysilicon layer form grid;
In the isolation well of grid both sides, inject formation source, drain region by ion.
As preferred version, the Cmax degree of depth that described reversed phase ion injects be arranged at source, drain region and isolation well at the interface near.
Compared with prior art, the present invention is when forming MOS transistor, the isolation well that forms is carried out reversed phase ion to be injected, on the one hand, reduced near the at the interface doping content of source, drain region and isolation well, thereby weaken junction capacitance herein, and further reduce the influence of parasitic junction capacitance transistor device; On the other hand, the surface that has kept isolation well with and with the substrate interface place near doping content, to avoid influencing the key property of transistor device.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Parts same as the prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size in layer and zone.
Fig. 1 to Fig. 3 is an existing P MOS transistor manufacturing flow chart;
Fig. 4 is the doping content distribution map of isolation well in the existing MOS transistor;
The formation flow chart of Fig. 5 MOS transistor of the present invention;
The flow chart that Fig. 6 reversed phase ion of the present invention injects;
Fig. 7 to Figure 11 is the transistorized manufacturing process generalized section of PMOS of the present invention;
Figure 12 is the doping content distribution map that repeatedly ion of the present invention injects and reversed phase ion injects;
Figure 13 is the doping content distribution map of isolation well of the present invention;
Figure 14 to Figure 18 is the manufacturing process generalized section of nmos pass transistor of the present invention.
Embodiment
Known from background technology, in the processing procedure of MOS transistor, near the at the interface doping content with source, drain region in the isolation well has determined the size of junction capacitance in the MOS transistor, can effectively eliminate junction capacitance so reduce the doping content at this place as much as possible.Can make two kinds of opposite dopants neutralize by isolation well is carried out anti-phase doping, thereby reduce doping content herein.
The invention provides a kind of formation method of MOS transistor, its flow process as shown in Figure 5, embodiment is as follows:
S1, elder generation pass through repeatedly ion and inject the formation isolation well on Semiconductor substrate;
S2, described isolation well is carried out reversed phase ion inject;
Wherein, if form PMOS, then isolation well is the N trap, and reversed phase ion injects the dopant that is adopted can be boron ion or indium ion; If form NMOS, then isolation well is the P trap, reversed phase ion inject the dopant that adopts can be phosphonium ion or arsenic ion;
S3, form grid oxic horizon and polysilicon layer on isolation well surface;
S4, the described grid oxic horizon of etched portions and polysilicon layer form grid;
S5, formation gate lateral wall;
S6, in the isolation well of grid both sides, inject formation source, drain region by ion, and high annealing.
Wherein, if form PMOS, then in the N trap, form P type source, drain region; If form NMOS, then in the P trap, form N type source, drain region.
Describedly isolation well is carried out reversed phase ion inject, as shown in Figure 6, concrete steps are as follows:
Source, drain region and isolation well depth is at the interface determined in S21, source, the drain region default according to MOS transistor;
S22, determine that according to above-mentioned depth the doping content that reversed phase ion injects distributes;
Wherein, the CONCENTRATION DISTRIBUTION that described reversed phase ion injects, maximum dopant concentration be arranged at default source, drain region and isolation well at the interface near, the doping content at this place when being slightly less than previous repeatedly ion injection; And isolation well surface and with substrate at the interface near, the doping content of corresponding position when the order of magnitude of doping content injects much smaller than previous repeatedly ion.
S23, the doping content of injecting according to default reversed phase ion distribute, and isolation well is carried out ion inject the type opposite of doping type and isolation well;
S24, the isolation well after ion injected carry out high annealing, to repair lattice.
Fig. 7 to Figure 10 is the transistorized manufacturing process specific embodiment of a PMOS of the present invention generalized section.
As shown in Figure 7, utilize repeatedly ion to inject earlier in the presumptive area on Semiconductor substrate 100 and form N trap 101, then N trap 101 is carried out reversed phase ion and inject, and carry out high annealing, repair lattice.
As shown in Figure 8, on N trap 101, form grid oxic horizon 102 and polysilicon layer 103 successively.
As shown in Figure 9, etched portions grid oxic horizon 102 and polysilicon layer 103 form the grid of PMOS, and expose N trap 101.
As shown in figure 10, grow the sidewall of grid.
As shown in figure 11, as mask, in the N of grid both sides trap 101, carry out ion and inject to form p type island region territory 104 with polysilicon layer 103, respectively as source region and the drain region of PMOS, and high annealing.
In above-mentioned flow process, described utilization repeatedly ion is injected when forming N trap 101, doping N class material such as phosphonium ion or arsenic ion etc., it mixes with the CONCENTRATION DISTRIBUTION of injecting the degree of depth shown in Figure 12 solid line, crest A point, B point corresponding respectively near surface and N trap near position, substrate place, trough C point is then corresponding to the predetermined P type source that forms, drain region 104 and N trap 101 at the interface.
Describedly N trap 101 is carried out reversed phase ion when injecting, doping P class material such as boron ion or indium ion etc.Wherein, distribute as shown in phantom in Figure 12, and the Cmax that the P class is mixed is positioned at C point position, had been slightly less than previous repeatedly ion and injected the concentration that resultant N class is mixed, to avoid N trap 101 generation transoids with the doping content of injecting the degree of depth; And all the other positions, as A, B point, the concentration numbers magnitude that the P class is mixed is then injected the concentration that resultant N class is mixed much smaller than previous repeatedly ion.
After the reversed phase ion injection, the doping of two kinds of opposite types of N trap inside neutralizes mutually, and doping content changes as shown in figure 13, and wherein dotted line and solid line are respectively the forward and backward doping content distribution curve of reversed phase ion injection.Because in 2 positions of A, B, the concentration that the concentration numbers magnitude that the P class is mixed is mixed much smaller than the N class can be ignored so doping content changes, thereby avoid influencing performances such as the threshold voltage of follow-up formed PMOS and isolation.And,,, promptly after forming PMOS, weakened the junction capacitance at the interface of P type source, drain region and N trap so effectively reduce the doping content that C is ordered in the N trap 101 because both concentration are approaching in C point and vicinity thereof, reduce the harmful effect of junction capacitance among the PMOS thus.
Figure 14 is to the manufacturing process specific embodiment generalized section that Figure 15 shows that nmos pass transistor of the present invention.
As shown in figure 14, utilize repeatedly ion to inject earlier in the presumptive area on Semiconductor substrate 200 and form P trap 201, then P trap 201 is carried out reversed phase ion and inject, and carry out high annealing, repair lattice.
As shown in figure 15, on P trap 201, form grid oxic horizon 202 and polysilicon layer 203 successively.
As shown in figure 16, etched portions grid oxic horizon 202 and polysilicon layer 203 form the grid of NMOS, and expose P trap 201.
As shown in figure 17, grow the sidewall of grid.
As shown in figure 18, as mask, in the P of grid both sides trap 201, carry out ion and inject to form N type zone 204 with polysilicon layer 203, respectively as source region and the drain region of NMOS, and high annealing.
With the PMOS same principle, in above-mentioned flow process, doping P class material such as boron ion or indium ion etc. are injected when forming P trap 201 in described utilization repeatedly ion; When P trap 201 is carried out the reversed phase ion injection, doping N class material such as phosphonium ion or arsenic ion etc.; The doping of two kinds of opposite types of P trap 201 inside neutralizes mutually, and resulting doping content also is similar to shown in Figure 13 with the distribution curve of base depth.In 2 positions of A, B, the order of magnitude of N class doping content is much smaller than P class doping content, and the variation of doping content can be ignored, and avoids influencing performances such as the threshold voltage of follow-up formed NMOS and isolation.And in C point position, both after forming NMOS, have weakened the junction capacitance at the interface of N type source, drain region and P trap because concentration is approaching, reduce the harmful effect of junction capacitance among the NMOS thus.
According to above-mentioned manufacture method, resulting MOS transistor comprises:
Semiconductor substrate with isolation well, described isolation well were carried out reversed phase ion and were injected;
Grid oxic horizon is positioned on the described isolation well;
Polysilicon gate is positioned on the described grid oxic horizon;
Source, drain region are in isolation well and lay respectively at the both sides of described polysilicon gate.
If described transistor is PMOS, isolation well is the N trap, and reversed phase ion injects doped with boron ion or indium ion.
If described transistor is NMOS, isolation well is the P trap, and reversed phase ion injects Doping Phosphorus ion or arsenic ion.
The Cmax degree of depth that described reversed phase ion injects is arranged at the near interface of source, drain region and isolation well.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (9)
1. a MOS transistor is characterized in that, comprising:
Semiconductor substrate with isolation well, described isolation well were carried out reversed phase ion and were injected;
Grid oxic horizon is positioned on the described isolation well;
Polysilicon gate is positioned on the described grid oxic horizon;
Source, drain region are in isolation well and lay respectively at the both sides of described polysilicon gate.
2. a kind of MOS transistor as claimed in claim 1 is characterized in that, described transistor is PMOS, and isolation well is the N trap, and reversed phase ion injects doped with boron ion or indium ion.
3. a kind of MOS transistor as claimed in claim 1 is characterized in that, described transistor is NMOS, and isolation well is the P trap, and reversed phase ion injects Doping Phosphorus ion or arsenic ion.
4. as claim 2 or 3 described a kind of MOS transistor, it is characterized in that the Cmax degree of depth that described reversed phase ion injects is arranged at the near interface of source, drain region and isolation well.
5. the formation method of a MOS transistor is characterized in that, comprising:
On Semiconductor substrate, pass through repeatedly ion and inject the formation isolation well;
Described isolation well is carried out reversed phase ion to be injected;
The grid of formation MOS transistor and source, drain region on isolation well.
6. the formation method of a kind of MOS transistor as claimed in claim 5 is characterized in that, described grid and source, the drain region of on isolation well, forming, and concrete steps comprise:
Form grid oxic horizon and polysilicon layer on the isolation well surface;
Described grid oxic horizon of etched portions and polysilicon layer form grid;
In the isolation well of grid both sides, inject formation source, drain region by ion.
7. the formation method of a kind of MOS transistor as claimed in claim 6 is characterized in that, described MOS transistor is PMOS, and isolation well is the N trap, and reversed phase ion injects doped with boron ion or indium ion.
8. the formation method of a kind of MOS transistor as claimed in claim 7 is characterized in that, described MOS transistor is NMOS, and isolation well is the P trap, and reversed phase ion injects Doping Phosphorus ion or arsenic ion.
9. as the formation method of claim 6 or 7 described a kind of MOS transistor, it is characterized in that the Cmax degree of depth that described reversed phase ion injects is arranged at the near interface of source, drain region and isolation well.
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| CN200910045900A CN101789447A (en) | 2009-01-23 | 2009-01-23 | Metal oxide semiconductor (MOS) transistor and formation method thereof |
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| CN200910045900A CN101789447A (en) | 2009-01-23 | 2009-01-23 | Metal oxide semiconductor (MOS) transistor and formation method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479707A (en) * | 2010-11-24 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Transistor and manufacturing method for same |
| CN102487016A (en) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Preparation method of transistor |
| CN106033729A (en) * | 2015-03-11 | 2016-10-19 | 上海凯世通半导体股份有限公司 | Doping method of Fin FET |
-
2009
- 2009-01-23 CN CN200910045900A patent/CN101789447A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479707A (en) * | 2010-11-24 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Transistor and manufacturing method for same |
| CN102479707B (en) * | 2010-11-24 | 2014-01-08 | 中芯国际集成电路制造(北京)有限公司 | Transistor and manufacturing method for same |
| CN102487016A (en) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Preparation method of transistor |
| CN102487016B (en) * | 2010-12-03 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | Preparation method of transistor |
| CN106033729A (en) * | 2015-03-11 | 2016-10-19 | 上海凯世通半导体股份有限公司 | Doping method of Fin FET |
| CN106033729B (en) * | 2015-03-11 | 2019-04-02 | 上海凯世通半导体股份有限公司 | The doping method of FinFET |
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Open date: 20100728 |