CN102479707B - Transistor and manufacturing method for same - Google Patents
Transistor and manufacturing method for same Download PDFInfo
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- CN102479707B CN102479707B CN201010559189.XA CN201010559189A CN102479707B CN 102479707 B CN102479707 B CN 102479707B CN 201010559189 A CN201010559189 A CN 201010559189A CN 102479707 B CN102479707 B CN 102479707B
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Abstract
The invention provides a transistor and a manufacturing method for the same. The method includes the steps: providing a semiconductor substrate with a formed active layer; forming buried layers spaced from the active layer on the surface of the semiconductor substrate on two sides of the active layer; forming first epitaxial layers flush with the active layer on the surfaces of the buried layers and in the space between each buried layer and the active layer; forming grooves exposed out of the semiconductor substrate in the first epitaxial layers, wherein the grooves are positioned among the buried layers and the active layer; forming buried side walls in the grooves, wherein the thickness of each buried side wall is smaller than the depth of each groove; forming second epitaxial layers on the surfaces of the buried side walls, the active layer and the first epitaxial layers; forming gate structures on the surfaces of the second epitaxial layers above the active layer; and forming a source region and a drain region in the second epitaxial layer and the first epitaxial layer on two sides of each gate structure, wherein the source region and the drain region are positioned on two sides of an isolating side wall. By the aid of the method, the short-channel effect and the performance of the transistor are improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly transistor and preparation method thereof.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device during semiconductor is manufactured, and it is widely used in various integrated circuits, and the doping type difference during according to main charge carrier and manufacture, be divided into NMOS and PMOS transistor.
Prior art provides a kind of transistorized manufacture method.Please refer to Fig. 1 to Fig. 3, is the transistorized manufacture method cross-sectional view of prior art.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, form gate dielectric layer 101 and grid 102 on described Semiconductor substrate 100, described gate dielectric layer 101 and grid 102 form grid structure.
Continuation, with reference to figure 1, is carried out oxidation technology, forms the oxide layer 103 that covers described grid structure.
Then, please refer to Fig. 2, form light doping section 104 in the Semiconductor substrate of grid structure both sides, described light doping section 104 forms by Implantation.
Then, please refer to Fig. 3, form the side wall 105 of grid structure on the Semiconductor substrate of grid structure both sides.Carry out source/drain region heavy doping and inject (S/D), the 106He drain region, the interior formation of Semiconductor substrate 100 source region 107 in the grid structure both sides.
Can find more information about prior art in the Chinese patent application that is CN101789447A at publication number.
Find in practice, the transistor short-channel effect that existing method is made is obvious, and the performance of device is undesirable.
Summary of the invention
The problem that the present invention solves has been to provide a kind of transistor and preparation method thereof, and described method has been improved transistorized short-channel effect, has improved the performance of device.
For addressing the above problem, the invention provides a kind of transistorized manufacture method, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface is formed with active layer, and the material of described active layer is identical with the material of described Semiconductor substrate;
Semiconductor substrate surface in described active layer both sides forms buried layer, between described buried layer and described active layer, has gap;
Form the first epitaxial loayer in described buried layer surface and gap, described the first epitaxial loayer flushes with described active layer;
Form the groove that exposes described Semiconductor substrate in described the first epitaxial loayer, described groove is between described buried layer and described active layer;
Form and bury side wall in described groove, described thickness of burying side wall is less than the degree of depth of described groove;
Form the second epitaxial loayer on described surface of burying side wall, active layer and the first epitaxial loayer;
The second epi-layer surface above described active layer forms grid structure;
Form source region and drain region in the second epitaxial loayer of described grid structure both sides and in the first epitaxial loayer, described source region and drain region are positioned at described isolation side walls both sides.
Alternatively, being positioned at described thickness range of burying the second epitaxial loayer of side wall top is 10～300 nanometers.
Alternatively, the material of described buried layer is the insulation material.
Alternatively, the thickness range of described buried layer is 5～100 dusts.
Alternatively, described material of burying side wall is the insulation material.
Alternatively, described thickness range of burying side wall is 3～30 nanometers.
Alternatively, the width range of described groove is 3～30 nanometers.
Alternatively, described insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
Alternatively, the thickness range that is positioned at second epitaxial loayer on described active layer surface is 20～100 nanometers.
Alternatively, the thickness range of described active layer is 0.05～0.2 micron.
Correspondingly, the present invention also provides a kind of transistor, comprising:
Semiconductor substrate, described semiconductor substrate surface is formed with active layer, and the material of described active layer is identical with the material of described Semiconductor substrate;
Buried layer, be positioned at the semiconductor substrate surface of described active layer both sides, between described buried layer and described active layer, has gap;
The first epitaxial loayer, be positioned at described buried layer surface and gap, and described the first epitaxial loayer flushes with described active layer;
Groove, be positioned at described the first epitaxial loayer, and described groove, between described buried layer and described active layer, and exposes described Semiconductor substrate;
Bury side wall, be positioned at described groove, described thickness of burying side wall is less than the degree of depth of described groove;
The second epitaxial loayer, be positioned at described surface of burying side wall, active layer and the first epitaxial loayer;
Grid structure, be positioned at the second epi-layer surface of described active layer top;
Source region, be positioned at described the second epitaxial loayer and the first epitaxial loayer of burying side wall one side.
Drain region, be positioned at described the second epitaxial loayer and the first epitaxial loayer of burying the side wall opposite side.
Alternatively, being positioned at described thickness range of burying the second epitaxial loayer of side wall top is 10～300 nanometers.
Alternatively, the material of described buried layer is the insulation material.
Alternatively, the thickness range of described buried layer is 5～100 dusts.
Alternatively, described material of burying side wall is the insulation material.
Alternatively, described thickness range of burying side wall is 3～30 nanometers.
Alternatively, the width range of described groove is 3～30 nanometers.
Alternatively, described insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
Alternatively, the thickness range that is positioned at second epitaxial loayer on described active layer surface is 20～100 nanometers.
Alternatively, the thickness range of described active layer is 0.05～0.2 micron.
Compared with prior art, the present invention has the following advantages:
At first the Semiconductor substrate that is formed with active layer is provided, the semiconductor substrate surface of described active layer both sides form with described active layer between the gapped buried layer of tool, the first epitaxial loayer that then formation flushes with described active layer in described buried layer surface and gap, then in described the first epitaxial loayer, form the groove that exposes described Semiconductor substrate, described groove is between described buried layer and described active layer, then in described groove, form thickness be less than described groove the degree of depth bury side wall, at the described side wall of burying, the surface of active layer and the first epitaxial loayer forms the second epitaxial loayer, the described side wall of burying is by the follow-up source region formed in the second epitaxial loayer of grid structure both sides and in the first epitaxial loayer and drain region isolation, thereby describedly bury the doping ion horizontal proliferation that side wall can prevent source region and drain region, thereby improve transistorized short-channel effect, and because described source region and drain region are positioned at the first epitaxial loayer and second epitaxial loayer of buried layer top, thereby reduced the junction capacitance between described source region and drain region and Semiconductor substrate, reduced junction leakage, improved the performance of device.
The accompanying drawing explanation
Fig. 1～Fig. 3 is the preparation method of transistor cross-sectional view of prior art;
Fig. 4 is preparation method of transistor schematic flow sheet of the present invention;
Fig. 5～Figure 15 is the preparation method of transistor cross-sectional view of one embodiment of the invention.
Embodiment
The transistorized short-channel effect that existing method is made is obvious, and the performance of device is undesirable.Development along with semiconductor technology, super shallow junction technology is applied to make source region and drain region, ion horizontal proliferation between source region and drain region is more serious, thereby make described short-channel effect more obvious, and source region and drain region and Semiconductor substrate exist larger junction capacitance and junction leakage, thereby reduced the response speed of device, affected the performance of device.
In order to address the above problem, the inventor proposes a kind of transistorized manufacture method, please refer to the preparation method of transistor schematic flow sheet of the present invention shown in Fig. 4, and described method comprises:
Step S1, provide Semiconductor substrate, and described semiconductor substrate surface is formed with active layer, and the material of described active layer is identical with the material of described Semiconductor substrate;
Step S2, the semiconductor substrate surface in described active layer both sides forms buried layer, between described buried layer and described active layer, has gap;
Step S3 forms the first epitaxial loayer in described buried layer surface and gap, and described the first epitaxial loayer flushes with described active layer;
Step S4 forms the groove that exposes described Semiconductor substrate in described the first epitaxial loayer, and described groove is between described buried layer and described active layer;
Step S5 forms and buries side wall in described groove, and described thickness of burying side wall is less than the degree of depth of described groove;
Step S6, form the second epitaxial loayer on described surface of burying side wall, active layer and the first epitaxial loayer;
Step S7, the second epi-layer surface above described active layer forms grid structure;
Step S8, form source region and drain region in the second epitaxial loayer of described grid structure both sides and in the first epitaxial loayer, and described source region and drain region are positioned at described isolation side walls both sides.
Below in conjunction with specific embodiments technical scheme of the present invention is described in detail.
For explanation better, technical scheme of the present invention, please refer to the preparation method of transistor cross-sectional view of the one embodiment of the invention shown in Fig. 5～Figure 15.
At first, please refer to Fig. 5, Semiconductor substrate 200 is provided, described semiconductor substrate surface 200 is formed with active layer 201, and the material of described active layer 201 is identical with the material of described Semiconductor substrate 200.
As an embodiment, the material of described Semiconductor substrate 200 is silicon.In other embodiment, the material of described Semiconductor substrate 200 can also be other semiconductor material such as germanium, germanium silicon.
In the present embodiment, the thickness range of described active layer 201 is 0.05～0.2 micron.As an embodiment, described active layer 201 forms by the etching semiconductor substrate.Particularly, the described manufacture method that includes described active layer 201 comprises:
The described Semiconductor substrate 200 of partial etching, form active layer 201 on remaining Semiconductor substrate 200 surfaces.
As other embodiment, the manufacture method of described active layer 201 can also be:
Surface deposition epitaxial loayer in described Semiconductor substrate 200;
The described epitaxial loayer of partial etching, form described active layer 201.
Then, please refer to Fig. 6, on the surface of the Semiconductor substrate 200 of described active layer 201 both sides, form buried layer 202.The material of described buried layer 202 is the insulation material, and described insulation material is silica, silicon nitride, carborundum or silicon oxynitride.As preferred embodiment, described insulation material is silica, and it can utilize oxidation technology or chemical vapor deposition method to make.
Described buried layer 202 is for the source region by follow-up formation and drain region and 200 isolation of described Semiconductor substrate, thereby reduces the junction capacitance between described source region and drain region and described Semiconductor substrate 200.
As preferred embodiment, the thickness range of described buried layer 202 is 5～100 dusts.
Then, please refer to Fig. 7, along the thickness direction of described active layer 201, the described buried layer 202 of etching forms gap between described active layer 201 and buried layer 202.
Described etching technics can be dry etch process or wet-etching technology, and described etching technics is same as the prior art, and the known technology as those skilled in the art, do not elaborate at this.
Described gap is used for exposing the Semiconductor substrate 200 of below, thereby can in follow-up processing step, can carry out epitaxial deposition process.
As an embodiment, the width range in described gap is 10 nanometers～1 micron.
Then, please refer to Fig. 8, form the first epitaxial loayer 203 in the surface of described buried layer 202 and gap, described the first epitaxial loayer 203 flushes with described active layer 201.The material of described the first epitaxial loayer 203, crystal orientation and resistivity and described Semiconductor substrate 200 are basic identical.As an embodiment, described the first epitaxial loayer 203 utilizes epitaxial deposition process to make.Described epitaxial deposition process is identical with existing epitaxial deposition process, as those skilled in the art's known technology, at this, does not do and explains.
Then, please refer to Fig. 9, at described the first epitaxial loayer 203, form the groove that exposes described Semiconductor substrate 200, described groove is between described buried layer 202 and described active layer 202.
The width range of described groove is 3～30 nanometers.
As an embodiment, the manufacture method of described groove is:
Carry out etching technics along described active layer 201 thickness directions, described the first epitaxial loayer 203 of etching, until expose the Semiconductor substrate 200 of below, described etching technics is wet-etching technology or dry etch process, the parameter of described wet-etching technology or dry etch process arranges same as the prior art, at this, does not do and repeats.
Then, please refer to Figure 10, in described the first epitaxial loayer 203 surfaces and groove, form insulating barrier, the material of described insulating barrier can be for silica, carborundum, carborundum or silicon oxynitride in interior insulation material.As an embodiment, the material of described insulating barrier is silica, and it can utilize oxidation technology or chemical vapor deposition method to make.
Then, please refer to Figure 11, remove the insulating barrier that is positioned at described the first epitaxial loayer 203 surfaces, the insulating barrier that is positioned at described groove forms buries side wall 204.The described side wall 204 of burying is for the source region that prevents follow-up formation and the diffusion of the doping ion between drain region, thereby improves transistorized short-channel effect.
As an embodiment, the method that the method for removing the insulating barrier that is positioned at described epitaxial loayer 203 surfaces is existing cmp, the method for described cmp, as those skilled in the art's known technology, is not done and is explained at this.
Then, please refer to Figure 12, carry out etching technics, remove part and bury side wall 204, make the described degree of depth of burying side wall 204 be less than the degree of depth of described groove, thereby be conducive to the carrying out of follow-up epitaxial deposition technique.
Then, please refer to Figure 13, carry out epitaxial deposition process, on described surface of burying side wall 204, active layer 201 and the first epitaxial loayer 203, form the second epitaxial loayer 205.Wherein, the thickness range that is positioned at second epitaxial loayer 205 on described active layer 201 surfaces is 20～100 nanometers.
Because the described degree of depth of burying side wall 204 is less than the degree of depth of described groove, when carrying out epitaxial deposition process, described top of burying side wall 204 is exposed out, and the both sides at described top have described the first epitaxial loayer 203, thereby described top can form the second epitaxial loayer 205 above burying side wall 204 described epitaxial deposition technique is described from described two side direction of burying side wall 204, and described the second epitaxial loayer 205 covers the described surfaces of burying side wall 204 and covering described the first epitaxial loayer 203.
Described the second epitaxial loayer 205 is made source region and drain region with described the first epitaxial loayer 203 for the processing step follow-up.Being positioned at described thickness range of burying the second epitaxial loayer 205 of side wall 204 tops is 10～300 nanometers, and described the second epitaxial loayer 205 is as transistorized channel region, as the source region of follow-up formation and the conducting channel between drain region.
Owing to utilizing epitaxial deposition process to make, therefore material, crystal orientation and the resistivity of material, crystal orientation and the resistivity of described the second epitaxial loayer 205 and described the first epitaxial loayer 203 are basic identical.
Then, please refer to Figure 14, the second epitaxial loayer 205 surfaces above described active layer 201 form gate dielectric layer 206 and grid 207 successively.
The material of described gate dielectric layer 206 is silica, and it can utilize oxidation technology to make.The thickness range of described gate dielectric layer 206 is 10～100 dusts.
The material of described grid 207 is polysilicon, and it can utilize chemical vapor deposition method to make.
Then, please continue to refer to Figure 14, in the both sides of described gate dielectric layer 206, both sides and formation gap, the top oxide layer 208 of grid 207, described gap oxide layer 208 is for the protection of described gate dielectric layer 206 and grid 207.Described gap oxide layer 208 can utilize oxidation technology or depositing operation to make.The thickness range of described gap oxide layer 208 is 10～50 dusts.
Then, please continue to refer to Figure 14, take described grid 207 and gap oxide layer 208 is mask, carry out Implantation, the interior formation light doping section 209 of the second epitaxial loayer 205 in described grid 207 both sides, the parameter of Implantation that forms described light doping section 209 is identical with the parameter of the Implantation of existing formation light doping section, as those skilled in the art's known technology, at this, does not do and explains.
Then, please refer to Figure 15, on the surface of the second epitaxial loayer 205 of described grid 207 and gap oxide layer 208 both sides, form side wall 208, described side wall 208 forms grid structures with described gate dielectric layer 206, grid 207, gap oxide layer 208.
The material of described side wall 208 is the insulation material, and the manufacture method of described side wall 208 is same as the prior art, as those skilled in the art's known technology, at this, does not do and explains.
Then, please continue to refer to Figure 15, in the second epitaxial loayer 205 of described grid structure both sides, with 210He drain region, the interior formation of the first epitaxial loayer 203 source region 211,210He drain region, described source region 211 is positioned at the both sides of described isolation side walls 204.The manufacture method in 210He drain region, described source region 211 utilizes existing source/leakage Implantation to form (SD implant).Owing to being positioned at described thickness range of burying the second epitaxial loayer 205 of side wall 204 tops, be 10～300 nanometers, described the second epitaxial loayer 205 is as transistorized channel region, as the source region of follow-up formation and the conducting channel between drain region.Being positioned at described thickness of burying the second epitaxial loayer 205 above side wall 204, it is above-mentioned number range, can guarantee transistorized normal operation, and described isolation side walls 204 can effectively stop the doping ion between 210He drain region, source region 211 to spread by described isolation side walls 204 positions, is conducive to improve short-channel effect.Because described the first epitaxial loayer 203 belows are formed with buried layer 202, described buried layer 202 can be isolated 210He drain region, source region 211 and the Semiconductor substrate 200 of below, reduces to form junction capacitance between 210Huo drain region 211, described source region and described Semiconductor substrate 200.
Through above-mentioned steps, the transistor of formation please refer to Figure 15, and described transistor comprises:
The first epitaxial loayer 203, be positioned at surface and the described gap of described buried layer 202, and described the first epitaxial loayer 203 flushes with described active layer 201;
Groove, be positioned at described the first epitaxial loayer 203, and described groove is between described buried layer 202 and described active layer 201;
The second epitaxial loayer 205, be positioned at described surface of burying side wall 204, active layer 201 and the first epitaxial loayer 203;
Grid structure, be positioned at the second epitaxial loayer 205 surfaces of described active layer 201 tops, described grid structure comprise the gate dielectric layer 206 that is positioned at described the second epitaxial loayer 205 surfaces, the grid 207 that is positioned at described gate dielectric layer 206 surfaces, the both sides that are positioned at described gate dielectric layer 206 both sides and grid 207 and top gap oxide layer 208, be positioned at the side wall 208 of described grid 207 and gap oxide layer 208 both sides;
As an embodiment, the material of described buried layer 202 is the insulation material, and its thickness range is 5～100 dusts.The material of described buried layer 202 can, for silica, silicon nitride, carborundum or silicon oxynitride, be preferably silica.
Described material of burying side wall 204 is the insulation material, and its thickness range is 3～30 nanometers, and described material of burying side wall 204 can be silica, silicon nitride, carborundum or silicon oxynitride.The width range of described groove is 3～30 nanometers.
Please refer to Figure 15, as an embodiment, the thickness range of described active layer 201 is 0.05～0.2 micron, and the thickness range that is positioned at second epitaxial loayer 205 on described active layer 201 surfaces is 20～100 nanometers.Material, crystal orientation and the resistivity of described the first epitaxial loayer 203 and the second epitaxial loayer 205 and material, crystal orientation and the resistivity of described Semiconductor substrate 200 are basic identical.In order to guarantee that transistor can work, described thickness of burying the second epitaxial loayer 205 of side wall 204 tops should be 10～300 nanometers, in above-mentioned thickness range, describedly bury the diffusion that side wall 204 can effectively prevent the doping ion in adjacent 210He drain region, source region 211, thereby can improve transistorized short-channel effect.Because described the first epitaxial loayer 203 belows are formed with buried layer 202, described buried layer 202 can be isolated 210He drain region, source region 211 and the Semiconductor substrate 200 of below, reduces to form junction capacitance between 210Huo drain region 211, described source region and described Semiconductor substrate 200.
To sum up, transistor provided by the invention and preparation method thereof, form isolation side walls between source region and drain region, described isolation side walls can prevent the doping ion diffusion between source region and drain region, improved transistorized short-channel effect, because described source region and drain region are positioned at the buried layer top, therefore described buried layer prevents from forming junction capacitance between source region and drain region and Semiconductor substrate, reduce junction leakage, improved transistorized performance.
Although the present invention discloses as above with preferred embodiment, the present invention not is defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (20)
1. a transistorized manufacture method, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface is formed with active layer, and the material of described active layer is identical with the material of described Semiconductor substrate;
Semiconductor substrate surface in described active layer both sides forms buried layer, between described buried layer and described active layer, has gap;
Form the first epitaxial loayer in described buried layer surface and gap, described the first epitaxial loayer flushes with described active layer;
Form the groove that exposes described Semiconductor substrate in described the first epitaxial loayer, described groove is between described buried layer and described active layer;
Form and bury side wall in described groove, described thickness of burying side wall is less than the degree of depth of described groove;
Form the second epitaxial loayer on described surface of burying side wall, active layer and the first epitaxial loayer;
The second epi-layer surface above described active layer forms grid structure;
Form source region and drain region in the second epitaxial loayer of described grid structure both sides and in the first epitaxial loayer, described source region and drain region are positioned at the described side wall both sides of burying.
2. transistorized manufacture method as claimed in claim 1, is characterized in that, being positioned at described thickness range of burying the second epitaxial loayer of side wall top is 10～300 nanometers.
3. transistorized manufacture method as claimed in claim 1, is characterized in that, the material of described buried layer is the insulation material.
4. transistorized manufacture method as claimed in claim 3, is characterized in that, the thickness range of described buried layer is 5～100 dusts.
5. transistorized manufacture method as claimed in claim 1, is characterized in that, described material of burying side wall is the insulation material.
6. transistorized manufacture method as claimed in claim 5, is characterized in that, described thickness range of burying side wall is 3～30 nanometers.
7. transistorized manufacture method as claimed in claim 1, is characterized in that, the width range of described groove is 3～30 nanometers.
8. transistorized manufacture method as described as claim 3 or 5, is characterized in that, described insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
9. transistorized manufacture method as claimed in claim 1, is characterized in that, the thickness range that is positioned at second epitaxial loayer on described active layer surface is 20～100 nanometers.
10. transistorized manufacture method as claimed in claim 1, is characterized in that, the thickness range of described active layer is 0.05～0.2 micron.
11. a transistor, is characterized in that, comprising:
Semiconductor substrate, described semiconductor substrate surface is formed with active layer, and the material of described active layer is identical with the material of described Semiconductor substrate;
Buried layer, be positioned at the semiconductor substrate surface of described active layer both sides, between described buried layer and described active layer, has gap;
The first epitaxial loayer, be positioned at described buried layer surface and gap, and described the first epitaxial loayer flushes with described active layer;
Groove, be positioned at described the first epitaxial loayer, and described groove, between described buried layer and described active layer, and exposes described Semiconductor substrate;
Bury side wall, be positioned at described groove, described thickness of burying side wall is less than the degree of depth of described groove;
The second epitaxial loayer, be positioned at described surface of burying side wall, active layer and the first epitaxial loayer;
Grid structure, be positioned at the second epi-layer surface of described active layer top;
Source region, be positioned at described the second epitaxial loayer and the first epitaxial loayer of burying side wall one side;
Drain region, be positioned at described the second epitaxial loayer and the first epitaxial loayer of burying the side wall opposite side.
12. transistor as claimed in claim 11, is characterized in that, being positioned at described thickness range of burying the second epitaxial loayer of side wall top is 10～300 nanometers.
13. transistor as claimed in claim 11, is characterized in that, the material of described buried layer is the insulation material.
14. transistor as claimed in claim 12, is characterized in that, the thickness range of described buried layer is 5～100 dusts.
15. transistor as claimed in claim 11, is characterized in that, described material of burying side wall is the insulation material.
16. transistor as claimed in claim 15, is characterized in that, described thickness range of burying side wall is 3～30 nanometers.
17. transistor as claimed in claim 11, is characterized in that, the width range of described groove is 3～30 nanometers.
18. the transistor as claim 13 or 15, is characterized in that, described insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
19. the transistor as claim 11 is stated, is characterized in that, the thickness range that is positioned at second epitaxial loayer on described active layer surface is 20～100 nanometers.
20. the transistor as claim 11 is stated, is characterized in that, the thickness range of described active layer is 0.05～0.2 micron.
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| CN201010559189.XA CN102479707B (en) | 2010-11-24 | 2010-11-24 | Transistor and manufacturing method for same |
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| CN201010559189.XA CN102479707B (en) | 2010-11-24 | 2010-11-24 | Transistor and manufacturing method for same |
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| CN102479707B true CN102479707B (en) | 2014-01-08 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4523213A (en) * | 1979-05-08 | 1985-06-11 | Vlsi Technology Research Association | MOS Semiconductor device and method of manufacturing the same |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN101789447A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor (MOS) transistor and formation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4523213A (en) * | 1979-05-08 | 1985-06-11 | Vlsi Technology Research Association | MOS Semiconductor device and method of manufacturing the same |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN101789447A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor (MOS) transistor and formation method thereof |
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