CN111092120B - Manufacturing method of field effect transistor device - Google Patents
Manufacturing method of field effect transistor device Download PDFInfo
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- CN111092120B CN111092120B CN201811242745.3A CN201811242745A CN111092120B CN 111092120 B CN111092120 B CN 111092120B CN 201811242745 A CN201811242745 A CN 201811242745A CN 111092120 B CN111092120 B CN 111092120B
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- 230000005669 field effect Effects 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000002347 injection Methods 0.000 claims abstract description 13
- 239000007924 injection Substances 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims description 30
- -1 arsenic ions Chemical class 0.000 claims description 27
- 229910052796 boron Inorganic materials 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 14
- 229910052785 arsenic Inorganic materials 0.000 claims description 13
- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
- 239000011574 phosphorus Substances 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 12
- 239000000969 carrier Substances 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000002513 implantation Methods 0.000 description 29
- 229910052751 metal Inorganic materials 0.000 description 19
- 239000002184 metal Substances 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 230000008569 process Effects 0.000 description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 239000007943 implant Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention provides a field effect transistor device and a manufacturing method thereof, and relates to the technical field of semiconductor production. The field effect transistor device includes: a substrate; the well region is positioned in the substrate and is implanted with ions of a first type, and the well region comprises a channel region, a lightly doped region, a source region and a drain region; a gate structure on the substrate, the gate structure being located directly above the channel region; the channel region comprises a counter-state doped region, and counter-state ions of a type opposite to the first type are implanted into the counter-state doped region and are symmetrically distributed relative to the central axis of the channel region. The channel region of the field effect transistor device provided by the invention comprises the anti-state doped region injected with the anti-state ions, and the anti-state doped region is symmetrically distributed relative to the central axis of the channel region, so that the conducting channel of the device is widened, the probability of forming hot carriers by electrons is reduced, the hot carrier injection effect of the device is reduced, the saturation current of the device is increased, the threshold voltage is reduced, and the device performance is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor production, in particular to a field effect transistor device and a manufacturing method thereof.
Background
After a period of operation of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device in an integrated circuit, the electrical properties of the device change gradually, for example: the threshold voltage (Vt) shifts, the transconductance (Gm) decreases, the saturation current (Idsat) decreases, and these transitions eventually lead to device failure. Studies have shown that this phenomenon is due to the hot carrier injection effect (Hot Carrier Injection, HCI).
In the fabrication of Dynamic Random Access Memory (DRAM), the hot carrier injection effect of NMOSFET devices in the memory peripheral circuits is improved, and the reliability of the memory devices can be improved.
Thus, in the memory field, there is a need for a simple and effective solution to the problem of device performance drift due to HCI.
It should be noted that the information of the present invention in the above background section is only for enhancing the understanding of the background of the present invention and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a field effect transistor device and a manufacturing method thereof, which at least overcome the problem of device performance drift caused by hot carrier injection effect to a certain extent.
Other features and advantages of the invention will be apparent from the following detailed description, or may be learned by the practice of the invention.
According to a first aspect of the present invention there is provided a field effect transistor device, the device comprising: a substrate; the well region is positioned in the substrate and is filled with ions of a first type, the well region comprises a channel region, a lightly doped region, a source region and a drain region, the source region and the drain region are respectively positioned at two sides of the channel region, and the lightly doped region is also positioned at two sides of the channel region; a gate structure on the substrate, the gate structure comprising a gate oxide layer and an electrode material layer on the gate oxide layer, the gate structure being located directly above the channel region; the channel region comprises an anti-state doped region, and the anti-state doped region is implanted with anti-state ions of a type opposite to the first type and is symmetrically distributed relative to the central axis of the channel region.
In the above scheme, the device is an N-type metal oxide field effect transistor device, and the counter ion includes arsenic ion.
In the scheme, the implantation dosage of the counter-state ions is 1.5E12-1.9E12 per cubic centimeter, and the implantation energy of the counter-state ions is 30-35 KeV.
In the above scheme, the ions of the first type are boron ions, the implantation dosage of the boron ions is 1.5E13 per cubic centimeter-3E 13 per cubic centimeter, and the implantation energy of the boron ions is 130 KeV-160 KeV.
In the above scheme, the lightly doped region is not connected with the counter doped region, and the ions implanted into the lightly doped region include phosphorus ions or arsenic ions.
According to a second aspect of the present invention, there is provided a method of manufacturing a field effect transistor device, comprising: providing a substrate; defining a first position of a channel region in the substrate, and performing second type ion implantation on the substrate part at the first position to form a counter-state doped region, wherein the counter-state doped region is symmetrically distributed relative to a central axis of the channel region; defining a second position of a well region in the substrate, and carrying out first type ion implantation on a substrate part of the second position, wherein the first type ion and the second type ion are opposite; forming a gate structure over the channel region; performing lightly doped ion implantation on the substrate part at the second position by taking the gate structure as a mask to form a lightly doped region, wherein the lightly doped region is positioned at two sides of the channel region; and carrying out source-drain injection on the substrate part with the second position of the lightly doped region to form a source region and a drain region, wherein the source region and the drain region are respectively positioned at two sides of the channel region.
In the above scheme, the device is an N-type metal oxide field effect transistor device, and the second type ion is arsenic ion.
In the above scheme, the implantation dose of the second type ion is 1.5E12-1.9E12 per cubic centimeter, and the implantation energy of the second type ion is 30-35 KeV.
In the above scheme, the first type ion is boron ion, the implantation dosage of the boron ion is 1.5E13 per cubic centimeter to 3E13 per cubic centimeter, and the implantation energy of the boron ion is 130KeV to 160KeV.
In the above scheme, the lightly doped region is not connected with the counter doped region, and the lightly doped ions include phosphorus ions or arsenic ions.
The technical scheme provided by the embodiment of the invention can have the following beneficial effects:
In the technical scheme provided by the exemplary embodiment of the invention, the channel region of the field effect transistor device comprises the anti-state doped region injected with the anti-state ions, and the anti-state doped region is symmetrically distributed relative to the central axis of the channel region, so that the conducting channel of the device is widened, the probability of forming hot carriers by electrons is reduced, the hot carrier injection effect of the device is reduced, the saturation current of the device is increased, the threshold voltage is reduced, and the device performance is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 schematically illustrates a block diagram of a field effect transistor device according to an embodiment of the present invention;
Fig. 2 schematically illustrates a flow chart of a method of manufacturing a field effect transistor device according to an embodiment of the invention;
FIG. 3 is a diagram illustrating performing step S304 of a second type ion implantation;
FIG. 4 is a schematic illustration of performing a first type of ion implantation;
FIG. 5 is a schematic cross-sectional view after completion of step S306;
Fig. 6 is a schematic cross-sectional view after completion of step S307;
Fig. 7 is a schematic cross-sectional view after step S308 is completed.
Detailed Description
Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the modules of the figures are flipped upside down, the components recited as "up" will become "down". Other relative terms such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.
In an NMOSFET in the related art, a symmetric structure is used as a conductive channel, the semiconductor device includes a substrate, a P-type well region, two N-type regions formed by N-type ion doping, namely a source region and a drain region, a conductive channel is formed between the two N-type regions, a gate oxide layer, a polysilicon gate layer and gate metal are generally covered on the conductive channel, source metal is formed corresponding to the source region, and drain metal is formed corresponding to the drain region. The substrate is a silicon substrate, the P-type well region is a well region with lower dosage of P-type ions (III-group element ions such As boron B or gallium Ga) and the source region and the drain region are two N+ regions with higher dosage of N-type ions (V-group element ions such As phosphorus P or arsenic As).
In addition, the conductive channel comprises a P-type doped region, wherein boron B ions are doped (the implantation energy is 10 KeV-15 KeV, and the implantation dosage is 2E12 per cubic centimeter-5.5E12 per cubic centimeter). There is also a lightly doped region in the portion of the conductive channel near the two high implant dose N + regions, respectively, into which phosphorus P or arsenic As plasma is doped. The polysilicon gate layer is polysilicon formed by N-type ion doping, and the gate metal is connected with the gate control line so as to input a gate voltage Vg to the gate of the MOSFET. The drain metal is connected to the data line to input the data voltage Vd to the drain of the MOSFET.
Here, the generation of the hot carrier effect is mainly affected by the electric field strength in the horizontal direction, where the electric field strength is greatest, that is, where the conductive channel is located near the drain, that is, where the strong electric field region is formed in the drain-gate region. The generation of hot carrier effects is mainly affected by the electric field strength in the horizontal direction, where the electric field strength is greatest, i.e., where the conductive channel is near the drain, and thus HCI usually occurs on the drain side.
Conventional approaches to addressing HCI may be to add a gate oxide or use a lightly doped (Light Doped Drain, simply lightly doped) technique. The gate oxide layer is added to improve the quality of gate oxide, for example, the H and H 2 O of Si-SiO 2 interface can be reduced, the plasma damage to the oxide layer in the reactive ion etching (Reactive Ion Etching, RIE for short) process of metal corrosion and the like can be reduced, or the silicon oxynitride is adopted to replace the original SiO 2 to make the gate oxide. The lightly doped drain region is arranged near the drain electrode in the channel, so that the lightly doped drain region is also subjected to partial voltage, and the structure can prevent the thermal electron degradation effect.
The embodiment of the disclosure provides a field effect transistor device, wherein P-type ions in a P-type doped region in a conductive channel in the related technology are changed into reverse N-type ions. The following describes example embodiments of the present disclosure in detail with reference to the accompanying drawings.
Fig. 1 schematically illustrates a structural diagram of a field effect transistor device of an exemplary embodiment of the present disclosure.
Referring to fig. 1, a field effect transistor device 200 according to an embodiment of the present invention includes: the substrate 201 and the well region 202 are positioned in the substrate 201, ions of a first type are implanted into the well region 202, the well region 202 comprises a channel region 205, a lightly doped region, a source region 203 and a drain region 204, and the source region 203 and the drain region 204 are respectively positioned at two sides of the channel region; a gate structure is located on the substrate 201, the gate structure including a gate oxide layer 206 and an electrode material layer located on the gate oxide layer, the gate structure being located directly above the channel region; the channel region 205 includes an anti-doped region, which is implanted with anti-ions of an opposite type to the first type and is symmetrically distributed with respect to a central axis of the channel region.
In the above scheme, the channel region of the field effect transistor device is provided with the counter-state doped region 2051 formed by injecting counter-state ions, so that the conducting channel of the device can be widened, the probability of forming hot carriers by electrons is reduced, the hot carrier injection effect of the device is reduced, the saturation current of the device is increased, the threshold voltage is reduced, and the device performance is improved.
In an exemplary embodiment of the present disclosure, the implantation dose of the counter ion is 1.5E12 per cubic centimeter to 1.9E12 per cubic centimeter, and the implantation energy of the counter ion is 30KeV to 35KeV.
In the technical scheme of the embodiment of the disclosure, the field effect transistor is an N-type MOSFET, which is called NMOS for short.
Specific structures of exemplary embodiments of the present disclosure are described below using NMOS employing an N-type substrate as an example.
As shown in fig. 1, the field effect transistor 200 is an NMOS device, and the substrate 201 is an N-type substrate. The well region 202 is formed by doping the substrate 201 with ions of the first type, i.e., P-type ions. Here, the P-type ion includes a +3 valent ion such as boron B. When the boron ion implantation is carried out, the implantation dosage of the boron ion is 1.5E13 per cubic centimeter to 3E13 per cubic centimeter, and the implantation energy of the boron ion is 130KeV to 160KeV.
The source region 203 and the drain region 204 are doped regions, and the ion states of the doping regions are N-type ions. Here, the N-type ion includes +5 valent ions such As phosphorus P, arsenic As, and the like.
As shown in fig. 1, the lightly doped regions include a first lightly doped region 2052 and a second lightly doped region 2053. The first lightly doped region 2052 is located adjacent to the source region 203; the second lightly doped region 2053 is located adjacent to the side of drain region 204. The first lightly doped region 2052 and the second lightly doped region 2053 are the same As lightly doped regions (such As lightly doped drain regions Lightly Doped Drain, LDD for short) of conventional NMOS transistors, wherein the lightly doped regions are doped with ions of the same type As the source region 203 and the drain region 204, i.e., the ion type doped in the first lightly doped region 307 and the second lightly doped region 308 is also an N-type ion, such As P or As +5 valence ions.
In this embodiment, the doping ions in the counter doping region 2051 are N-type, and the doping ions in the source region 203, the drain region 204, the first lightly doped region 2052 and the second lightly doped region 2053 are also N-type, i.e. the doping ions in the counter doping region 2051 are the same as the doping ions in the source region 203, the drain region 204, the first lightly doped region 2052 and the second lightly doped region 2053, and are only different from the doping ions in the well region 202.
In addition, as shown in fig. 2, neither lightly doped region 2052 nor lightly doped region 2053 is connected to the counter doped region 2051, where the lightly doped region is implanted with ions of phosphorus or arsenic.
As shown in fig. 1, a gate oxide layer 206, a polysilicon gate layer 207, and a gate metal 208 are also disposed over the conductive channel 205, as well as a source metal 209 disposed over the source region 203 and a drain metal 210 disposed over the drain region 204. The polysilicon gate layer 207 is polysilicon formed by N-type ion doping, and the gate metal 308 is connected to a gate control line so as to input a gate voltage Vg to the gate of the MOSFET. The drain metal 210 is connected to the data line to input the data voltage Vd to the drain of the MOSFET.
In summary, the channel region of the field effect transistor device provided by the embodiment of the invention includes the anti-state doped region implanted with the counter-state ions, and the anti-state doped region is symmetrically distributed relative to the central axis of the channel region, so that the conducting channel of the device is widened, the probability of forming hot carriers by electrons is reduced, the hot carrier injection effect of the device is reduced, the saturation current of the device is increased, the threshold voltage is reduced, and the device performance is improved.
Fig. 2 is a flowchart of a method for fabricating a field effect transistor device according to an embodiment of the disclosure, and the following details will take an example of fabricating an NMOS device, as shown in fig. 2, and the method includes the following steps:
step S302, providing a substrate.
Step S304, defining a first position of the channel region in the substrate, and performing second type ion implantation on the substrate portion at the first position to form a counter doped region, wherein the counter doped region is symmetrically distributed relative to a central axis of the channel region.
In step S305, a second position of the well region is defined in the substrate, and a first type ion implantation is performed on a portion of the substrate at the second position, where the first type ion is opposite to the second type ion.
In step S306, a gate structure is formed over the channel region.
In step S307, lightly doped ion implantation is performed on the substrate portion at the second position with the gate structure as a mask, so as to form lightly doped regions, and the lightly doped regions are located at two sides of the channel region.
And step S308, carrying out source-drain injection on the substrate part with the second position of the lightly doped region by taking the gate structure as a mask to form a source region and a drain region, wherein the source region and the drain region are respectively positioned at two sides of the channel region.
When the scheme is adopted to manufacture the device, the conducting channel is widened, and the probability of forming hot carriers by electrons is reduced, so that the hot carrier injection effect of the device is reduced, the saturation current of the device is increased, the threshold voltage is reduced, and the device performance is improved.
In exemplary embodiments of the present disclosure, a P-type substrate may be directly employed, an N-type substrate may be employed, and the conductive channel is located in a P-type well region in the substrate. When the P-type substrate is adopted, the implantation dosage of the P-type ions in the well region is higher than that of the P-type ions in the substrate.
Fig. 3 is a schematic diagram illustrating performing step S304 to perform a first type ion implantation. As shown in fig. 3, arsenic As ion implantation is performed at a specific location (e.g., a specific location defined by a photolithography process) in the N-type substrate 901, to form an anti-state doped region 9051. The ion implantation in this step is counter-doping, i.e. the ion implanted in a specific location in the counter-ion implantation process should be of the N-type ions such As P or As, which are opposite to the ion implanted in the conventional NMOS.
In this embodiment, this step performs ion implantation over the entire length of the conductive channel to form a counter-doped region that is symmetrically distributed about the central axis of the channel region.
In step S304, when the first form ion implantation, that is, the counter ion implantation is performed on the substrate, the implantation dose of the counter ion is 1.5E12 to 1.9E12 per cubic centimeter, and the implantation energy of the counter ion is 30 to 35kev.
For example, in this embodiment, the implantation energy for the reverse ion implantation may be selected to be 32KeV, and the implantation dose of ions may be 1.7E12 per cubic centimeter.
It should be noted that, the ion implantation may cause lattice damage of the crystal, after the ion implantation process, the integrity of the crystal lattice must be recovered by high-temperature annealing, and the high-temperature annealing may cause further diffusion of ions, so that the range of the ion implantation area should be slightly smaller than the range of the desired counter-state doped area, so that the abnormal-state doped area formed after the high-temperature annealing just meets the requirement. As an example, the first ion implantation to form the counter doped region may further include an annealing process, which may be used to repair damage to the substrate and to control diffusion of implanted ions.
In an exemplary embodiment of the present disclosure, in step S305, a first type ion implantation is required to be performed on a second location where a well region defined in a substrate is located, where the first type ion is opposite to the second type ion. Thus, the first type here is P-type ions. As shown in fig. 4, P-type ions are implanted to form P-type well region 902.
In an exemplary embodiment of the present disclosure, the ion type of the ion forming the well region, i.e., the ion implantation of the first type ion, is P-type ion, e.g., a +3 valent ion such as a boron ion. Here, the implantation energy of the boron ions is 130kev to 160kev, and the implantation dose of the boron ions is 1.5e13 per cubic centimeter to 3E13 per cubic centimeter.
For example, in this embodiment, the implantation energy of boron ions may be selected to be 150KeV, and the implantation dose of boron ions may be 2E13 per cubic centimeter.
In step S306, a gate structure is formed on the counter-doped region of the substrate. Specifically, as shown in fig. 5, a gate oxide layer 906 and a polysilicon gate layer 907 are formed over the channel region, i.e., the conductive channel.
Specifically, a gate oxide layer 906 and a polysilicon gate layer 907 are formed over the conductive channel by deposition etching. In this step, polysilicon is formed on the conductive channel, specifically amorphous silicon is formed by PECVD reaction, and then polysilicon is manufactured by excimer laser annealing. Wherein the polysilicon here may be N-doped, i.e. N + Poly.
In step S307, lightly doped ion implantation is performed on both sides of the conductive channel, and as shown in fig. 6, a first lightly doped region 9052 and a second lightly doped region 9053 are formed, respectively.
In step S307, ion implantation is performed on both sides of the conductive channel in addition to the formation of the counter doped region 9051 in the conductive channel to form a first lightly doped region 9052 and a second lightly doped region 9053 on both sides of the channel region, respectively. Wherein the lightly doped region is not connected with the counter doped region, and the lightly doped ions comprise phosphorus ions or arsenic ions.
The implantation energy of the lightly doped ions in the step is 15 KeV-35 KeV, and the implantation dosage of the ions is 5E13 per cubic centimeter-2E 14 per square centimeter. As shown in fig. 6, the ion depth in the counter doped region 9051 is deeper than the ion depths in the first and second lightly doped regions 9052 and 9053.
In step S308, source-drain implantation is performed in the conductive channel near the first lightly doped region 9052 and the second lightly doped region 9053, and a source region and a drain region are formed, respectively, as shown in fig. 7. Here, a gate sidewall 908 is added to two sides of the gate structure, and the component may be silicon nitride.
Specifically, a source doped region, i.e., source region 903, and a drain doped region, i.e., drain region 904, are formed at positions adjacent to the first lightly doped region 9052 and the second lightly doped region 9053, respectively, by an ion implantation process. Wherein the first lightly doped region 9052 is near the side of the source region 903, the second lightly doped region 9053 is near the side of the drain region 904, and the source region and the drain region are respectively located at two sides of the channel region.
In step S308, the ion type implanted in the source drain implantation is also N-type ions such As P or As. When the source region or the drain region is formed, the implantation energy of ions is 15 KeV-25 KeV, and the implantation dosage of the ions is 5E13 per cubic centimeter-5E 15 per square centimeter.
Finally, forming gate metal, source metal and drain metal through a composition process. This step forms a gate metal over polysilicon gate layer 907, a source metal over source doped region 903, and a drain metal over drain doped region 904, ultimately forming a field effect transistor device.
In one exemplary embodiment of the present disclosure, the counter ion implant is of the opposite ion type to the first type ion implant, and the counter ion implant is of the same ion type as the lightly doped ion implant.
In the step of ion implantation, a preset mask is used to perform shielding so as to form a desired structure on the substrate.
Finally, the gate metal is connected to the gate control line to input the gate signal Vg to the gate electrode, and the drain metal is connected to the data line to input the data signal Vd to the drain electrode, as shown in fig. 1.
Based on the manufacturing method, in the manufacturing method of the field effect transistor device provided by the embodiment of the invention, the channel region of the device is injected with the counter-state ions to form the counter-state doped region symmetrically distributed relative to the central axis of the channel region, so that the conducting channel of the device is widened, the probability of forming hot carriers by electrons is reduced, the hot carrier injection effect of the device is reduced, the saturation current of the device is increased, the threshold voltage is reduced, and the device performance is improved.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (5)
1. A method of manufacturing a field effect transistor device, comprising:
providing a substrate;
Defining a first position of a channel region in the substrate, and performing second type ion implantation on the substrate part at the first position to form a counter-state doped region, wherein the counter-state doped region is symmetrically distributed relative to a central axis of the channel region;
defining a second position of a well region in the substrate, and carrying out first type ion implantation on a substrate part of the second position, wherein the first type ion and the second type ion are opposite;
forming a gate structure over the channel region;
performing lightly doped ion implantation on the substrate part at the second position by taking the gate structure as a mask to form a lightly doped region, wherein the lightly doped region is positioned at two sides of the channel region;
And carrying out source-drain injection on the substrate part with the second position of the lightly doped region to form a source region and a drain region, wherein the source region and the drain region are respectively positioned at two sides of the channel region.
2. The method of claim 1, wherein the device is an N-type metal oxide field effect transistor device and the second type of ions are arsenic ions.
3. The method of claim 2, wherein the second type of ions are implanted at a dose of 1.5E12 to 1.9E12 per cubic centimeter and the second type of ions are implanted at an energy of 30 to 35kev.
4. The method of claim 1, wherein the first type of ions are boron ions, the boron ions are implanted at a dose of 1.5e13 per cubic centimeter to 3E13 per cubic centimeter, and the boron ions are implanted at an energy of 130kev to 160kev.
5. The method of claim 1, wherein the lightly doped region is not connected to the counter doped region and the lightly doped ions comprise phosphorus ions or arsenic ions.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5904530A (en) * | 1991-05-15 | 1999-05-18 | Goldstar Electron Co., Ltd. | Method of making LDD structure spaced from channel doped region |
| KR20050071033A (en) * | 2003-12-31 | 2005-07-07 | 동부아남반도체 주식회사 | Semiconductor device and method for manufacturing thereof |
| CN101609841A (en) * | 2008-06-18 | 2009-12-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of metal-oxide semiconductor (MOS) (MOS) transistor arrangement and manufacture method thereof |
| CN103296027A (en) * | 2012-02-28 | 2013-09-11 | 德克萨斯仪器股份有限公司 | Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors |
| CN104658913A (en) * | 2015-02-10 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for NLDMOS |
| US9997628B1 (en) * | 2017-04-13 | 2018-06-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of fabricating thereof |
| CN208835069U (en) * | 2018-10-24 | 2019-05-07 | 长鑫存储技术有限公司 | Field-effect tube device |
-
2018
- 2018-10-24 CN CN201811242745.3A patent/CN111092120B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5904530A (en) * | 1991-05-15 | 1999-05-18 | Goldstar Electron Co., Ltd. | Method of making LDD structure spaced from channel doped region |
| KR20050071033A (en) * | 2003-12-31 | 2005-07-07 | 동부아남반도체 주식회사 | Semiconductor device and method for manufacturing thereof |
| CN101609841A (en) * | 2008-06-18 | 2009-12-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of metal-oxide semiconductor (MOS) (MOS) transistor arrangement and manufacture method thereof |
| CN103296027A (en) * | 2012-02-28 | 2013-09-11 | 德克萨斯仪器股份有限公司 | Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors |
| CN104658913A (en) * | 2015-02-10 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for NLDMOS |
| US9997628B1 (en) * | 2017-04-13 | 2018-06-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of fabricating thereof |
| CN208835069U (en) * | 2018-10-24 | 2019-05-07 | 长鑫存储技术有限公司 | Field-effect tube device |
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