CN111129156A - Manufacturing method of NMOS (N-channel metal oxide semiconductor) device and semiconductor device manufactured by same - Google Patents
Manufacturing method of NMOS (N-channel metal oxide semiconductor) device and semiconductor device manufactured by same Download PDFInfo
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- CN111129156A CN111129156A CN201911373468.4A CN201911373468A CN111129156A CN 111129156 A CN111129156 A CN 111129156A CN 201911373468 A CN201911373468 A CN 201911373468A CN 111129156 A CN111129156 A CN 111129156A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 238000000034 method Methods 0.000 claims abstract description 135
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 63
- 229920005591 polysilicon Polymers 0.000 claims description 47
- 238000005468 ion implantation Methods 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 34
- 238000002955 isolation Methods 0.000 claims description 26
- 229910052732 germanium Inorganic materials 0.000 claims description 20
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 20
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 15
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 17
- 238000002513 implantation Methods 0.000 description 12
- 239000000243 solution Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention relates to a method for manufacturing an NMOS (N-channel metal oxide semiconductor) device and a semiconductor device manufactured by the method, and relates to a manufacturing process of a semiconductor integrated circuit.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit manufacturing process, and more particularly, to a method for manufacturing an NMOS device and a semiconductor device manufactured thereby.
Background
In current integrated circuits, high voltage devices, such as input/output (I/O) devices, are important components. Compared with a low-voltage device (such as a core device), the high-voltage device has the characteristics of high working voltage Vdd and high driving capability. However, under high operating voltage, a strong transverse electric field is stored in a channel of the high-voltage device, so that carriers are subjected to impact ionization in the transportation process to generate extra electron hole pairs, and part of hot carriers are injected into a gate oxide layer, so that the threshold voltage of the device is increased, the saturation current and the carrier mobility are reduced, and the like, and the phenomenon is called as the HCI (hot carrier injection) effect. The HCI effect is a problem often encountered in high voltage device design and is a major factor affecting device characteristics and reliability, especially NMOS devices.
Currently, the LDD ion implantation process with high energy and low dose is mostly used to obtain deeper LDD junction to reduce the lateral electric field, which is the most effective means for improving the HCI effect. Specifically, the MOS device generates a substrate carrier while generating a hot carrier, a current formed by the substrate carrier is referred to as a substrate current Isub, and the size of the substrate current Isub can represent HCI, i.e., HCI is more serious when the substrate current Isub is larger. Specifically, as shown in fig. 1, the relationship between the LDD implantation energy and Isub is schematically shown, and as shown in fig. 1, increasing the LDD ion implantation energy can reduce Isub, thereby making the HCI effect lighter. However, as the size of MOSFET devices is continuously reduced, the gate oxide thickness and the polysilicon thickness are thinner and thinner, and the LDD junction is also changed, especially in the shallow process below 0.13 um. By increasing the energy of the LDD ion implantation, the HCI effect can be improved. But limited by the polysilicon thickness, the energy must be kept below a level that can break down the polysilicon layer, and thus tends not to control the HCI effect within an acceptable range.
Disclosure of Invention
The invention aims to provide a manufacturing method of an NMOS (N-channel metal oxide semiconductor) device, which aims to effectively improve the HCI (hydrogen induced interface) effect and improve the performance of the NMOS device.
The manufacturing method of the NMOS device provided by the invention comprises the following steps: s1: providing a substrate, wherein the substrate comprises isolation regions formed by an isolation process and an active region positioned between the isolation regions, and a P-well region is defined in the active region; s2: forming a thin gate oxide layer on the P-well region, and forming a polycrystalline silicon layer on the thin gate oxide layer; s3: defining a grid structure pattern area of the NMOS device through a photoetching exposure process, carrying out a phosphorus ion implantation process on a polycrystalline silicon layer in the grid structure pattern area of the NMOS device, and then carrying out a germanium ion implantation process on the polycrystalline silicon layer in the grid structure pattern area of the NMOS device so as to form an amorphous layer on the top of the polycrystalline silicon layer in the grid structure pattern area of the NMOS device; s4: forming a polysilicon gate mask layer, an anti-reflection layer and a photoresist layer on the polysilicon layer, then performing a photoetching process to form a gate structure, and performing a rapid thermal oxidation reaction, wherein the top of the gate structure comprises an amorphous layer formed in the step S3; s5: defining an N-type lightly doped source drain injection region by a photoetching exposure process, and performing an N-type lightly doped source drain injection process; and S6: and carrying out a source-drain ion implantation process to form the NMOS device.
Further, the substrate is a Si substrate.
Furthermore, the isolation process is a shallow trench isolation process.
Further, the thin gate oxide layer has a thickness of between 50 and 200 angstroms.
Further, the polysilicon layer has a thickness of 1000 angstroms.
Furthermore, the manufacturing method of the NMOS device is used in the manufacturing process of the NMOS device with the working voltage Vdd larger than 2.5V.
Furthermore, the manufacturing method of the NMOS device is used in the manufacturing process of the NMOS device with the working voltage Vdd of 5V.
Furthermore, the manufacturing method of the NMOS device is used for the process below 0.13 um.
The invention also provides a semiconductor device which comprises the NMOS device manufactured by the manufacturing method of the NMOS device.
The invention also provides a manufacturing method of the NMOS device, which comprises the following steps: s1: providing a substrate, wherein the substrate comprises isolation regions formed by an isolation process and an active region positioned between the isolation regions, and a P-well region and an N-well region are defined in the active region; s2: forming a thin gate oxide layer on the substrate, and forming a polysilicon layer on the thin gate oxide layer; s3: performing a germanium ion implantation process to form an amorphous layer on the top of the polysilicon layer; s4: forming a polysilicon gate mask layer, an anti-reflection layer and a photoresist layer on the polysilicon layer, then performing a photoetching process to form a gate structure, and performing a rapid thermal oxidation reaction, wherein the top of the gate structure comprises an amorphous layer formed in the step S3; s5: defining a lightly doped source drain injection region by a photoetching exposure process, and performing a lightly doped source drain injection process; and S6: and carrying out a source-drain ion implantation process to form an NMOS device and a PMOS device.
Further, step S3 includes defining a gate structure pattern region of the NMOS device by a photolithography exposure process after step S2, and then performing a germanium ion implantation process, where the germanium ion implantation process is a process of performing ion implantation on the polysilicon layer in the gate structure pattern region of the NMOS device, so as to form an amorphous layer on top of the polysilicon layer in the gate structure pattern region of the NMOS device.
Furthermore, the manufacturing method of the NMOS device is used for the process of more than 0.13 um.
Furthermore, the manufacturing method of the NMOS device is used in the manufacturing process of the NMOS device with the working voltage Vdd larger than 2.5V.
Furthermore, the manufacturing method of the NMOS device is used in the manufacturing process of the NMOS device with the working voltage Vdd of 5V.
The invention also provides a semiconductor device which comprises the NMOS device manufactured by the manufacturing method of the NMOS device.
In the manufacturing process of the NMOS device, a germanium amorphous layer is formed on the top of a polycrystalline silicon layer after the polycrystalline silicon is deposited, so that the injection depth of an N-type lightly doped source/drain injection process to the polycrystalline silicon layer can be reduced, the energy of the N-type lightly doped source/drain injection process can be increased to reach the range of effectively improving the HCI effect, the HCI effect is effectively improved, the performance of the NMOS device is improved, and only one Ge injection is required to be added after the phosphorus ion injection process is carried out on the polycrystalline silicon layer in a grid structure pattern area of the NMOS device.
Drawings
FIG. 1 is a graph showing the relationship between the LDD implant energy and Isub.
Fig. 2 is a flowchart of a method for manufacturing an NMOS device according to a first embodiment of the present invention.
Fig. 3 is a flowchart of a method for manufacturing an NMOS device according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In a first embodiment of the present invention, a method for manufacturing an NMOS device is provided, and specifically, referring to fig. 2, fig. 2 is a flowchart of a method for manufacturing an NMOS device according to a first embodiment of the present invention, where the method for manufacturing an NMOS device according to the first embodiment of the present invention includes:
s1: providing a substrate, wherein the substrate comprises isolation regions formed by an isolation process and an active region positioned between the isolation regions, and a P-well region is defined in the active region;
in an embodiment of the present invention, the substrate may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon on Insulator) substrate, or the like.
In an embodiment of the present invention, the isolation process is a Shallow Trench Isolation (STI) process.
S2: forming a thin gate oxide layer on the P-well region, and forming a polycrystalline silicon layer on the thin gate oxide layer;
in an embodiment of the present invention, the thickness of the thin gate oxide layer is between 50 angstroms and 200 angstroms.
In one embodiment of the present invention, the thickness of the polysilicon layer is 1000 angstroms, although there may be a deviation of 1000 angstroms, in one embodiment of the present invention, the deviation is within 20%, preferably within 10%, and more preferably within 5%.
S3: defining a grid structure pattern area of the NMOS device through a photoetching exposure process, carrying out a phosphorus (P) ion implantation process on a polycrystalline silicon layer in the grid structure pattern area of the NMOS device, and then carrying out a germanium (Ge) ion implantation process on the polycrystalline silicon layer in the grid structure pattern area of the NMOS device so as to form an amorphous layer on the top of the polycrystalline silicon layer in the grid structure pattern area of the NMOS device;
in order to inhibit the polysilicon depletion effect and reduce the electrical property of the gate oxide, the N-type polysilicon gate can be pre-doped immediately after the polysilicon deposition, and the ion implantation of the N-type polysilicon gate pre-doping generally adopts phosphorus implantation, namely, the phosphorus (P) ion implantation process is carried out on the polysilicon layer in the grid structure pattern region of the NMOS device.
The energy, the dose and the angle of the germanium (Ge) ion implantation process are not specifically limited, and the thickness of the formed amorphous layer is not limited, and the energy, the dose and the angle of the germanium (Ge) ion implantation process and the thickness of the formed amorphous layer can be changed according to the requirements of the actual process.
S4: forming a polysilicon gate mask layer, an anti-reflection layer and a photoresist layer on the polysilicon layer, then performing a photoetching process to form a gate structure, and performing a rapid thermal oxidation Reaction (RTO), wherein the top of the gate structure comprises an amorphous layer formed in the step S3;
a rapid thermal oxidation Reaction (RTO) may repair defects in the gate structure caused by the aforementioned processes.
S5: defining an N-type lightly doped source drain injection region by a photoetching exposure process, and performing an N-type lightly doped source drain injection process; and
s6: and carrying out a source-drain ion implantation process to form the NMOS device.
In summary, in the manufacturing process of the NMOS device, after the polysilicon is deposited, a germanium (Ge) amorphous layer is formed on the top of the polysilicon layer, so that the implantation depth of the N-type lightly doped source/drain implantation process on the polysilicon layer can be reduced, and therefore, the energy of the N-type lightly doped source/drain implantation process can be increased within the range of achieving the purpose of effectively improving the HCI effect, thereby effectively improving the HCI effect and the performance of the NMOS device.
In an embodiment of the present invention, the method for manufacturing an NMOS device is suitable for a high voltage NMOS device, such as an NMOS device having a working voltage Vdd greater than 2.5V. The effect is better, and the manufacturing method of the NMOS device is suitable for the manufacturing process of the NMOS device with the working voltage Vdd of 5V.
In an embodiment of the invention, the method for manufacturing the NMOS device is suitable for a process below 0.13 um. In the process below 0.13um, after the polysilicon deposition, the phosphorus (P) ion implantation process is carried out on the polysilicon layer in the grid structure pattern area of the NMOS device, and a Ge implantation is directly added after the phosphorus (P) ion implantation process, and the Ge implantation process and the phosphorus (P) ion implantation process share one mask plate, so the cost increase can be controlled to be minimum.
The present invention further provides a method for manufacturing an NMOS device according to a second embodiment, and specifically, referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing an NMOS device according to a second embodiment of the present invention, where the method for manufacturing an NMOS device according to the second embodiment of the present invention includes:
s1: providing a substrate, wherein the substrate comprises isolation regions formed by an isolation process and an active region positioned between the isolation regions, and a P-well region and an N-well region are defined in the active region;
in an embodiment of the present invention, the substrate may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon on Insulator) substrate, or the like.
In an embodiment of the present invention, the isolation process is a Shallow Trench Isolation (STI) process.
S2: forming a thin gate oxide layer on the substrate, and forming a polysilicon layer on the thin gate oxide layer;
in an embodiment of the present invention, the thickness of the thin gate oxide layer is between 50 angstroms and 200 angstroms.
In one embodiment of the present invention, the thickness of the polysilicon layer is 1000 angstroms, although there may be a deviation of 1000 angstroms, in one embodiment of the present invention, the deviation is within 20%, preferably within 10%, and more preferably within 5%.
S3: performing a germanium (Ge) ion implantation process to form an amorphous layer on top of the polysilicon layer;
the energy, the dose and the angle of the germanium (Ge) ion implantation process are not specifically limited, and the thickness of the formed amorphous layer is not limited, and the energy, the dose and the angle of the germanium (Ge) ion implantation process and the thickness of the formed amorphous layer can be changed according to the requirements of the actual process.
S4: forming a polysilicon gate mask layer, an anti-reflection layer and a photoresist layer on the polysilicon layer, then performing a photoetching process to form a gate structure, and performing a rapid thermal oxidation Reaction (RTO), wherein the top of the gate structure comprises an amorphous layer formed in the step S3;
a rapid thermal oxidation Reaction (RTO) may repair defects in the gate structure caused by the aforementioned processes.
S5: defining a lightly doped source drain injection region by a photoetching exposure process, and performing a lightly doped source drain injection process; and
s6: and carrying out a source-drain ion implantation process to form an NMOS device and a PMOS device.
In summary, in the manufacturing process of the semiconductor device, after the polysilicon is deposited, a germanium (Ge) amorphous layer is formed on the top of the polysilicon layer, so that the implantation depth of the lightly doped source/drain implantation process to the polysilicon layer can be reduced, the energy of the lightly doped source/drain implantation process can be increased to reach the range of effectively improving the HCI effect, the HCI effect is effectively improved, the performance of the semiconductor device is improved, and only one Ge implantation process needs to be added after the polysilicon layer is formed.
In an embodiment of the present invention, the method for manufacturing an NMOS device is suitable for a high voltage NMOS device, such as an NMOS device having a working voltage Vdd greater than 2.5V. The effect is better, and the manufacturing method of the NMOS device is suitable for the manufacturing process of the NMOS device with the working voltage Vdd of 5V.
In an embodiment of the present invention, step S3 further includes: after step S2, a gate structure pattern region of the NMOS device is defined through a photolithography exposure process, and then a germanium ion implantation process is performed, where the germanium ion implantation process is a process of performing ion implantation on a polysilicon layer in the gate structure pattern region of the NMOS device, so as to form an amorphous layer on top of the polysilicon layer in the gate structure pattern region of the NMOS device. Thus, compared to the prior art, the present invention needs to add a mask in step S3, but the PMOS region can be protected by the mask, thereby avoiding the influence of the germanium (Ge) ion implantation process on the PMOS device.
In an embodiment of the invention, the method for manufacturing the NMOS device is suitable for a process of more than 0.13 um. In the above process of 0.13um, after the deposition of the polysilicon, the phosphorous (P) ion implantation process is not generally required to be performed on the polysilicon layer in the gate structure pattern region of the NMOS device, so that, compared to the first embodiment of the present invention, the Ge implantation process in the second embodiment of the present invention will affect the performance of the PMOS device, otherwise, a mask is required to be added to protect the PMOS device region. However, the second embodiment of the present invention can effectively improve the HCI effect of the NMOS device as the first embodiment.
The present invention also provides a semiconductor device including an NMOS device manufactured by the method for manufacturing an NMOS device according to the first embodiment of the present invention or the method for manufacturing an NMOS device according to the second embodiment of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (15)
1. A method for manufacturing an NMOS device is characterized by comprising the following steps:
s1: providing a substrate, wherein the substrate comprises isolation regions formed by an isolation process and an active region positioned between the isolation regions, and a P-well region is defined in the active region;
s2: forming a thin gate oxide layer on the P-well region, and forming a polycrystalline silicon layer on the thin gate oxide layer;
s3: defining a grid structure pattern area of the NMOS device through a photoetching exposure process, carrying out a phosphorus ion implantation process on a polycrystalline silicon layer in the grid structure pattern area of the NMOS device, and then carrying out a germanium ion implantation process on the polycrystalline silicon layer in the grid structure pattern area of the NMOS device so as to form an amorphous layer on the top of the polycrystalline silicon layer in the grid structure pattern area of the NMOS device;
s4: forming a polysilicon gate mask layer, an anti-reflection layer and a photoresist layer on the polysilicon layer, then performing a photoetching process to form a gate structure, and performing a rapid thermal oxidation reaction, wherein the top of the gate structure comprises an amorphous layer formed in the step S3;
s5: defining an N-type lightly doped source drain injection region by a photoetching exposure process, and performing an N-type lightly doped source drain injection process; and
s6: and carrying out a source-drain ion implantation process to form the NMOS device.
2. The method of claim 1 wherein the substrate is a Si substrate.
3. The method of claim 1 wherein the isolation process is a shallow trench isolation process.
4. The method of claim 1 wherein the thin gate oxide layer has a thickness of between 50 and 200 angstroms.
5. The method of claim 1 wherein the polysilicon layer has a thickness of 1000 angstroms.
6. The method of claim 1, wherein the method is used in a process of manufacturing an NMOS device with a working voltage Vdd greater than 2.5V.
7. The method of claim 6, wherein the method is used in a process of manufacturing an NMOS device with a working voltage Vdd of 5V.
8. The method of claim 1 wherein the method is used for 0.13um or less processes.
9. A method for manufacturing an NMOS device is characterized by comprising the following steps:
s1: providing a substrate, wherein the substrate comprises isolation regions formed by an isolation process and an active region positioned between the isolation regions, and a P-well region and an N-well region are defined in the active region;
s2: forming a thin gate oxide layer on the substrate, and forming a polysilicon layer on the thin gate oxide layer;
s3: performing a germanium ion implantation process to form an amorphous layer on the top of the polysilicon layer;
s4: forming a polysilicon gate mask layer, an anti-reflection layer and a photoresist layer on the polysilicon layer, then performing a photoetching process to form a gate structure, and performing a rapid thermal oxidation reaction, wherein the top of the gate structure comprises an amorphous layer formed in the step S3;
s5: defining a lightly doped source drain injection region by a photoetching exposure process, and performing a lightly doped source drain injection process; and
s6: and carrying out a source-drain ion implantation process to form an NMOS device and a PMOS device.
10. The method of claim 9, wherein the step S3 further comprises defining a gate structure pattern region of the NMOS device by a photolithography exposure process after the step S2, and then performing a germanium ion implantation process, wherein the germanium ion implantation process is a process of performing ion implantation on the polysilicon layer in the gate structure pattern region of the NMOS device, so as to form an amorphous layer on top of the polysilicon layer in the gate structure pattern region of the NMOS device.
11. The method of claim 9 wherein the NMOS device is used for 0.13um or higher processes.
12. The method of claim 9 wherein the NMOS device is used in a process for manufacturing an NMOS device having an operating voltage Vdd greater than 2.5V.
13. The method of claim 12, wherein the method is used in a process of manufacturing an NMOS device with a working voltage Vdd of 5V.
14. A semiconductor device comprising an NMOS device fabricated by the method of fabricating an NMOS device of claim 1.
15. A semiconductor device comprising an NMOS device fabricated by the method of fabricating an NMOS device of claim 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112635403A (en) * | 2021-03-09 | 2021-04-09 | 晶芯成(北京)科技有限公司 | Preparation method of static random access memory |
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|---|---|---|---|---|
| CN112635403A (en) * | 2021-03-09 | 2021-04-09 | 晶芯成(北京)科技有限公司 | Preparation method of static random access memory |
| CN112635403B (en) * | 2021-03-09 | 2021-05-28 | 晶芯成(北京)科技有限公司 | Preparation method of static random access memory |
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Application publication date: 20200508 |