CN112635403A - Preparation method of static random access memory - Google Patents
Preparation method of static random access memory Download PDFInfo
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- 238000000034 method Methods 0.000 claims abstract description 41
- 238000005280 amorphization Methods 0.000 claims abstract description 32
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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Abstract
The invention provides a preparation method of a static random access memory, which executes pre-amorphization ion implantation on a part of polycrystalline silicon layer before executing N-type ion implantation, and can prevent injected ions from longitudinally diffusing and entering a P well region through a gate oxide layer in the N-type ion implantation process due to overlarge grain size in the polycrystalline silicon layer, thereby causing the reduction of the threshold voltage of a subsequently formed pull-down NMOS transistor and causing voltage mismatch. Meanwhile, the inhibition effect of N-type ion implantation on the polycrystalline depletion effect is improved. In addition, because the pull-up PMOS transistor and the pull-down NMOS transistor which are formed subsequently share the same grid structure, the execution of the pre-amorphization ion implantation can also inhibit the transverse diffusion of ions in the N-type ion implantation, avoid the influence of the N-type ion implantation on the threshold voltage of the pull-up PMOS transistor which is formed subsequently, relieve the problem of voltage mismatch and improve the performance of the device. And the same mask is used for two times of ion implantation, so that the preparation cost is low and the process is simple.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of a static random access memory.
Background
Static Random-Access Memory (SRAM) has the advantages of high speed, low power consumption, compatibility with standard processes, and the like, and is widely used in electronic products such as computers, mobile phones, digital cameras, multimedia players, and the like.
The static random access memory is composed of a plurality of static random access memory units, and each static random access memory unit is essentially composed of a pair of connected inverters. Referring to fig. 1, fig. 1 shows a six-transistor sram cell including two pass gate transistors W1 and W2, two pull-up transistors P1 and P2, and two pull-down transistors N1 and N2. Wherein, P1 and P2 are both PMOS tubes; n1 and N2 are both NMOS transistors. The gates of pass-gate transistors W1 and W2 are controlled by word line WL to determine whether the current SRAM cell is selected. A latch (latch) consisting of pull-up transistors P1 and P2 and pull-down transistors N1 and N2 is used to store the state. The storage state can be read through bit line BL and bit line BLB, and the storage state read from bit line BLB is in opposite phase.
However, as the process node of the semiconductor device is developed to 90nm and below, the sram is prone to voltage mismatch, which seriously affects the device performance.
Therefore, a new method for manufacturing the sram is needed to solve the voltage mismatch problem of the sram and improve the device performance.
Disclosure of Invention
The invention aims to provide a preparation method of a static random access memory, which aims to solve the problem of voltage mismatch of the static random access memory.
In order to solve the above technical problems, the present invention provides a method for manufacturing a static random access memory, comprising:
providing a substrate, wherein the substrate comprises a P well region for forming a pull-down NMOS transistor and an N well region for forming a pull-up PMOS transistor, a gate oxide layer and a polycrystalline silicon layer which are sequentially formed are covered on the substrate, and the gate oxide layer and the polycrystalline silicon layer both continuously extend from the P well region and cover the P well region to the N well region;
forming a patterned mask layer on the polysilicon layer to protect the corresponding polysilicon layer on the N well region and expose a corresponding part of the polysilicon layer on the P well region;
performing pre-amorphization ion implantation on the exposed part of the polycrystalline silicon layer on the P well region by taking the patterned mask layer as a mask;
performing N-type ion implantation on the exposed part of the polycrystalline silicon layer on the P well region by using the patterned mask layer as a mask and adopting N-type ions;
sequentially etching the polycrystalline silicon layer and the gate oxide layer to form a grid shared by a pull-down NMOS transistor and a pull-up PMOS transistor, wherein the grid extends from the N well region to the P well region; and part of the grid electrode positioned in the pull-down NMOS transistor area is N-type doped polycrystalline silicon after the combined action of the pre-amorphization ion implantation and the N-type ion implantation.
Optionally, in the method for manufacturing a static random access memory, when the pre-amorphization ion implantation and the N-type ion implantation are performed, the ion implantation is performed on the entire thickness of the polysilicon layer.
Optionally, in the method for manufacturing a static random access memory, an ion implantation dose in the pre-amorphization ion implantation is less than or equal to 1E15Per square centimeter.
Optionally, in the method for manufacturing a static random access memory, a dose of the pre-amorphization ion implantation is less than a dose of the N-type ion implantation.
Optionally, in the method for manufacturing a static random access memory, the ions injected in the pre-amorphization ion implantation include antimony ions, germanium ions, or silicon ions.
Optionally, in the preparation method of the static random access memory, after the N-type ion implantation and before the polysilicon layer and the gate oxide layer are sequentially etched to form the gate, the preparation method of the static random access memory further includes: and performing an annealing process on the polycrystalline silicon layer.
Optionally, in the preparation method of the static random access memory, after the gate is formed, a first sidewall is formed, and the first sidewall covers a sidewall of the gate.
Optionally, in the preparation method of the static random access memory, after the first side wall is formed, light-doped source-drain ion implantation is performed on the P-well region and the N-well region respectively by using the first side wall and the gate as masks, so as to form light-doped drain structures of a pull-down NMOS transistor and a pull-up PMOS transistor respectively.
Optionally, in the preparation method of the static random access memory, after the lightly doped drain structure is formed, a second side wall is formed, the second side wall covers the side wall of the first side wall, and the first side wall and the second side wall form a gate side wall of the gate.
Optionally, in the preparation method of the static random access memory, after the gate sidewall is formed, heavily doped source-drain ion implantation is performed on the P-well region and the N-well region respectively by using the gate sidewall and the gate as masks, so as to form source-drain electrodes of a pull-down NMOS transistor and a pull-up PMOS transistor.
In summary, the method for manufacturing the static random access memory provided by the invention comprises the following steps: providing a substrate, wherein the substrate comprises a P well region for forming a pull-down NMOS transistor and an N well region for forming a pull-up PMOS transistor, a gate oxide layer and a polycrystalline silicon layer which are sequentially formed are covered on the substrate, and the gate oxide layer and the polycrystalline silicon layer are extended and covered to the N well region continuously from the P well region. And forming a patterned mask layer on the polycrystalline silicon layer to protect the corresponding polycrystalline silicon layer on the N well region and expose a corresponding part of the polycrystalline silicon layer on the P well region. And performing pre-amorphization ion implantation on the exposed part of the polycrystalline silicon layer on the P well region by taking the patterned mask layer as a mask. And performing N-type ion implantation on the exposed part of the polycrystalline silicon layer on the P well region by using the patterned mask layer as a mask and adopting N-type ions. Sequentially etching the polycrystalline silicon layer and the gate oxide layer to form a grid shared by a pull-down NMOS transistor and a pull-up PMOS transistor, wherein the grid extends from the N well region to the P well region; and part of the grid electrode positioned in the pull-down NMOS transistor area is N-type doped polycrystalline silicon after the combined action of the pre-amorphization ion implantation and the N-type ion implantation.
Therefore, the pre-amorphization ion implantation is performed on part of the polycrystalline silicon layer before the N-type ion implantation is performed, so that the situation that the implanted ions longitudinally diffuse and enter the P well region through the gate oxide layer due to overlarge grain size in the polycrystalline silicon layer in the N-type ion implantation process, and the threshold voltage of a subsequently formed pull-down NMOS transistor is reduced to cause voltage mismatching can be prevented. Meanwhile, the inhibition effect of N-type ion implantation on the polycrystalline depletion effect is improved. In addition, the pull-up PMOS transistor and the pull-down NMOS transistor which are formed subsequently share the same grid structure, so that the execution of the pre-amorphization ion implantation can also inhibit the transverse diffusion of ions in the N-type ion implantation, avoid the influence of the N-type ion implantation on the threshold voltage of the pull-up PMOS transistor which is formed subsequently, further relieve the problem of voltage mismatch of the static random access memory and improve the performance of the device. And the same mask is used when the pre-amorphization ion implantation and the N-type ion implantation are carried out, so that the preparation cost is low, and the process is simple.
Drawings
FIG. 1 is a circuit diagram of a static random access memory cell;
FIG. 2 is a flow chart of a method for fabricating a static random access memory in an embodiment of the present invention;
FIGS. 3-13 are schematic diagrams of semiconductor structures at various steps of an embodiment of the present invention;
wherein the reference numerals are:
100-a substrate; 101-a gate oxide layer; 102 a-a polysilicon layer; 102 b-a gate; 103-patterning a mask layer; 104 a-a first lightly doped drain structure; 104 b-a second lightly doped drain structure; 105 a-first side wall; 105 b-a second sidewall;
a P-Well-P Well region; an N-Well-N Well region; ST 1-shallow trench isolation structure; CT-metal contact holes.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently. It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
To solve the above technical problem, the present embodiment provides a method for manufacturing a static random access memory, referring to fig. 2, the method for manufacturing a static random access memory includes:
step one S10: providing a substrate, wherein the substrate comprises a P well region for forming a pull-down NMOS transistor and an N well region for forming a pull-up PMOS transistor, a gate oxide layer and a polycrystalline silicon layer which are sequentially formed are covered on the substrate, and the gate oxide layer and the polycrystalline silicon layer are extended and covered to the N well region continuously from the P well region.
Step two S20: and forming a patterned mask layer on the polycrystalline silicon layer to protect the corresponding polycrystalline silicon layer on the N well region and expose a corresponding part of the polycrystalline silicon layer on the P well region.
Step three S30: and performing pre-amorphization ion implantation on the exposed part of the polycrystalline silicon layer on the P well region by taking the patterned mask layer as a mask.
Step four S40: and performing N-type ion implantation on the exposed part of the polycrystalline silicon layer on the P well region by using the patterned mask layer as a mask and adopting N-type ions.
Step five S50: sequentially etching the polycrystalline silicon layer and the gate oxide layer to form a grid shared by a pull-down NMOS transistor and a pull-up PMOS transistor, wherein the grid extends from the N well region to the P well region; and part of the grid electrode positioned in the pull-down NMOS transistor area is N-type doped polycrystalline silicon after the combined action of the pre-amorphization ion implantation and the N-type ion implantation.
The method for manufacturing the sram provided in this embodiment is specifically described below with reference to fig. 3 to 13:
step one S10: referring to fig. 3, a substrate 100 is provided, where the substrate 100 includes a P-well region for forming a pull-down NMOS transistor and an N-well region for forming a pull-up PMOS transistor, and the substrate 100 is covered with a gate oxide layer 101 and a polysilicon layer 102a, which are sequentially formed, and both the gate oxide layer 101 and the polysilicon layer 102a extend from the P-well region to the N-well region.
The P well region and the N well region are separated by a shallow trench isolation structure STI. Optionally, boron ions are implanted into the P-well region to form a pull-down NMOS transistor in the P-well region. Phosphorus ions are injected into the N well region so as to form a pull-up PMOS transistor in the N well region.
Further, the gate oxide layer 101 is made of a material including, but not limited to, silicon dioxide, and the gate oxide layer 101 may be formed by a thermal oxidation process. The polysilicon layer 102a may be formed by a chemical vapor deposition process.
Step two S20: referring to fig. 4-7, a patterned mask layer 103 is formed on the polysilicon layer 102a to protect the polysilicon layer 102a corresponding to the nwell region and expose a portion of the polysilicon layer 102a corresponding to the pwell region.
Fig. 5 is a top view of a semiconductor structure, fig. 6 is a cross-sectional view of a-a 'in fig. 5, and fig. 7 is a cross-sectional view of B-B' in fig. 5. The patterned mask layer 103 covers the polysilicon layer 102a over the nwell region to avoid affecting the polysilicon layer 102a over the nwell region in a subsequent ion implantation process. Wherein, the exposed portion of the polysilicon layer 102a is used as a part of a gate structure of a pull-down NMOS transistor to be formed subsequently. Optionally, the patterned mask layer 103 is a photoresist layer.
Step three S30: referring to fig. 8, a pre-amorphization ion implantation (PAI) is performed on the exposed portion of the polysilicon layer 102a on the P-well region by using the patterned mask layer 103 as a mask.
Referring to fig. 1, in the sram, a gate a2 of P1 is connected to a gate a5 of N1, and a gate B2 of P2 is connected to a gate B5 of N2. Therefore, in order to meet the trend of reducing the critical dimension of the semiconductor device and realize more space saving, the same gate can be shared by P1 and N1 and the same gate can be shared by P2 and N2. However, the design method results in that the formed pull-down NMOS transistor is prone to generate poly depletion effect, which affects the performance of the pull-down NMOS transistor, and thus affects the whole sram. In contrast, this design does not significantly affect the performance of the pull-up PMOS transistor. Therefore, when the pull-down NMOS transistor is prepared, N-type ions need to be implanted into the gate of the pull-down NMOS transistor to alleviate the poly depletion effect.
Meanwhile, the grain size of the polysilicon in the polysilicon layer 102a is increased by injecting N-type ions, and as the grain size is increased, the injected N-type ions are easily diffused transversely to the gate portion corresponding to the pull-up PMOS transistor, thereby affecting the pull-up PMOS transistor, and are diffused longitudinally, not only the polycrystalline depletion effect cannot be well relieved, but also the N-type ions are diffused into the P-well region by longitudinal diffusion and remain in a channel of a subsequently formed NMOS device, or enter a subsequently formed source and drain, so that the threshold voltage of the pull-down NMOS transistor is pulled down, and the voltage mismatch of the static random access memory is caused.
Therefore, in order to avoid the above problem, the present embodiment provides a method for manufacturing a sram, wherein a pre-amorphization ion implantation is performed on the polysilicon layer 102a on the P-well region before the N-type ion implantation is performed to suppress grain enlargement of the polysilicon, thereby alleviating the above problem.
Further, ion implantation in the pre-amorphization ion implantationThe dosage is less than or equal to 1E15Per square centimeter. Wherein the energy of the pre-crystallization ion implantation depends on the thickness of the polysilicon layer 102a, and the greater the thickness of the polysilicon layer 102a, the greater the implantation energy. And the pre-crystallization ion implantation is performed for the entire thickness of the polysilicon layer 102a for superior effect. The ions injected in the pre-amorphization ion injection comprise antimony ions, germanium ions or silicon ions.
Step four S40: referring to fig. 9, N-type ion implantation is performed on the exposed portion of the polysilicon layer 102a on the P-well region by using N-type ions with the patterned mask layer 103 as a mask.
Wherein the dose of the pre-amorphization ion implantation is smaller than that of the N-type ion implantation. And N-type ion implantation is performed for the entire thickness of the polysilicon layer 102a when N-type ion implantation is performed. The method for manufacturing the static random access memory provided by the embodiment adopts the same mask, namely the patterned mask layer 103, so that the pre-amorphization ion implantation and the N-type ion implantation are realized, the manufacturing cost is saved, and the operation process is simple. And N-type ion implantation is performed on the basis of pre-amorphization ion implantation, so that the polycrystalline depletion effect can be better inhibited, the transverse and longitudinal diffusion of the implanted N-type ions can be avoided, and the problem of voltage mismatch of the static random access memory is solved.
Further, after N-type ion implantation is performed on the exposed portion of the polysilicon layer 102a, the patterned mask layer 103 is removed. Then, an annealing process is performed on the polysilicon layer 102a to activate the doped ions.
Step five S50: referring to fig. 10, the polysilicon layer 102a and the gate oxide layer 101 are sequentially etched to form a gate 102b shared by a pull-down NMOS transistor and a pull-up PMOS transistor, wherein the gate 102b extends from the nwell region to the P-well region; and a part of the gate 102b in the pull-down NMOS transistor region is N-type doped polysilicon obtained by the combined action of the pre-amorphization ion implantation and the N-type ion implantation.
Further, referring to fig. 10-12, after the gate 102b is formed, an oxide layer is grown on the surface of the exposed substrate 100 and the surface of the gate 102b, and then a first sidewall 105a is formed by etching, where the first sidewall 105a covers the sidewall of the gate 102 b. After the first sidewall 105a is formed, a first photoresist layer (not shown) is formed to cover each film layer on the N-well region, expose each film layer on the P-well region, and perform lightly doped source/drain ion implantation on the P-well region with the first sidewall 105a on the P-well region as a barrier, so as to form a first lightly doped drain structure 104 a. The lightly doped source-drain ion implantation is used for weakening the hot carrier effect of the gate 102b region, and the optional implanted ions are arsenic ions. Similarly, the first photoresist layer is removed to form a second photoresist layer (not shown), the second photoresist layer covers each film layer on the P-well region to expose each film layer on the N-well region, and then lightly doped source/drain ion implantation is performed on the N-well region to form a second lightly doped drain structure 104 b. Optionally, the fourth ion implanted ions include boron difluoride.
Further, after the first lightly doped drain structure 104a and the second lightly doped drain structure 104b are formed, a second sidewall 105b is formed, and the second sidewall 105b covers the first sidewall. Optionally, the second sidewall spacer is made of silicon nitride. The first sidewall 105a and the second sidewall 105b form a gate sidewall. After the gate sidewall spacers are formed, as shown in fig. 11-12, heavily doped source-drain ion implantation is performed on the P-well region and the N-well region respectively by using the gate sidewall spacers 105 and the gate 102 as masks, so as to form a source S and a drain D of a pull-down NMOS transistor and a pull-up PMOS transistor. As shown in fig. 13, the gate 102b is shared by the pull-down NMOS transistor and the pull-up PMOS transistor.
In summary, in the method for manufacturing the sram provided in this embodiment, pre-amorphization ion implantation is performed on a portion of the polysilicon layer 102a before N-type ion implantation is performed, so that it can be prevented that, in the N-type ion implantation process, because the grain size in the polysilicon layer 102a is too large, implanted ions longitudinally diffuse and penetrate through the gate oxide layer 101 into the P-well region, thereby causing a decrease in threshold voltage of a subsequently formed pull-down NMOS transistor, which causes a voltage mismatch. Meanwhile, the inhibition effect of N-type ion implantation on the polycrystalline depletion effect is improved. In addition, the pull-up PMOS transistor and the pull-down NMOS transistor which are formed subsequently share the same grid structure, so that the execution of the pre-amorphization ion implantation can also inhibit the transverse diffusion of ions in the N-type ion implantation, avoid the influence of the N-type ion implantation on the threshold voltage of the pull-up PMOS transistor which is formed subsequently, further relieve the problem of voltage mismatch of the static random access memory and improve the performance of the device. And the same mask is used when the pre-amorphization ion implantation and the N-type ion implantation are carried out, so that the preparation cost is low, and the process is simple.
It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
Claims (10)
1. A method for manufacturing a static random access memory is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a P well region for forming a pull-down NMOS transistor and an N well region for forming a pull-up PMOS transistor, a gate oxide layer and a polycrystalline silicon layer which are sequentially formed are covered on the substrate, and the gate oxide layer and the polycrystalline silicon layer both continuously extend from the P well region and cover the P well region to the N well region;
forming a patterned mask layer on the polysilicon layer to protect the corresponding polysilicon layer on the N well region and expose a corresponding part of the polysilicon layer on the P well region;
performing pre-amorphization ion implantation on the exposed part of the polycrystalline silicon layer on the P well region by taking the patterned mask layer as a mask;
performing N-type ion implantation on the exposed part of the polycrystalline silicon layer on the P well region by using the patterned mask layer as a mask and adopting N-type ions;
sequentially etching the polycrystalline silicon layer and the gate oxide layer to form a grid shared by a pull-down NMOS transistor and a pull-up PMOS transistor, wherein the grid extends from the N well region to the P well region; and part of the grid electrode positioned in the pull-down NMOS transistor area is N-type doped polycrystalline silicon after the combined action of the pre-amorphization ion implantation and the N-type ion implantation.
2. The method of claim 1, wherein the ion implantation is performed for the entire thickness of the polysilicon layer during both the pre-amorphization ion implantation and the N-type ion implantation.
3. The method of claim 1, wherein the pre-amorphization ion implantation is performed at an ion implantation dose of 1E or less15Per square centimeter.
4. The method of claim 1, wherein a dose of the pre-amorphization implant is less than a dose of the N-type implant.
5. The method of claim 1, wherein the ions implanted in the pre-amorphization implantation comprise antimony ions, germanium ions or silicon ions.
6. The method of claim 1, wherein after said implanting of N-type ions and before etching said polysilicon layer and said gate oxide layer in sequence to form said gate, said method further comprises: and performing an annealing process on the polycrystalline silicon layer.
7. The method of claim 1, wherein a first sidewall is formed after the gate is formed, the first sidewall covering a sidewall of the gate.
8. The method according to claim 7, wherein after the first sidewall is formed, lightly doped source-drain ion implantation is performed on the P-well region and the N-well region respectively, using the first sidewall and the gate as masks, to form lightly doped drain structures of a pull-down NMOS transistor and a pull-up PMOS transistor respectively.
9. The method according to claim 8, wherein a second sidewall is formed after the lightly doped drain structure is formed, the second sidewall covers a sidewall of the first sidewall, and the first sidewall and the second sidewall form a gate sidewall of the gate.
10. The method according to claim 9, wherein after the gate sidewall is formed, heavily doped source-drain ion implantation is performed on the P-well region and the N-well region, respectively, using the gate sidewall and the gate as masks, to form source-drain electrodes of a pull-down NMOS transistor and a pull-up PMOS transistor.
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