KR100468704B1 - DRAM device and manufacturing method thereof - Google Patents

Abstract

Disclosed are a DRMA device and a method of manufacturing the same. According to the present invention, a DRAM device includes a cell array region transistor having a single source / drain region, a peripheral circuit region including a source / drain region of an LDD structure, and a peripheral circuit region including a source / drain region of a double LDD structure. PMOS transistors. The source / drain region of the double LDD structure of the peripheral circuit region PMOS transistor is composed of a high concentration p-type impurity region, a low concentration p-type impurity region, and a low concentration n-type impurity region. Since the PMOS transistors in the peripheral circuit region are formed in a double LDD structure, short channel effects can be prevented and hot carrier effects can be effectively reduced.

Description

DDR device and its manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a dynamic random access memory (DRAM) and a method of manufacturing the same.

DRAM devices are roughly divided into cell array regions and peripheral circuit regions. In the cell array region, a plurality of memory cells in which data is stored are arranged in a matrix form, and a circuit for driving memory cells of the cell array region is arranged in a peripheral circuit region.

Since transistors arranged in the cell array region and the peripheral circuit region are different in their respective uses, the characteristics of the transistor should be optimized for the purpose. Therefore, the transistors of the cell array region are formed of only a single source / drain region composed of low concentration impurity regions, and the transistors of the peripheral circuit region are formed of source / drain regions of a lightly doped drain (LDD) structure.

1 and 2, a conventional DRAM device will be described.

First, referring to FIG. 1, on the semiconductor substrate 10 of the cell array region, a transistor including a gate 12 having a spacer 20 and a source / drain region composed of only a low concentration of n-type impurity region 22 is formed. It is. On the semiconductor substrate 10 in the peripheral circuit region, a source / drain region comprising a gate 14 having an LDD structure forming spacer 20 and a low concentration n-type impurity region 18 and a high concentration n-type impurity region 26. A PMOS transistor comprising a gate 16 formed with an NMOS transistor and an LDD structure forming spacer 20 and a source / drain region including a low concentration of p-type impurity region 17 and a high concentration of p-type impurity region 24 are provided. Formed.

Phosphorus (P) and arsenic (As) may be used as n-type impurities. Since arsenic has a higher molecular weight than phosphorus, it has a disadvantage of damaging a substrate during ion implantation to generate a junction leakage current, and phosphorus has a large diffusion rate. There is a disadvantage of increasing the short channel effect. Therefore, the n-type impurity region 22 of the cell array region is formed using phosphorus, and the n-type region of the peripheral circuit region is formed in which the reduction of the junction leakage current is most important in order to ensure a reliable on / off operation and a long refresh time. The impurity regions 18 and 26 are formed using arsenic.

As mentioned above, since phosphorus has a high diffusion and has a short channel effect, the n-type impurity region 22 of the NMOS transistor of the cell array region is formed by forming a spacer 20 and then implanting phosphorous ions. If possible, increase the effective channel length. In this case, subsequent heat treatment must be performed so that the n-type impurity region 22 can be diffused to the edge portion of the gate 12. However, it is not easy to control the n-type impurity region to be diffused only to a desired position, and the impurities in the peripheral circuit region are also diffused together to reduce the effective channel length of the transistors in the peripheral circuit region. In particular, since the p-type impurity regions 17 and 24 constituting the PMOS transistor in the peripheral circuit region are formed of boron (B) having a very high diffusivity, the problem of reducing the effective channel length becomes more serious.

The proposed structure to solve this problem is shown in FIG. That is, as shown in Fig. 2, the LDD region of the PMOS transistor is not formed as a p-type impurity region having a high diffusivity, but is formed as a n-type impurity region 18 having a low concentration. The low concentration of the n-type impurity region 18 can prevent the problem that the effective channel length of the PMOS transistor is reduced during the heat treatment process for diffusing the low-concentration n-type impurity region 22 of the cell array region NMOS transistor. have. However, when the structure of the PMOS transistor is formed as shown in Fig. 2, the high concentration of the p-type impurity region 24 must be overlapped with the low concentration of the n-type impurity region 18 by a subsequent heat treatment process. There is a difficulty in controlling the thickness and heat treatment process conditions well. In addition, since the concentration of the LDD region 18 becomes high due to the diffusion of a high concentration of p-type impurities, there is a new problem that the hot carrier effect cannot be prevented properly.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a DRAM device having transistors having different structures optimized for use of transistors arranged in a cell array region and a peripheral circuit region.

Another object of the present invention is to provide a manufacturing method suitable for manufacturing a DRAM device having transistors of different structures optimized for the use of transistors arranged in the cell array region and the peripheral circuit region.

The DRAM device of the present invention for achieving the above technical problem is a cell array region transistor having a single source / drain region, a peripheral circuit region NMOS transistor having a source / drain region of the LDD structure and a source / drain region of a dual LDD structure And a peripheral circuit region PMOS transistor having a.

In the present invention, the source / drain region of the double LDD structure includes a high concentration of p-type impurity region, a low concentration of p-type impurity region, and a low concentration of n-type impurity region, and the low concentration of n-type impurity region is a channel. It is preferred to have a structure adjacent to the area. In particular, the low concentration n-type impurity region is arsenic ions, the low concentration p-type impurity region is boron or boron fluoride ion, the high concentration p-type impurity region is boron fluoride ion, and the single source / drain region is Preferably, the phosphorus ions and the source / drain regions of the LDD structure are formed of arsenic ions.

The cell array region transistor may include a single spacer on a gate sidewall, and the peripheral circuit region NMOS transistor and a PMOS transistor may include a double spacer on a gate sidewall.

And a silicide film on the gate upper surface of the peripheral circuit region NMOS transistor and the source / drain region of the LDD structure, and on the gate upper surface of the peripheral circuit region PMOS transistor and the source / drain region of the double LDD structure, It is preferable to include a silicide prevention film on the gate top surface, the spacer and the single source region of the cell array region transistor.

According to the manufacturing method of the present invention for achieving the above another technical problem, first, a plurality of first gates and a plurality of second gates having a length greater than the first gate is formed on a semiconductor substrate. Next, a low concentration n-type impurity region is formed in the semiconductor substrate adjacent to the edges of the plurality of second gates. Subsequently, a first spacer is formed on sidewalls of the plurality of first gates and the plurality of second gates, respectively, and then a low concentration is formed on the semiconductor substrate adjacent to edges of the plurality of first spacers formed on the sidewalls of the first gates. Low concentration p-type impurity regions are formed in the semiconductor substrate adjacent to edges of the plurality of first spacers formed on sidewalls of gates to be used as gates of a PMOS transistor among the plurality of second gates. Next, second spacers are formed on the first spacers formed on sidewalls of the plurality of second gates, respectively, to form double spacers. Finally, the high concentration n-type impurity regions are formed on the region in which the low concentration p-type impurity regions are formed in the semiconductor substrate adjacent to the edges of the plurality of second spacers formed on the region in which the low concentration n-type impurity regions are formed. High concentration p-type impurity regions are formed in the semiconductor substrate adjacent to the edges of the plurality of second spacers.

In the present invention, the low concentration n-type impurity regions formed in the semiconductor substrate adjacent to the edges of the plurality of second gates form arsenic ions adjacent to the edges of the plurality of first spacers formed on the sidewalls of the first gates. Low concentration n-type impurity regions formed in the semiconductor substrate may form phosphorus ions on the semiconductor substrate adjacent to edges of the plurality of first spacers formed on sidewalls of gates to be used as gates of a PMOS transistor among the plurality of second gates. The low concentration p-type impurity regions to be formed include high concentration n of boron ions or boron fluoride ions in the semiconductor substrate adjacent to edges of the plurality of second spacers formed on the region where the low concentration n-type impurity regions are formed. Type impurity regions contain arsenic ions, the low concentration The high concentration of p-type impurity regions formed in the semiconductor substrate adjacent to the edges of the plurality of second spacers formed on the region where the p-type impurity regions are formed is preferably formed by implanting boron fluoride ions.

In example embodiments, the forming of the double spacer may be formed on an upper surface of the first gates, on the plurality of first spacers formed on sidewalls of the first gates, and on the semiconductor substrate adjacent to an edge of the first spacers. It is preferable to proceed simultaneously with the step of forming the suicide prevention film pattern on the low concentration n-type impurity regions, and after forming the high concentration of n-type impurity regions and the high concentration of p-type impurity regions, It is further provided. First, a transition metal film is formed on the entire surface of the resultant product of the high concentration n-type impurity regions and the high concentration p-type impurity regions. Next, the resultant in which the transition metal film is formed is heat-treated to form a silicide film on the top surfaces of the plurality of second gates, on the high concentration n-type impurity region, and on the high concentration p-type impurity region. Finally, the transition metal film which remains unreacted without forming a silicide film during the heat treatment step is removed.

In the DRAM device according to the present invention, since the PMOS transistors in the peripheral circuit region have a double LDD structure, the short channel effect can be prevented and the hot carrier effect can be effectively reduced.

DETAILED DESCRIPTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and fully understand the scope of the invention to those skilled in the art. It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions are highlighted for clarity.

3-12 are fabricated for manufacturing a DRAM device having transistors of different structures optimized for the use of transistors arranged in the cell array region, core region and peripheral circuit region according to one embodiment of the present invention. Cross-sectional views of process intermediate stage structures are shown.

Referring to FIG. 3, first, a conductive film such as a polycrystalline silicon film is deposited on a semiconductor substrate 100, and then patterned to form a gate 102 of a cell array region NMOS transistor, gates of a peripheral circuit region NMOS, and a PMOS transistor ( 104 and 106, respectively. Since the cell array region is directly affected by the design rule compared to the peripheral circuit region, the length of the gate 102 formed in the cell array region is smaller than the length of the gates 104 and 106 formed in the peripheral circuit region. Next, after the photoresist is coated on the entire surface of the resultant gates 102, 104, and 106, the photoresist is etched by a photo process to form a first photoresist pattern 108 that exposes a peripheral circuit region. Subsequently, n-type impurity ions 109 such as arsenic ions are implanted into the semiconductor substrate 100 using the first photoresist pattern 108 as an ion implantation mask to form a low concentration n-type impurity region 110.

Referring to FIG. 4, after the first photoresist pattern 108 is removed, an insulating film, for example, a nitride film is deposited on the entire surface of the resultant product having the low concentration n-type impurity region 110 formed thereon. Subsequently, the insulating layer is anisotropically etched to form first spacers 112 on sidewalls of the gate 102 of the cell array region NMOS transistor, the gates 104 and 106 of the peripheral circuit region NMOS and PMOS transistors, respectively.

Next, as shown in FIG. 5, the second photoresist pattern 114 exposing only the cell array region is formed on the semiconductor substrate 100 on which the first spacer 112 is formed, and then the second photoresist pattern is formed. Using the 114 as an ion implantation mask, an n-type impurity 115, for example, phosphorus ion, is implanted to form a low concentration n-type impurity region 116 of the cell array region NMOS transistor to complete the NMOS transistor.

Subsequently, after the second photoresist pattern 114 is removed, as shown in FIG. 6, a third photoresist pattern 118 is formed to expose only the region where the PMOS transistor of the peripheral circuit region is to be formed. P-type impurity ions 119 such as boron or boron fluoride (BF ₃ ) ions are implanted using the third photoresist pattern 118 as an ion implantation mask to form a low concentration of p-type impurity region 120.

Subsequently, after the third photoresist pattern 118 is removed, as shown in FIG. 7, the insulating film 122 to be formed of the silicide prevention film pattern and the second spacer on the entire surface of the substrate 100, for example, 200 nm to It is formed to a thickness of 300Å.

Next, as shown in FIG. 8, after forming the fourth photoresist pattern 124 exposing only the peripheral circuit region, the nitride film 122 formed in the peripheral circuit region is anisotropically etched to form the NMOS and PMOS transistors of the peripheral circuit region. A second spacer 122S is formed on the first spacer 112 of the gates 104 and 106 to form a double spacer structure, and at the same time, the silicide prevention layer pattern 122P is formed on the entire cell array region.

Subsequently, after the fourth photoresist pattern 124 is removed, a fifth photoresist pattern 126 is formed to expose only a region where the NMOS transistor of the peripheral circuit region is to be formed, as shown in FIG. 9. Next, the n-type impurity 127, for example, arsenic, is implanted using the fifth photoresist pattern 126 as an ion implantation mask to form a high concentration n-type impurity region 128. As a result, the NMOS transistor of the peripheral circuit region including the source / drain regions of the LDD structure including the low concentration n-type impurity region 110 and the high concentration n-type impurity region 128 is completed.

After the fifth photoresist pattern 126 is removed, a sixth photoresist pattern 130 is formed to expose a region where the PMOS transistor of the peripheral circuit region is to be formed, as shown in FIG. 10. The p-type impurity ions 131 such as boron fluoride are ion-implanted using the sixth photoresist pattern 130 as an ion implantation mask to form a high concentration of the p-type impurity region 132. As a result, a PMOS transistor having a double LDD structure source / drain region including a low concentration n-type impurity region 110, a low concentration p-type impurity region 120, and a high concentration p-type impurity region 132 is completed.

Next, after the sixth photoresist pattern 130 is removed, a silicide forming process for lowering power consumption and operating speed of the DRAM device is performed. First, as shown in FIG. 11, a transition metal film 134 such as Ti, Ta, Co, or Mo is stacked on the entire surface of the resultant transistors.

Subsequently, the transition metal is heat-treated to form the transition metal film 134, thereby exposing the high concentration n-type impurity region 128 of the exposed polysilicon and peripheral circuit region NMOS transistors on the peripheral circuit region gates 104 and 106. And react with the exposed silicon of the high concentration of p-type impurity region 132 of the PMOS transistors to form silicide. During the silicide formation process, the silicide prevention film pattern 122P formed on the cell array region prevents silicide from being formed on the transistors of the cell array region. This is because the silicidation reaction of the transistors in the cell array region causes a problem that the leakage current increases.

After silicide formation, the silicide, the substrate 100 and the first and second spacers 112, 122S remove the unreacted transition metal by selective etching that is not etched. As a result, a silicide film 136 is formed on the high concentration n-type impurity region 128 of the peripheral circuit region NMOS transistor and the high concentration p-type impurity region 132 of the PMOS transistors and on the polysilicon gates, respectively. As a result, the surface resistance of the shallow junction region of the source / drain region is lowered to increase the operating speed of the DRAM device.

A DRAM device having transistors of different structures optimized for the use of transistors arranged in a cell array region and a peripheral circuit region formed according to the manufacturing method of the present invention described with reference to FIGS. A result will be described with reference to FIG. 12.

Referring to FIG. 12, an NMOS transistor in a cell array region is composed of a single source 112 and a single source / drain region 116 composed of a low concentration of n-type impurity regions. On the other hand, the transistors in the peripheral circuit region are composed of double spacers 112 and 122S. The NMOS transistor in the peripheral circuit region is composed of an LDD structure source / drain region including a low concentration n-type impurity region 110 and a high concentration n-type impurity region 128, whereas the PMOS transistor in the peripheral circuit region has a low concentration n. It is composed of a source / drain region of a double LDD structure composed of a type impurity region 110, a low concentration p-type impurity region 120, and a high concentration p-type impurity region 132. Since the PMOS transistors in the peripheral circuit region are formed in a double LDD structure, short channel effects can be prevented and hot carrier effects can be effectively reduced.

While the preferred embodiments of the invention have been described in the drawings and the description, specific terms have been used, which are used in technical concepts rather than for the purpose of limiting the scope of the invention as set forth in the claims below. Therefore, the present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.

In the DRAM device according to the present invention, a double LDD including a source drain region of a peripheral circuit region PMOS transistor having a low concentration n-type impurity region 110, a low concentration p-type impurity region 120, and a high concentration p-type impurity region 132. Form into a structure. Therefore, since the low concentration n-type impurity region 110 having a diffusion degree smaller than that of the p-type impurity is adjacent to the channel, the n-type impurity region 116 of the cell array region can be diffused to the edge portion of the gate 102. In the subsequent heat treatment process, the problem of reducing the effective channel length due to the side diffusion of the impurity region of the PMOS transistor is prevented. In addition, since the n-type impurity region 110 is thinner than the n-type impurity region 18 of the conventional LDD structure shown in FIG. 2, the low-concentration p-type impurity region 120 is formed of the n-type impurity region 110. Can easily overlap. Since the high concentration of p-type impurity region 132 and the low concentration of n-type impurity region 110 are not in direct contact with each other, the low concentration of p-type impurity region 120 is formed between these two regions. Due to the diffusion, the LDD region 110 may have a high concentration, thereby effectively preventing the hot carrier effect.

Fig. 1 is a cross sectional view of a conventional DRAM device, showing a NMOS transistor in a cell array region, an NMOS transistor and a PMOS transistor in a peripheral circuit region, respectively.

FIG. 2 is a cross-sectional view of a conventional DRAM device in which the source / drain region structure of the DRMA device shown in FIG. 1 and the PMOS transistor in the peripheral circuit region are different.

3-12 are cross-sectional views of intermediate stage structures of a fabrication process for fabricating a DRAM device in accordance with one embodiment of the present invention.

Claims (17)

A cell array region transistor having a single source / drain region; A peripheral circuit region NMOS transistor having a source / drain region of an LDD structure; And And a peripheral circuit region PMOS transistor having a source / drain region of a dual LDD structure. The method of claim 1, wherein the source / drain region of the double LDD structure has a high concentration of p-type impurity regions, a low concentration of p-type impurity regions, and a low concentration of n-type impurity regions. And a structure adjacent to the channel region. 3. The method of claim 2, wherein the low concentration n-type impurity region is formed of arsenic ions, the low concentration p-type impurity region is formed of boron or boron fluoride ions, and the high concentration p-type impurity region is formed of boron fluoride ions. DRAM device. The DRAM device of claim 3, wherein the single source / drain region is formed of phosphorus ions, and the source / drain region of the LDD structure is formed of arsenic ions. The method of claim 1, wherein the cell array region transistor has a single spacer on the gate sidewall, And the peripheral circuit region NMOS transistor and the PMOS transistor have double spacers on a gate sidewall. 6. A silicide according to claim 5, wherein the gate top surface of the peripheral circuit region NMOS transistor and the source / drain region of the LDD structure and the gate top surface of the peripheral circuit region PMOS transistor and the source / drain region of the double LDD structure are formed. A DRAM device, further comprising a film. 7. The DRAM device of claim 6, further comprising a silicide prevention film on a gate top surface, a spacer, and a single source region of the cell array region transistor. The DRAM device of claim 1, wherein a gate length of the cell array region transistor is smaller than a gate length of the peripheral circuit region NMOS and PMOS transistors. Forming a plurality of first gates and a plurality of second gates of greater length than the first gate on the semiconductor substrate; Forming a low concentration n-type impurity region in the semiconductor substrate adjacent to the edges of the plurality of second gates; Forming first spacers on sidewalls of the plurality of first gates and the plurality of second gates, respectively; Low concentration n-type impurity regions are formed on the sidewalls of the gates to be used as gates of the PMOS transistors of the second gates in the semiconductor substrate adjacent to the edges of the plurality of first spacers formed on the sidewalls of the plurality of first gates. Forming low concentration p-type impurity regions in the semiconductor substrate adjacent to edges of the plurality of first spacers; Forming a double spacer by forming second spacers on the first spacers formed on sidewalls of the plurality of second gates, respectively; And High concentrations of n-type impurity regions in the semiconductor substrate adjacent to edges of the second spacers formed on the region where only the low concentration of n-type impurity regions are formed are formed on the region where the low concentration of p-type impurity regions are formed. Forming a high concentration of p-type impurity regions in the semiconductor substrate adjacent to an edge. The method of claim 9, wherein the forming of the low concentration n-type impurity region in the semiconductor substrate adjacent to the edges of the plurality of second gates is performed by implanting arsenic ions. 10. The method of claim 9, wherein forming a low concentration of n-type impurity regions in the semiconductor substrate adjacent to edges of the plurality of first spacers formed on sidewalls of the first gates is performed by implanting phosphorus ions. Method of manufacturing a DRAM device. The method of claim 9, wherein the forming of low concentration p-type impurity regions in the semiconductor substrate adjacent to edges of the plurality of first spacers formed on sidewalls of gates to be used as gates of a PMOS transistor among the plurality of second gates is performed. A method of manufacturing a DRAM device, characterized by advancing boron ions or boron fluoride ions. The method of claim 9, wherein the forming of the high concentration n-type impurity regions in the semiconductor substrate adjacent to the edges of the plurality of second spacers formed on the region where the low concentration n-type impurity regions are formed is performed by implanting arsenic ions. A method of manufacturing a DRAM device, characterized by the above-mentioned. 10. The method of claim 9, wherein forming a high concentration of p-type impurity regions in the semiconductor substrate adjacent to edges of the plurality of second spacers formed on the region where the low concentration of p-type impurity regions is formed is implanted boron fluoride ions. A method of manufacturing a DRAM device, characterized in that it is carried out. The method of claim 9, wherein the forming of the double spacers is performed on the semiconductor substrate, the upper surface of the first gates, the plurality of first spacers formed on sidewalls of the first gates, and the semiconductor substrate adjacent to an edge of the first spacers. And forming a suicide prevention film pattern on the formed low concentration n-type impurity regions. The method of claim 15, wherein the forming of the double spacer and the silicide prevention layer is performed. Forming an insulating film over the entire surface of the resultant p-type impurity regions formed thereon; And Low concentration n-type impurity regions formed on an upper surface of the first gates, on the plurality of first spacers formed on sidewalls of the first gates, and on the semiconductor substrate adjacent to an edge of the first spacers by anisotropically etching the insulating layer. Forming a silicide protection layer pattern thereon and forming a second spacer on the plurality of first spacers formed on sidewalls of the plurality of second gates, respectively. The method of claim 15, after forming the high concentration of n-type impurity regions and the high concentration of p-type impurity regions. Forming a transition metal film on the entire surface of the resultant portion of the high concentration n-type impurity regions and the high concentration p-type impurity regions; Heat-treating the resultant on which the transition metal film is formed to form a silicide film on the upper surfaces of the plurality of second gates, on the high concentration n-type impurity region, and on the high concentration p-type impurity region; And And removing the transition metal film that remains in an unreacted state without forming a silicide film during the heat treatment step.