JP2990118B2 - High-performance mos field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an MO having a small size.
The present invention relates to a method for manufacturing an S-type field effect transistor and a field effect transistor having a narrow gate electrode.

[0002]

BACKGROUND OF THE INVENTION Field effect transistors, commonly referred to as FETs or MOSFETs, are the most common devices among modern integrated circuit devices. FIG. 1 shows an example of a field-effect transistor structure. Field separation area 12
Are formed on the surface of the substrate 10, thereby defining active device regions, and laterally separating adjacent devices formed within and on the surface of the substrate 10. The gate oxide layer for the field effect transistor is
A gate electrode 16 of doped polysilicon is formed over the gate oxide layer 14.

An oxide spacer structure 18 is connected to a gate electrode 16.
Can be provided on both sides. Source / drain region 2
The inner edge of 0 defines a channel region at the substrate surface, and the source / drain regions extend from both sides of gate electrode 16 to field isolation region 12. Source/
The drain region 20 has a lightly doped drain (LDD) structure in which the relatively lightly doped inner portion of the source / drain region aligns with the edge of the gate electrode 16 and the relatively high source / drain region height. The doped portion is aligned with the oxide spacer structure 18.

Normally, the field effect transistor structure shown in FIG. 1 is manufactured as follows. First, a field isolation mask is formed on the surface of the substrate 10, and an opening is provided in the mask to expose the substrate in a region where a field isolation structure is to be formed. The field isolation structure is then formed using a local oxidation of silicon (LOCOS) method as shown, or using a shallow trench isolation method. The field isolation mask can then be stripped and various implants can be made into the active area of substrate 10 to adjust the doping distribution of the substrate in the active area.
Next, a gate oxide layer 14 is grown on the cleaned surface of the active area of the substrate 10. A low pressure chemical vapor deposition (LPCV)
Blanket deposition of polysilicon by method D).

[0005] This polysilicon layer is doped, for example by ion implantation, and then a gate electrode 16 is defined over the active area using photolithography. Source / drain regions 20 are formed by a two-stage implantation method. The first ion implantation is performed by masking the substrate using the gate electrode and the field isolation region, and performing the LD implantation.
A relatively lightly doped portion of the D source / drain region 20 is formed. A layer of CVD oxide is deposited over the gate electrode extending over the surface of the device, and then a spacer structure 18 is formed on both sides of the gate electrode 16 using an etch-back technique. The second implant is performed to a higher dose than the first implant to form a relatively heavily doped region aligned with the oxide spacer structure 18 and to complete the source / drain region 20.

[0006] Improving device densities and reducing the cost of manufacturing integrated circuits are closely related to reducing the size of devices in integrated circuits. The width of the gate electrode 16, as well as the size of other device structures, are determined by conventional lithographic methods. Generally, M shown in FIG.
The reduction in size of OS field effect transistors cannot be pushed beyond the resolution and alignment limits of the particular processing technology used in fabricating the device of FIG. Thus, the width of the gate electrode 16 is typically designed to have a width d that is equal to the design rules of the particular method used in manufacturing the gate electrode.

[0007] Further reducing the size of the gate electrode is desirable to reduce device size and improve the density of integrated circuits. Higher resolution lithography techniques can facilitate the formation of smaller gate electrodes, but the use of this technique is extremely costly and economically justified only in very high volume production. can do. In the case of relatively small production runs and specialty or low profit margin circuits, performing such costly processing is inefficient. Therefore, it is difficult to further reduce the size of the MOS field-effect transistor in FIG. 1 even if a lithography technique having a higher resolution is introduced.

Another disadvantage of the device shown in FIG. 1 and its method of manufacture is that the source / drain electrodes have a low enough resistance to provide good device performance. An important injection operation is required. The required high level of ion implantation raises various problems. For example, a high ion implantation dose renders the substrate on which the source / drain regions are to be formed amorphous. The recrystallization of the substrate in the source / drain regions is then performed by an annealing process, which may cause defects in the recrystallized material or cause excessive diffusion from the source / drain regions. There is. Excessive diffusion from the source / drain regions may cause the channel region under the gate electrode to be narrower than desired and degrade device performance.

[0009]

Accordingly, it is an object of the present invention to provide a method of manufacturing a field effect transistor device having a narrow gate electrode. It is another object of the present invention to provide a method for forming source / drain regions in a more controlled manner.

[0010]

SUMMARY OF THE INVENTION In a first aspect, the present invention provides a method of manufacturing a field effect transistor. In this method, a mask is formed on a substrate, exposing the surface of the substrate and having an opening having a wall. A spacer material layer is provided on the mask and in the opening of the mask. This layer of spacer material is etched to form spacers along the walls of the mask opening, and a gate insulator is formed on the surface of the substrate between the spacers. A gate electrode is formed between the spacers in contact with a gate insulator.

According to the present invention, a field effect transistor is manufactured by depositing a first polysilicon layer on a substrate on a second surface thereof and forming an opening having a wall in the first polysilicon layer. I do. An insulating material layer is provided over the first polysilicon layer, and the insulating material layer is then removed from over the first polysilicon layer and over the substrate in the opening.
A portion of the layer of insulating material is left within the opening on the opening wall. A gate insulator is formed over the substrate surface within the opening, and a second polysilicon layer is deposited over the gate insulator and over portions of the insulating material layer remaining within the opening. The second polysilicon layer is patterned to define an upper portion of the gate electrode in a lateral direction.

The present invention, in a first aspect, produces a field effect transistor having a gate electrode that is narrower than the design rules for the method used to fabricate the field effect transistor. The width of the mask opening can be designed to be equal to the design rules for the method used. A layer of insulating material is deposited over the mask and over the exposed portions of the substrate within the mask openings. An etch back process is performed on the insulating material layer to define a spacer structure on the substrate along both sides of the mask opening.

Next, a gate oxide layer is formed at the base of the mask opening to cover the substrate between the spacer structures. A polysilicon layer is deposited over the mask, over the surface of the spacer structure in the mask opening, and over the gate oxide layer at the bottom of the opening. The portions of the polysilicon layer are then removed using photolithography, leaving a polysilicon gate electrode extending into the mask opening. The effective length of the gate electrode formed by this method is reduced by the total width of the insulating spacer structure formed in the mask opening due to the design rule for the processing method.

In some examples of this aspect of the invention, the mask is at least partially formed from a lower doped polysilicon layer, some of which is above the substrate surface. This lower polysilicon layer preferably remains in place after electrode formation to form a wiring line in contact with the source / drain region for the narrow gate field effect transistor.

In another example of this aspect of the invention, the threshold adjustment after forming the spacer structure in the mask opening, but before depositing the patterned polysilicon layer on the gate electrode. Injection or anti-punch-through injection can be performed. Implanted ions through the mask opening narrowed by the spacer structure form threshold adjust or anti-punch through implants, which are self-aligned to the subsequently formed narrow gate electrode.

In another aspect, the present invention produces a MOS field effect transistor having source / drain regions at least partially raised above the surface of a crystalline substrate. For example, a source for a field effect transistor /
The drain region may be comprised of a doped silicon layer on the surface of the crystalline substrate, and only a plurality of source / drain regions may be formed in the substrate. Source in substrate /
Most preferably, the plurality of portions of the drain region are formed by diffusing impurities from the doped polysilicon layer into the source / drain regions in the substrate at a later stage of the field effect transistor fabrication.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects of the invention will now be described in detail with reference to specific examples of the invention shown in FIGS.

As shown in FIG. 2, the fabrication of a narrow gate field effect transistor begins on a silicon substrate 30 by forming a field isolation region 32 on the surface of the substrate. Field isolation area is conventional LOCO
It can be an S-oxide structure or a shallow trench isolation structure. An advantage of the present invention is that reduced size field effect transistors and reduced size circuits comprising field effect transistors can be formed using LOCOS technology, which is now relatively inexpensive and relatively reliable. . The above aspects of the invention are immediately applicable to devices incorporating shallow trench isolation structures or other isolation structures. Polysilicon layer 34
Is blanket deposited on the device to provide a separation structure 32
And coating the substrate surface in the active area.

The polysilicon layer 34 is a typical LPCV
Using D polysilicon deposition conditions, a thickness of 2000-4
It can be deposited up to 000 °. 30-50 Ke
By implanting arsenic ions with the energy of V,
1 × 10 silicon layer 34 ^Fifteen~ 2 × 10¹⁶/cm^TwoNo
Doping up to the dose amount. Injection energy injected
Ions remain in the polysilicon layer 34 and reach the substrate.
Not enough to prevent the substrate from being damaged by implantation.
Most preferably, it is smaller. Provided to the polysilicon layer 34
The amount of dopant supplied depends on the subsequent polysilicon layer 3
The impurity is changed to the polysilicon layer 34 by the annealing process of FIG.
From the substrate 30 into a narrow gate field effect transistor.
Highly doped source / drain regions for transistors
The amount is such that a portion is formed.

In the completed structure, the source / drain regions are preferably located partially in the polysilicon layer 34 and partially in the substrate 30. Since the part of the source / drain region in the substrate is formed by diffusion,
These portions are typically shallower than the source / drain regions formed in the substrate by ion implantation alone, as shown in FIG. Preferably, no activation anneal is performed at this stage of the process. Annealing for activating impurities in the narrow gate MOS field effect transistor is performed at a later stage of the process to limit the number of heat treatment steps and to limit the diffusion range of the dopant in the substrate. preferable.

Next, an opening 3 is formed on the polysilicon layer 34.
A mask having 8 is formed. The opening 38 exposes the polysilicon layer 34 over the area that will be etched away to form an opening in the layer 34. A gate electrode is formed later in the opening of the layer 34. The mask 36 shown in FIG. 2 can be formed from photoresist by conventional photolithographic techniques, or can be a hard mask depending on the particular processing method used. The openings 38 in the photoresist mask 36 preferably have a width d equal to the design rules of the particular processing method used.

As will be apparent from the following description, subsequent processing results in a gate electrode having an effective length shorter than the length d dictated by the design rules of the conventional processing method. Next, the anisotropic etching of the doped polysilicon layer 34 is performed through the opening 38 of the photoresist mask 36 by using, for example, a plasma etching agent obtained from HCl gas and HBr gas. An opening 35 is formed (FIG. 3).

Next, a layer of material 40, preferably a layer of insulating material, is deposited over the device. The material layer 40 is formed in the spacer structure in the opening 35 of the polysilicon layer 34 by an etch back method. Accordingly, the material layer 40 is preferably selectively etched with an etchant that does not rapidly etch either the polysilicon or the silicon substrate. Preferably, the deposited insulating material is a doped oxide, so that the impurities are diffused from the spacer structure into the substrate adjacent to the opening where the gate electrode is formed, thereby providing a source / drain region of the narrow gate field effect transistor. Can be formed.

To facilitate this process, the width of the spacer structure must be large enough to provide the appropriate width for the lightly doped portions of the LDD source / drain regions. Further, the width of the spacer structure that functions to reduce the width of the opening 35 of the polysilicon layer 34 determines the length of the gate electrode of the narrow gate field effect transistor. This is because the gate electrode is formed in the space separating the spacer structure in the opening 35. Therefore, the width of the spacer structure is
The setting needs to be made so that both the width of the lightly doped portion of the source / drain region and the length of the gate electrode for the narrow gate field effect transistor are determined. Since the spacer structure is formed by an etch-back method, the width of the spacer is essentially the same as the thickness of the deposition layer 40.

With respect to the dimensions of this device, it is expected that these dimensions may be different for other device structures, but a suitable thickness of material layer 40 is between 1000 and 200
0 °. Therefore, the spacer structure to be formed is 1000
It has a width of ~ 2000mm. The example shown in FIGS.
As it relates to an S-type field effect transistor, it is preferred to diffuse the donor dopant from the insulating spacer into the substrate to form a lightly doped portion of the narrow gate field effect transistor. Of course, if a PMOS type device or another LDD structure is formed, the material layer 40 is doped with an acceptor such as boron.

Alternatively, if it is not necessary to form a lightly doped portion, it is desirable to form material layer 40 from an undoped oxide. In such a case, it is desirable to make the undoped sidewall spacer thinner, or it is desirable to make at least the insulating portion of the sidewall spacer thinner. However, it is most desirable that the surface of the sidewall structure be a reliable insulator. In the case of the illustrated NMOS field effect transistor, the material used for the layer 40 is a phosphorus-doped oxide with a phosphorus content of 1 to 10%, for example lath (PSG) of phosphosilicate.

The material layer 40 has a substrate temperature of 300 to 450 ° C.
Can be deposited using a chemical vapor deposition (CVD) method. After deposition, material layer 40 is etched back to form insulating sidewall spacer structures 42 on both sides of opening 35 in polysilicon layer 34. Suitable etch-back process, the fluorine-based etchant, for example, consists of an anisotropic etching using a reactive ion etching with an etching agent obtained from CHF ₃ or C ₂ F _6. In a representative example, this process etches the material layer 40, but over the polysilicon lines 34 and the substrate 30.
Stop on. FIG. 4 shows the generated structure.

It is often desirable to perform one or more injections into the substrate below the field effect transistor to adjust the operating characteristics of the field effect transistor. For example, it may be desirable to perform one or both of a threshold adjustment implant and an anti-punchthrough implant for a narrow gate field effect transistor. Both the threshold adjustment implantation and the anti-punch through implantation can be performed by implanting ions 44 from the exposed surface of the substrate 30 between the insulating spacer structures 42. Both of these implantations consist of implanting boron ions 44 to different depths below the substrate surface, as shown in FIG.

The exact nature of the threshold adjustment implant will vary from device to device, but is typically a relatively shallow implant. The anti-anti-through implant is typically performed deep below the channel of the field effect transistor, for example, implanting boron ions to a dose of about 1 × 10 ¹² / cm ² at an energy of about 100 KeV. Consisting of Since the gate electrode is formed by depositing polysilicon in the openings defined by the insulating spacers 42, the implant performed as shown in FIG. 5 will self-align with the subsequently formed gate electrode. I do.

This is an important advantage, especially with respect to anti-punchthrough injection. The reason for this is that a more limited anti-punchthrough implant than before is much less likely to form a P / N junction with the source / drain regions than in a typical conventional field effect transistor structure. . As the P / N junction between the various channel implants and the source / drain regions decreases or disappears, the source / drain capacitance decreases and the operation of the narrow gate field effect transistor becomes faster.

After all the desired implants have been made, the device of FIG. 5 is heated to anneal the impurities implanted into the substrate by anti-punch-through implants. This heat treatment anneals and activates the impurities implanted in the polysilicon layer 34, and preferably removes the impurities from the polysilicon layer 3.
4 and from the doped oxide region 42 into the substrate. Diffusion of the preferred arsenic dopant from the polysilicon layer 34 results in a relatively shallow highly doped portion 4 of the source / drain region for the narrow gate field effect transistor.
8 form. Preferred doped oxide spacer structure 42
When the preferred phosphorus dopant is diffused from
A lightly doped region 50 of the drain region is formed.

An annealing step suitable for forming the structure of FIG. 5 involves the device being 800-900 minutes for 10-100 minutes.
Heating to ° C. Generally, the portions of the source / drain regions formed in the substrate are shallower than those formed by the conventional implantation method shown in FIG. Further, since the source / drain regions in the substrate are formed by diffusion, the level of damage to the lattice due to ion implantation to be annealed is significantly lower than typical levels in ion implanted source / drain regions. Finally, most of the highly doped source / drain regions are formed above the substrate and below the polysilicon layer 34, so that
The doping levels for the drain regions 48, 50 can be lower than in conventional field effect transistor structures, while providing suitable conductive source / drain regions.

Although this is a suitable processing step for the annealing step described above, this annealing step can be performed at a later stage of the processing to further reduce the number of heat treatment steps.
For example, this anneal step can be combined with a subsequent anneal step if the subsequent anneal step, such as used to make the gate electrode conductive, does not degrade device performance. However, in most cases, it is preferred that annealing be performed at this stage to ensure the formation of the highest quality gate oxide layer.

Next, a gate oxide layer 52 is grown on the exposed portions of substrate 30 between insulating spacer structures 42, with the device of FIG. 5 in an oxidizing atmosphere. Also,
At this stage, if the polysilicon surface of the polysilicon wiring line 34 is exposed, a polysilicon oxide layer 54 is grown on the polysilicon wiring line 34. The second polysilicon layer 56 is, for example, 2000
Blanket deposit over the device to a thickness of ５5000 °. The second polysilicon layer 56 is formed on a narrow gate electrode for a field effect transistor.

Preferably, the polysilicon wiring lines 34 are separated from the second polysilicon layer 56 by a reliable insulator such as a polysilicon oxide layer 54. The second polysilicon layer 56 is doped with arsenic by implanting arsenic with an energy of 30 to 50 KeV to a dose of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ² . The second polysilicon layer is patterned using conventional lithography to define an upper portion of the gate electrode 56 laterally. In this lithography process, the insulating layer 54 is
Preferably, it is chosen to act as an etch stop for the etch of No. 6. As a result, the first polysilicon layer 34 is protected.

Of course, the lateral extent of the lower portion of the gate electrode 56 is limited by the sidewall spacer structure 42.
The effective portion of the gate electrode 56 in the illustrated field effect transistor structure is the effective portion of the second polysilicon layer in contact with the gate oxide layer 52. Therefore, the effective length of the gate electrode 56 is determined by the degree of separation between the insulating spacer structures 42, and the degree of separation is smaller than the design rule d. An anneal is performed to activate the impurities in the gate electrode 56, and this process is continued until an integrated circuit with a narrow gate field effect transistor is completed, as in the conventional method.

The above description has been made with respect to a method of manufacturing an NMOS field effect transistor.
It can be easily applied to the manufacture of a field effect transistor. For example, the polysilicon interconnect lines 34 can be doped with boron and the insulating spacers 42 can be formed from boron-doped silicate glass to form P-type source / drain regions for PMOS field-effect transistors. it can. Both the NMOS type field effect transistor and the PMOS type field effect transistor are:
It can be manufactured without providing an LDD structure. In such a case, the insulating spacer structure 42 is undoped and is a silicon oxide based glass.

For field effect transistors that do not incorporate an LDD structure, it may be desirable to form either a thinner spacer structure or a spacer that is not completely insulating. That is, the portion of the spacer adjacent to the wall of the opening 35 of the first polysilicon layer 34 can be formed from doped polysilicon formed by blanket deposition and etching. Next, the insulating surface of the spacer is formed by coating the surface of the spacer facing the polysilicon oxide or silicon nitride of the gate electrode. Such a method is preferred for lowering the channel resistance when a channel with a higher resistance is not desired.

Changing the basic structure shown in FIGS. 2-6 may be desirable in certain applications. For example, it may be desirable to use another material with higher conductivity for the polysilicon wiring lines 34. Such a structure lowers the resistance of the connection to the source / drain region formed via the wiring line 34. Wiring line 34
If a higher level of conductivity is desired for
In the step shown in FIG. 2, a multilayer conductor can be used instead of the single-layer polysilicon wiring line. One suitable multilayer conductor comprises a lower doped polysilicon layer covered by a layer of a metal silicide, such as titanium silicide or tungsten silicide.

These metal silicides are formed by physical deposition directly on the surface of the lower polysilicon layer to avoid high temperature annealing steps. In other methods, the high temperature anneal step may involve polycide (poly)
cide) Used in forming metal silicides in structures. Alternatively, the multilayer structure can be comprised of a lower doped polysilicon layer covered with a refractory metal layer. In yet another example, a single layer of a refractory metal such as titanium can be used instead of the polysilicon layer.
The use of a titanium layer is compatible with the method described above. The reason is,
This is because the impurity atoms implanted in the titanium easily diffuse into the titanium and can be used to dope the titanium wiring lines into the source / drain regions.

In each of the above variations, the remainder of the process is continued as described above, by substituting the appropriate etchant necessary to etch the multilayer structure.
Further, in a typical example, it is necessary to form an insulator on a multilayer wiring line different from the polysilicon oxide used in the device of FIG. 6, and to insulate this wiring line from the gate electrode. In the manufacturing stage shown in FIG. 2, the CV deposited as a capping layer on the multilayer conductor
D-nitride is particularly suitable for this structure.

This is important when forming narrow gate field effect transistors because silicon nitride acts as an etch stop in the etch-back method used for the preferred oxide layer 40 in forming the spacer structure. This is because it is compatible with the etching process used in the above.
However, for most applications, the example of a wiring line in which doped polysilicon is the only conductor is preferred because of its ease of manufacture, predictability, and low stress levels in the inner layers.

FIG. 7 shows another modification of the embodiment shown in FIGS. In the example of FIG. 7, the wiring line 34 and the gate electrode 56 are formed by forming a silicon nitride layer 60 instead of the polysilicon oxide layer 54 provided in the above-described example.
To reduce the likelihood of a leak. Other aspects of the device of FIG. 7 are the same as those of the device shown in FIG.

The silicon nitride layer is deposited as a capping layer on the doped polysilicon layer 34 by the CVD method in the manufacturing process shown in FIG. After that,
In the step of etching the wiring line 34, an appropriate etching agent is introduced into the silicon nitride, and the process proceeds as described above.
If the polysilicon line 34 is capped with a silicon nitride layer, little or no oxide will grow on the line during the formation of the gate oxide layer 52.

The advantage of the method of manufacturing a field effect transistor described herein is that the source / drain region and the gate electrode are manufactured as described above, so that the wiring line 34 connected to the source / drain region is naturally formed. That is. This is a high density integrated circuit device,
It has many advantages. For example, if the illustrated narrow gate field effect transistor is used in a static random access memory device, the interconnect lines 34 in any standard cell structure may be interconnected between the transistor and other devices. The part can be easily formed.

Although the invention has been described with particular emphasis on certain preferred embodiments thereof, the invention is not limited to these particular embodiments. Those skilled in the art will appreciate that different embodiments and other variations of the present invention can be implemented to be consistent with the teachings of the present invention described above. Accordingly, the scope of the present invention is determined by the appended claims.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a conventional MOS field effect transistor structure.

FIG. 2 is a sectional view showing a first step in an example of the method for manufacturing a MOS field effect transistor according to the present invention.

FIG. 3 is a sectional view showing a step subsequent to FIG. 2;

FIG. 4 is a sectional view showing a step subsequent to FIG. 3;

FIG. 5 is a sectional view showing a step subsequent to FIG. 4;

FIG. 6 is a sectional view showing a step subsequent to that of FIG. 5;

FIG. 7 is a cross-sectional view showing a step corresponding to FIG. 6 in another example of the method for manufacturing a MOS field effect transistor according to the present invention.

[Explanation of symbols]

 10 Substrate 12 Field isolation region 14 Gate oxide layer 16 Gate electrode 18 Oxide spacer structure 20 Source / drain region 30 Silicon substrate 32 Field isolation region (isolation structure) 34 First polysilicon layer (polysilicon wiring line) 35 Opening 36 Photoresist mask 38 Opening 40 Material layer (insulating material layer, deposited layer, oxide layer) 42 Spacer structure (spacer, doped oxide region) 44 Ion (boron ion) 48 Highly doped portion of source / drain region 50 Source / drain Lightly doped part of the region 52 Gate oxide layer 54 Polysilicon oxide layer (insulating layer) 56 Second polysilicon layer (gate electrode) 60 Silicon nitride layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78

Claims (17)

(57) [Claims] A method of manufacturing a 1. A field effect transistor, on a substrate, the step of forming a mask having an opening having a surface exposed allowed and the wall of the substrate; on the mask and in said mask opening, doped Oxide
Step providing a spacer material layer consisting of: step by etching the spacer material layer to form a spacer along the walls of the mask openings; step of forming a gate insulator on the surface of the substrate between the spacers; and Forming a gate electrode by contacting the gate insulator between the spacers. Wherein it becomes the mask of a conductive material, The method of claim 1 wherein the finished said gate electrode, characterized in that there <br/> to extend over a portion of the mask. 3. The method of claim 2, further comprising the step of heating to diffuse impurities from the mask into the substrate and forming at least a portion of the source / drain region adjacent to a wall of the mask opening. Item 7. The method according to Item 1. . 4. The method of claim 1, wherein the mask comprises a conductive material, and wherein the method comprises: heating the mask to diffuse impurities from the mask into the substrate; The method of claim 1, further comprising the step of forming. 5. The method of claim 4, wherein said mask comprises polysilicon. 6. The heating step of diffusing impurities from the spacer into the substrate to form at least a portion of a source / drain region adjacent to a wall of the mask opening. The described method. 7. A method of manufacturing a field effect transistor, comprising: depositing a first polysilicon layer on a substrate; forming an opening having a wall in the first polysilicon layer; Insulation of doped oxide on silicon layer
Providing a layer of material ; removing the layer of insulating material on the surface of the first polysilicon layer and on the substrate in the opening, and removing a portion of the layer of insulating material within the opening on a wall of the opening. Forming a gate insulator on the substrate in the opening; and forming a second polysilicon layer on the gate insulator and on a portion of the insulating material layer remaining in the opening. Depositing; and patterning the second polysilicon layer to define an upper portion of a gate electrode. 8. The method of claim 1, further comprising: forming a first layer in the first polysilicon layer before forming the opening in the first polysilicon layer.
Claims: A step of implanting an impurity.
7. The method according to 7 . 9. 請 which comprises contacting the surface of said substrate adjacent said first polysilicon layer in the opening
The method of claim 8 . 10. The method of claim 1, further comprising: diffusing the first impurity from the first polysilicon layer into the substrate to form at least a portion of a source / drain region for the field effect transistor. Suppose
The method of claim 9 . 11. The method according to claim 11, wherein the insulating material layer is a doped oxide, and further comprising a diffusion step of diffusing the first impurity and diffusing a dopant from the doped oxide into the substrate adjacent to the opening wall. The method according to claim 10 , wherein: 12. The method of claim 11, wherein the insulating material layer The method according to claim 7, characterized in that a coating layer deposited on the exposed surface of the surface and the substrate of the first polysilicon layer. Wherein said removing step, the method according to claim 7, characterized in that an anisotropic etch-back process to form the spacers on the aperture wall. 14. The method of claim 12 , wherein said layer of insulating material is deposited over a layer of dielectric material covering a surface of said first polysilicon layer. 15. The insulating material layer is made of SiO ₂ ,
The method of claim 14, wherein said layer of dielectric material comprises silicon nitride. The upper of claim 16, wherein the gate electrode, on top of the aperture wall and said first polysilicon layer, The method of claim 7, wherein the extend laterally. 17. The method of claim 16 , wherein said gate electrode is separated from said first polysilicon layer by polysilicon oxide.