KR20000032293A - Method for manufacturing semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor memory device is provided to selectively form a silicide layer on a periphery region in one time of a photography process, and to form each gate spacer on a cell array region and the periphery region. CONSTITUTION: A gate(8) is formed on a substrate(2) having a cell array region and a periphery region. Next, an oxide layer(10) and an insulation layer(12) of a predetermined etching ratio are sequentially evaporated on whole area of the substrate(2) including the gate(8). Next, a mask pattern(14) is formed so that the periphery region is exposed. Next, a dry etching is performed to the insulation layer(12) in the periphery region while the oxide layer(10) is used as an etch stopping layer, so that a first gate spacer(12a) is formed. Next, a mask pattern(14) is removed. Next, the oxide layer(10) in the periphery region is removed, so that an upper area of the semiconductor substrate(2) is exposed at two sides of the gate spacer(12a). Next, a silicide layer(18) is formed on the exposed semiconductor substrate(2). Next, a dry etching is performed to the insulation layer(12) with an etching selection ratio to the silicide layer(18) in the cell array region while the oxide layer(10) is used as an etch stopping layer, so that a second gate spacer(12b) is formed.

Description

METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device in which a silicide layer is selectively formed in a peripheral circuit region.

As dynamic random access memory (DRAM) becomes increasingly integrated, the size of transistors is also getting smaller and smaller to sub-micron levels. Therefore, in the case of NMOS transistors, as the drain voltage increases, source and drain depletion regions meet each other, and a potential barrier between the source and the channel is also encountered. This lowers and punchthrough occurs. Then, the breakdown voltage of the source / drain of the transistor is reduced, the threshold voltage is reduced, and a typical short channel effect that causes an increase in swing occurs.

In order to improve such a short channel effect, a shallow junction should be formed by reducing ion implantation energy for forming a high concentration source / drain region. Then, the area occupancy of the source / drain regions becomes smaller than that of the normal voltage, and the depletion region of the source / drain regions is reduced to improve the short channel effect and to increase the punch-through voltage.

However, the shallow junction adversely affects ohmic contact and sheet resistance. That is, when the contact etching process is a problem that the ohmic contact is difficult due to the silicon consumption of the source / drain region, and the just etch process to minimize the silicon consumption of the source / drain region to form the ohmic contact There is a problem that a contact not open occurs.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and can selectively apply a silicidation process to a peripheral circuit region except for a cell array region of a semiconductor memory device, thereby providing ohmic contact for a shallow junction. It is an object of the present invention to provide a method of manufacturing a semiconductor memory device that can be formed.

1 to 4 are flowcharts sequentially showing processes of a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

2: semiconductor substrate 4: polysilicon film

5, 12, 20: silicon nitride film 6: HTO film

8 gate 9a, 9b low concentration source / drain region

10 buffer oxide film 14 photoresist pattern

12a, 12b: Gate spacer 16: High concentration source / drain region

18 silicide film 22 interlayer insulating film

(Configuration)

According to the present invention for achieving the above object, a method of manufacturing a semiconductor memory device, between the gate oxide film on a semiconductor substrate 2 having a cell array region and a peripheral region (periphery region) between; Forming a gate 8; Sequentially forming an oxide film (10) and an insulating film (12) having an etch selectivity with the oxide film (10) over the semiconductor substrate (2) including the gate (8); Forming a mask pattern 14 to expose the peripheral circuit region; Dry etching the insulating layer 12 of the peripheral circuit region to form a first gate spacer 12a, wherein the oxide layer 10 is formed as an etch stopping layer; Removing the mask pattern (14); Removing the oxide layer (10) in the peripheral circuit region to expose an upper portion of the semiconductor substrate (2) on both sides of the first gate spacer (12a); Forming a silicide layer (18) on the exposed semiconductor substrate (2); And dry etching the insulating layer 12 of the cell array region to form a second gate spacer 12b, wherein the oxide layer 10 is used as an etch stop layer, and an etch selectivity is applied to the silicide layer 18. Forming by performing under conditions having.

In a preferred embodiment of the method, the method may further include forming low concentration source / drain regions 9a and 9b in the semiconductor substrate 2 on both sides of the gate 8 before the oxide film 10 is formed. .

In a preferred embodiment of this method, a high concentration source / drain region 16 is formed in the semiconductor substrate 2 on both sides of the first gate spacer 12a before removing the oxide film 10 in the peripheral circuit region. It may further comprise a step.

(Action)

Referring to FIG. 3, in the novel semiconductor memory device manufacturing method according to the embodiment of the present invention, a silicide film may be selectively formed in a peripheral circuit region in one photo process, and further, in a cell array region and a peripheral circuit region. Each gate spacer can be formed.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4.

1 to 4 are flowcharts sequentially showing processes of a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention may first include a gate 8 on a semiconductor substrate 2 having a cell array region and a peripheral region. ) Is formed. The gate 8 is formed by sequentially depositing a polysilicon film 4, a silicon nitride film 5, and a high temperature oxide (HTO) film 6 on the semiconductor substrate 2, and then applying a gate mask. These films are then patterned to form. A gate oxide (not shown) is formed below the gate 8.

For example, low concentration source / drain regions 9a and 9b are formed in the semiconductor substrate 2 on both sides of the gate 8 using an impurity ion implantation process.

A buffer oxide 10 is deposited on the entire surface of the semiconductor substrate 2 including the gate 8. The buffer oxide film 10 is a middle temperature oxide (MTO) or HTO, and is deposited to a thickness of about 100 GPa. A silicon nitride film 12 for forming a gate spacer on the buffer oxide film 10 is deposited to a thickness of about 600 kPa.

In FIG. 2, a photoresist pattern 14 is formed on the silicon nitride film 12 to expose the peripheral circuit region. The silicon nitride layer 12 of the exposed peripheral circuit region is etched by a dry etching method such as an etch back process to form a gate spacer 12a on the buffer oxide layer 10 on both sidewalls of the gate 8. do. In this case, the buffer oxide layer 10 is used as an etch stop layer when the gate spacer 12a is formed. As the upper portion of the gate 8 is etched roundly in the gate spacer 12a forming process, the aspect ratio of the contact hole is reduced in the subsequent self-aligned contact forming process.

Similarly to forming the low concentration source / drain regions 16, for example, a high concentration source / drain region 16 is formed in the semiconductor substrate 2 on both sides of the gate spacer 12a using an impurity ion implantation process.

Referring to FIG. 3, after the photoresist pattern 14 is removed, the buffer oxide layer 10 is removed to expose silicon in the low concentration source / drain region 9a of the peripheral circuit region.

When the exposed silicon is silicided using a silicidation process well known in the art, a silicide film 18 is formed on the source / drain regions 9a of the peripheral circuit region.

Next, the silicon nitride film 12 of the cell array region is etched by a dry etching method to form a gate spacer 12b on the buffer oxide film 10 on both sidewalls of the gate 8. In this case, as in the formation of the gate spacer 12a in the peripheral circuit region, the buffer oxide layer 10 is used as an etch stop layer when the gate spacer 12b is formed.

As described above, the buffer oxide layer 10 serves as an etch stop layer when the gate spacers 12a and 12b are formed to prevent etching of silicon in the lower concentration source / drain regions 9a and 9b. In addition, the upper portion of the gate 8 is etched roundly during the gate spacer 12b forming process, thereby reducing the aspect ratio of the contact hole during the subsequent self-aligned contact forming process.

In this case, the dry etching process for forming the gate spacer 12b is performed under a condition where the etching selectivity of the silicon nitride film and the oxide film is sufficiently large to prevent the field oxide film of the peripheral circuit region from being consumed, and the buffer oxide film of the cell array region ( 10) remain almost the same thickness immediately after deposition. In general, the silicide layer 18 also has an etch selectivity with respect to the silicon nitride layer under such conditions, and may further increase the etch selectivity by adjusting process conditions.

In a subsequent process, as shown in FIG. 4, a silicon nitride film 20 used for forming a self-aligned contact on the entire surface of the semiconductor substrate 2, and an interlayer insulating film 22 for isolation between wirings are sequentially deposited. The silicon nitride film 20 is deposited to a thickness of about 100 GPa.

According to the present invention, the silicide layer may be selectively formed in the peripheral circuit region in one photo process, and the respective gate spacers may be formed in the cell array region and the peripheral circuit region.

Claims (5)

Forming a gate 8 on the semiconductor substrate 2 having a cell array region and a peripheral region, with a gate oxide film interposed therebetween; Sequentially forming an oxide film (10) and an insulating film (12) having an etch selectivity with the oxide film (10) over the semiconductor substrate (2) including the gate (8); Forming a mask pattern 14 to expose the peripheral circuit region; Dry etching the insulating layer 12 of the peripheral circuit region to form a first gate spacer 12a, wherein the oxide layer 10 is formed as an etch stopping layer; Removing the mask pattern (14); Removing the oxide layer (10) in the peripheral circuit region to expose an upper portion of the semiconductor substrate (2) on both sides of the first gate spacer (12a); Forming a silicide layer (18) on the exposed semiconductor substrate (2); And Dry etching the insulating layer 12 of the cell array region to form a second gate spacer 12b, wherein the oxide layer 10 is used as an etch stop layer, and has an etch selectivity with respect to the silicide layer 18. A method of manufacturing a semiconductor memory device comprising the step of forming under conditions. The method of claim 1, And the insulating film is a silicon nitride film. The method of claim 1, The dry etching process for forming the second gate spacer 12b is performed under conditions having a sufficiently high etching selectivity with respect to the oxide layer so that the field oxide layer of the peripheral circuit region is not etched. Manufacturing method. The method of claim 1, And forming a low concentration source / drain regions (9a, 9b) in the semiconductor substrate (2) on both sides of the gate (8) before forming the oxide film (10). The method of claim 1, Before removing the oxide film 10 in the peripheral circuit region, forming a high concentration source / drain region 16 in the semiconductor substrate 2 on both sides of the first gate spacer 12a. Manufacturing method.