JP2002368013A - Cmos thin-film transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control crystal orientation when an amorphous silicon film is crystallized by a laser annealing method. SOLUTION: A polycrystalline silicon film where laser annealing is made is subjected to ion implantation for forming a seed crystal having a specific orientation, and then solid-phase growth is made, thus controlling the crystal orientation. At this time, the depth of ion implantation is controlled, thus creating the regions of n and p channels in the same process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-temperature poly-Si
More particularly, the present invention relates to p-channel and n-channel CMOS thin film transistors and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, thin-film semiconductor elements used in flat panel displays include, for example, (1) the latest liquid crystal process technology in 1999 (published by Nikkei BP, 1999).
As described on page 4, PE-C
VD (Plasma Enhancement Chemical Vapor Depositio
After forming an amorphous silicon film using the n) method, a dehydrogenation annealing process was performed to reduce hydrogen contained in the amorphous silicon film, and then polycrystallized by an excimer laser annealing process. .

[0003] For example, (2) Japanese Patent Application Laid-Open No. H8-10254
According to the method for forming a crystalline semiconductor thin film described in Japanese Patent Application Publication No. 3 (1999), after a polycrystalline silicon film is formed, the polycrystalline silicon film is ion-implanted using a mask (11).
A microcrystalline silicon region having a crystal orientation of 0) is formed adjacent to a completely amorphous region, and the microcrystalline silicon region is used as a crystal growth nucleus to form an adjacent amorphous silicon region. By crystallizing the region, a polycrystalline silicon film having a large grain size is formed at a desired position.

Also, for example, (3) Japanese Patent Application Laid-Open No. H8-24200
According to the configuration of the thin film integrated circuit described in Japanese Patent Publication No.
By independently controlling the crystal grain size and the amounts of crystalline and amorphous components of the semiconductor thin film used for the channel transistor and the p-channel transistor, the performance of the n-channel transistor and the p-channel transistor can be independently controlled. I was

[0005]

In order to operate a semiconductor device at high speed, it is essential to have a high carrier mobility. When a semiconductor element is formed using polycrystalline silicon, one of the causes of inhibiting carrier mobility is as follows.
The existence of grain boundaries. Ideally, the crystal grain size is infinitely large like single-crystal silicon and there is no grain boundary. In order to reduce the influence of the crystal grain boundaries as much as possible, attempts are being made to reduce the number of crystal grain boundaries per unit area by forming polycrystalline silicon having larger crystal grains.

Another factor that determines the carrier mobility of polycrystalline silicon is the crystal orientation. If the crystal orientation is poor, an electrical barrier is generated between adjacent crystal grains, so that the transferability of carriers such as electrons and holes also decreases. Ideally, an n-channel field effect transistor using electrons as carriers is formed on a (100) or (111) crystal plane, and a p-channel field effect transistor using holes as carriers is formed on a (110) crystal plane. Thus, more efficient electron and hole carrier transfer properties can be obtained.

When the amorphous silicon film is crystallized by using the excimer laser annealing method as shown in the above-mentioned prior art (1), generally, annealing at a relatively low laser energy density is performed. Polycrystalline silicon with random orientation is formed, and the (111) crystal plane is preferentially oriented by increasing the laser energy density. In this technique, it has been impossible to independently control the orientation of the polycrystalline silicon crystal plane of each of the n-channel field-effect transistor and the p-channel field-effect transistor.

On the other hand, when the above-mentioned prior art (2) is used, (11)
0) Since all the crystal growth nuclei other than the crystal plane are completely destroyed, it is impossible to grow a polysilicon film other than the (110) crystal orientation on the substrate.

In the above-mentioned prior art (3), different carrier mobilities can be obtained by using different crystal grain sizes or different crystal / amorphous ratios in each of the n-channel transistor and p-channel transistor formation portions. I was However, with this method, it is possible to control the magnitude of the carrier mobility, but it is essentially impossible to obtain the optimum electrical characteristics by making the n-channel transistor and the p-channel transistor compatible.

An object of the present invention is to solve the above-mentioned problems,
For example, even when a polycrystalline silicon thin film is grown above a glass substrate containing SiO ₂ as a main component,
It is an object of the present invention to provide a CMOS transistor which controls the crystal orientation of each polycrystalline silicon thin film constituting an n-channel transistor and a p-channel transistor and has a large mobility.

[0011]

An object of the present invention is to provide a polycrystalline silicon thin film provided over a substrate, a channel region, an insulating film, a gate electrode, a source electrode,
A thin film transistor comprising a drain electrode, and a source electrode and a drain electrode connected to a source region and a drain region, respectively, which are provided on at least a part of the polycrystalline silicon thin film with the channel region interposed therebetween. The thin film transistor is composed of an n-channel type field effect thin film transistor using electrons as carriers and a p-channel type field effect thin film transistor using holes as carriers. The n-channel type field effect thin film transistor is substantially parallel to the surface of the substrate. At least a part of the crystal has a (111) preferential orientation in the direction, and the p-channel field-effect thin film transistor has at least a part of the (110) preferential crystal in a direction substantially parallel to the surface of the substrate. By forming a CMOS thin film transistor internally It is achieved.

Further, according to the present invention, in the polycrystalline silicon thin film, the X-ray diffraction intensity due to the (111) crystal lattice plane and (2)
20) The crystal orientation index A obtained from the X-ray diffraction intensity by the crystal lattice plane satisfies the range of 0.75 ≦ A ≦ 1.0 in the n-channel type field effect thin film transistor region, and in the p channel type field effect transistor region A ≦
This is achieved by satisfying the range of 0.3. However, the above-mentioned crystal orientation index A = {(111) diffraction intensity / 100} / ｛(111) diffraction intensity / 100 + (2
20) Defined by diffraction intensity / 55 °.

The polycrystalline silicon thin films in the n-channel type and p-channel type field effect thin film transistor regions have the above-mentioned crystal orientation characteristics, respectively, so that the average electron mobility of the n channel type field effect transistor semiconductor thin film is at least 200 cm. ² / VS
And the average hole mobility of the p-channel field effect transistor semiconductor thin film is at least 100 cm ^2.
/ V · S or more.

In the present invention, the above-mentioned polycrystalline silicon thin film in which the crystal orientation of each of the n-channel transistor and the p-channel transistor is controlled is formed by a first step of forming an amorphous silicon thin film above a substrate. A second step of irradiating the amorphous silicon thin film with a laser beam to polycrystallize at least a part of the amorphous silicon thin film; and forming a thin film of an arbitrary thickness on the polycrystalline silicon film. A fourth step of ion-implanting specific atoms into the polycrystalline silicon thin film through the thin film formed in the third step, and removing the thin film formed in the third step. And a sixth step of recrystallizing the polycrystalline silicon thin film after ion implantation by heat treatment. As the thin film used as a mask during the ion implantation in the third step, for example, a silicon oxide film can be used.

Further, in the present invention, in order to independently control the crystal orientation of the polycrystalline silicon thin film of each of the n-channel transistor and the p-channel transistor, the thin film formed in the third step is etched by using an etching method. This is achieved by selectively forming a thick film region and a thin film region, and using this difference in film thickness to change the ion implantation depth during ion implantation.

In the fourth step, since the ion implantation depth can be changed by controlling the ion implantation energy, the region of each of the n-channel transistor and the p-channel transistor can be changed. It is possible to independently control the crystal orientation of the polycrystalline silicon thin film. The ion implantation element in the fourth step is achieved by using, for example, a Si element.

Further, the recrystallization treatment of the semiconductor thin film in the sixth step is performed by a rapid thermal annealing method using a lamp, a heat treatment method in a furnace at an atmosphere temperature of 450 ° C. or less, or a laser beam. This is realized by using a heat treatment method.

[0018]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a process schematic diagram for explaining a process of forming a polycrystalline silicon thin film according to one embodiment. First, as shown in FIG. 1A, as one example, Corning 7059 glass is used as a substrate 101.
Well-known plasma CVD on this glass substrate 101
A silicon nitride film 102 (with a thickness of 50 nm) is formed by using the method. Then, a silicon oxide film 103 (thickness: 100 nm) is formed thereon by the same plasma CVD method. Further, an amorphous silicon film (film thickness 50 nm) is formed 104 by using a plasma CVD method. The glass substrate 101 may be a transparent substrate such as quartz or PET (polyethylene terephthalate). Alternatively, the amorphous silicon film 104 may be formed by an LPCVD method (a low-pressure chemical vapor method), a sputtering method, an evaporation method, or the like.

Next, the thin film on the substrate is annealed for 30 minutes in a furnace at 450 ° C., for example, so that hydrogen contained in the amorphous silicon film 104 is eliminated. In the present embodiment, the furnace was set in a nitrogen atmosphere. Thereafter, the amorphous silicon film 104 on which the above-described dehydrogenation treatment has been performed is, for example, XeCl laser (wavelength 308 n).
m) was used for laser crystallization. In this embodiment, the energy density of the laser beam is 300 to 500 mJ / cm.
^{And 2} .

In this embodiment, the amorphous silicon film 104 is used.
By irradiating the same portion with laser light a plurality of times, the amorphous silicon film 104 is crystallized. Here, as a method of irradiating a plurality of times, the steps of irradiating the laser light on the amorphous silicon film 104 at predetermined intervals after irradiating the laser light for the first time and repeating the irradiation of the laser light again are repeated. I did it. By repeating laser light irradiation and scanning at predetermined intervals in this manner, the same portion of the amorphous silicon film 104 is substantially irradiated with laser light a plurality of times.

An X-ray diffraction measurement was performed on the polycrystalline silicon crystal thin film thus manufactured, and the crystal orientation was evaluated. The results will be described below. FIG. 2 shows an example in which the amorphous silicon film 104 has a thickness of 300 mJ / cm 2.
5 shows the results of X-ray diffraction measurement of a polycrystalline silicon thin film immediately after excimer laser irradiation at an energy density of 30 times. As shown in this figure, the (111) diffraction line indicating the (111) crystal plane and the (110) crystal plane indicate the (22).
0) Diffraction lines were clearly observed.

Generally, when the polycrystalline silicon film is completely randomly oriented, the (111) diffraction intensity: (220) diffraction intensity is 100: 55. Therefore, as one index for evaluating the crystal orientation of the polycrystalline silicon film, the following orientation index A is defined using the (111) diffraction intensity and the (220) diffraction intensity. A = {(111) diffraction intensity / 100} / ｛(111) diffraction intensity / 100 + (2
20) Diffraction intensity / 55 ° Using the above definition expression, the closer the orientation index is to 1, the more the (111) preferred orientation is indicated, and the closer the orientation index is to 0, the more the (110) orientation. This indicates that the orientation is preferred. When the orientation index is 0.5, it indicates that the orientation is random orientation.

FIG. 3 shows the relationship between the laser energy density and the orientation index. Since the orientation index when the laser energy density is low is about 0.5, it can be seen that a specific crystal orientation is not oriented but what is called random orientation. Also, it can be seen that the orientation index approaches 1 as the laser energy density increases, and the (111) preferential orientation occurs.

Next, as shown in FIG.
An insulating film 105 made of SiO ₂ is formed on the polycrystalline silicon film 104 by using the VD method. This insulating film 105 serves as a mask for subsequent Si ion implantation. Therefore, the depth of the ion implantation can be changed depending on the thickness of the insulating film 105. In order to verify how the ion implantation depth at this time affects the crystallinity of the polycrystalline silicon film, In this embodiment, 10n
insulating films 105 having different thicknesses of m, 50 nm, and 150 nm
Was formed. As the thickness of the insulating film is smaller, the implanted ions reach deeper.

Next, as shown in FIG.
5, ions were implanted into the polycrystalline silicon film 104 described above. In the present embodiment, Si atoms were used as ions for implantation. Then, as shown in FIG. 1D, the insulating film 105 used for ion implantation using a hydrofluoric acid solution is used.
Is completely removed. Finally, recovery annealing by RTA (rapid thermal annealing) is performed to recover damage due to ion implantation existing in the silicon layer and to recrystallize the silicon layer.
Was formed. The activation annealing of the damaged layer is performed by RTA.
Instead, an annealing process using a furnace body is also possible.

FIG. 4 shows that the thickness of the insulating film 105 is 10 n.
m, 50 nm, and 150 nm.
The relationship between the crystal orientation of the polycrystalline silicon film 106 and the laser energy density is shown. The crystal orientation is shown using the orientation index A described above. In this example, the acceleration energy at the time of Si ion implantation was set to 50 keV.

It can be seen that the orientation index when the thickness of the SiO ₂ film as the insulating film 105 is large (150 nm) is hardly changed as compared with the orientation index before ion implantation (see FIG. 3). That is, the silicon film having the (111) orientation before the ion implantation has the (111) orientation after the ion implantation, and the silicon film having the random orientation has the random orientation even after the ion implantation. It means there is.

On the other hand, when the thickness of the insulating film 105 (SiO ₂ film) is 50 nm, the relationship between the laser energy density and the orientation index A greatly changes before and after ion implantation. That is, if ion implantation is not performed, the laser energy density (for example, 450 m
J / cm ² ), or a laser energy density (for example, 350 mJ / c) showing random orientation.
Even with m ² ), the crystal orientation is broken by ion implantation, and the (110) orientation becomes remarkable. And the insulating film 105
When the ion implantation is performed with the thickness of the (SiO ₂ film) being 10 nm, regardless of the orientation index A of the polycrystalline silicon before the ion implantation and the magnitude of the laser energy density, the specific crystal orientation is obtained. It was found that the film had a random orientation without a surface.

As shown in FIG. 4, the change in the relationship between the orientation index A and the laser energy density depending on the presence or absence of ion implantation can be interpreted as follows. That is,
When the insulating film 105 (SiO ₂ film) is thick (for example, in the case of 150 nm described in this embodiment), the implanted ions pass through the insulating film 105 and are located below the SiO ₂ film because the SiO ₂ film is too thick. It hardly reaches the polycrystalline silicon film 104. Therefore, even after the recovery annealing, the orientation of the polycrystalline silicon before the ion implantation is preserved as it is, without substantially changing before and after the crystal orientation ion implantation.

On the other hand, when the insulating film 105 (SiO ₂ film) is extremely thin (for example, when the thickness is 10 nm shown in this embodiment), the implanted ions sufficiently reach the polycrystalline silicon film 104. As a result, the polycrystalline silicon film 1 before ion implantation is formed.
This completely destroys the crystal structure of No. 04 and completely changes it to amorphous silicon. Therefore, it is considered that even after subsequent recrystallization annealing, the crystal grows in a random orientation without growing in a specific crystal orientation.

When the insulating film 105 (SiO ₂ film) is neither extremely thick nor thin, for example, 50 nm, a so-called channeling phenomenon observed by ion implantation of single crystal silicon. Is presumed to have occurred. The channeling phenomenon is a phenomenon in which implanted ions pass through interstitial spaces without colliding with atoms constituting a crystal. Due to the geometrical arrangement of the atoms constituting the crystal lattice, channeling is most likely to occur in the case of single crystal silicon when ion implantation is performed perpendicular to the (110) plane. It is considered that a similar phenomenon can occur in the ion implantation of the polycrystalline silicon film 104. In the case of a crystal lattice composed of crystal particles having a (110) crystal orientation among the crystal particles constituting the polycrystalline silicon film 104, In addition, the implanted ions incident from the vertical direction of the thin film are least damaged.

On the other hand, the probability that the implanted ions collide with a crystal lattice composed of crystal grains having other orientations including the (111) crystal orientation is higher, and as a result, the damage to the crystal lattice is increased. Guessed. Therefore, the polycrystalline silicon film 104 after the ion implantation is (1)
10) The crystal grains having the orientation preferentially remain, and the crystal grains having the (110) orientation preferentially remain.
It is considered that the recrystallization of No. 4 facilitates the (110) preferential orientation of the newly generated polycrystalline silicon film 106.

As described above, the polycrystalline silicon film 10
After an insulating film 105 having an arbitrary thickness is provided on the substrate 4, Si ions are implanted through the insulating film 105 and then recrystallized to obtain a polycrystal having a (111) orientation or a (110) orientation. The silicon film 106 can be formed. In this embodiment, the depth of the Si ion implantation is controlled by changing the thickness of the insulating film 105, but the same effect can be obtained by controlling the ion implantation energy. That is, when ion implantation is performed deeper, ion implantation may be performed using Si ions having high energy.

Next, a CMOS type thin film transistor according to another embodiment will be described. FIG. 5 is a cross-sectional view showing an outline of a thin film transistor, in which a first underlayer 202, a second underlayer 203, an n-channel semiconductor silicon layer 204, and a p-channel semiconductor silicon layer 2 on a glass substrate 201 are shown.
06, an insulating layer 207, an electrode layer 208, an insulating layer 209, a contact hole 210, and an electrode 211.

FIG. 6 illustrates in detail the steps of the thin film transistor in this embodiment. First, FIG.
As shown in FIG. 1, as one example, a silicon nitride film 202 (50 nm thick) as a first underlayer is formed on a Corning 7059 glass substrate 201 by using a well-known plasma CVD method.
m). And on top of this, the plasma CV
A silicon oxide film 203 (thickness: 100 nm) as a second base layer is formed by Method D. Further, an amorphous silicon film 204 (50 nm thick) is formed by a plasma CVD method. The glass substrate is not limited to the above-mentioned corning glass, and may be a transparent substrate such as quartz or PET (polyethylene terephthalate). Alternatively, the amorphous silicon film 204 may be formed by an LPCVD method (a low-pressure chemical vapor method), a sputtering method, an evaporation method, or the like.

Next, the glass substrate 201 on which the amorphous silicon film 204 has been formed is annealed in a furnace at 450 ° C. for 30 minutes to dehydrogenate the amorphous silicon film 204. At this time, the atmosphere in the furnace body was a nitrogen atmosphere. After that, the above-mentioned amorphous silicon film 204 is
The crystallization process was performed using 1 laser (wavelength 308 nm, pulse width 20 nsec). The type of laser light is a KrF laser (wavelength: 248 nm) which is an excimer laser, YAG
A laser, an Ar laser, or the like may be used. The crystallization conditions were such that the energy density of the laser beam was 450 mJ /
cm ² and 30 times of irradiation. The laser irradiation was performed in a nitrogen atmosphere.

In this embodiment, the same portion of the amorphous silicon film 204 is irradiated with laser light a plurality of times,
The crystallization of the amorphous silicon film 204 is performed. Here, as a method of irradiating a plurality of times, the steps of irradiating the laser light on the amorphous silicon film 204 at predetermined intervals after irradiating the first laser light, and irradiating the laser light again are repeated. I did it. By repeating the laser light irradiation and the scan at a predetermined interval in this manner, the same portion of the amorphous silicon film 204 is substantially irradiated with the laser light a plurality of times.

Next, as shown in FIG. 6B, an insulating film 205 (film thickness: 150 nm) made of SiO _{2 is} formed by a plasma CVD method to form an amorphous silicon film 204 having been subjected to the above-mentioned crystallization process. (Hereinafter referred to as a polycrystalline silicon film 204)
Form on top. This insulating film 205 serves as a mask for subsequent Si ion implantation. Then, the insulating film 205 is formed in a predetermined pattern by using a well-known photolithography method. Here, as shown in the figure, in a region where the n-channel transistor and the p-channel transistor are formed, the insulating film 2 is formed.
The film thickness of No. 05 was changed. That is, the film thickness in the n-channel transistor region was 150 nm, which is the film thickness formed first, and the film thickness in the p-channel transistor region was 50 nm.

Next, as shown in FIG. 6C, ions are implanted into the polycrystalline silicon film 204 through the patterned insulating film 205 to form a silicon layer 220 for an n-channel transistor and a p-channel A silicon layer 230 for a type transistor is formed. After that, the insulating film 205 is completely removed using a hydrofluoric acid solution. Then, recovery annealing using an RTA (rapid thermal annealing) method is performed in order to recover damage at the time of ion implantation existing in the n-channel silicon layer 220 and the p-channel silicon layer 230 and to perform recrystallization. Note that the activation annealing of the damaged region can be performed by an annealing process using a furnace body.

Next, as shown in FIG. 6D, a predetermined pattern is formed on the silicon films 220 and 230 by using the photolithography method. Thereafter, the insulating film 20 made of SiO ₂ is successively formed using, for example, a plasma CVD method.
7 are patterned polycrystalline silicon films 221 and 2
31 is formed. In this embodiment, Si
The thickness of the O ₂ insulating film 207 was set to 100 nm. Further, an electrode layer 208 serving as a gate electrode is formed by a well-known sputtering method. Here, TiW (thickness: 200 nm) was used as the electrode layer 208. Subsequently, the electrode layer 208 is processed into a predetermined pattern using a photolithography method, and then ion implantation is performed on the polycrystalline silicon films 221 and 231 using the electrode layer 208 as a mask to form an n-channel type channel region. 221a, n
Channel type source region 221b, n channel type drain region 221b, and p channel type channel region 231
a, n-channel type source region 231b and n-channel type drain region 231b are formed. In this embodiment, n
When a channel type semiconductor is formed, phosphorus is implanted as an n-channel type impurity, and when a p-channel type semiconductor is formed, boron is implanted as a p-channel type impurity.

Further, the polysilicon layers 221 and 231
In order to recover the damage caused by ion implantation inherent in
Activation annealing is performed by RTA (rapid thermal annealing). The activation annealing of the damaged layer can be performed by an annealing process using a furnace body.

Thereafter, the Si is again formed by the plasma CVD method.
An O ₂ insulating layer 209 (with a thickness of 500 nm) is formed so as to cover the electrode layer 208. Then, a contact hole 210 for securing electrical connection with the source region 221b, 231b and the drain region 221b, 231b is formed at a predetermined position of the SiO ₂ insulating layer 209, and the inside of the contact hole 210 is buried. Thus, the source regions 221b and 231b and the drain region 221
b, 231b (material TiW /
(A multilayer film of Al).

Finally, an annealing process is performed in hydrogen at 400 ° C. for 60 minutes to complete the thin film transistor using the polycrystalline silicon film shown in FIG.

Here, the results of evaluating the characteristics of the n-channel and p-channel transistors manufactured above are shown below. FIGS. 7 and 8 show the relationship between the field-effect mobility and the crystal orientation index of an n-channel transistor and a p-channel transistor, respectively. As is clear from this figure, the field-effect mobility and the crystal orientation index show a very strong correlation. In particular, in the case of an n-channel transistor, a transistor having a channel region made of a polycrystalline silicon film with a (111) crystal orientation is used. When the orientation index A is set to 0.75 or more, characteristics of a transistor having a field-effect mobility of 200 cm 2 / Vs or more can be realized.

Similarly, the p-channel transistor shown in FIG. 8 has a very strong correlation between the field-effect mobility and the crystal orientation index, and has a channel region made of a (110) crystal-oriented polycrystalline silicon film. It is clear that a transistor has been formed. By setting the orientation index A of the polycrystalline silicon layer to 0.3 or less, a p-channel transistor having a field-effect mobility of 100 cm2 / Vs or more can be realized.

As described above, according to the series of processes described with reference to FIG. 6, it is possible to independently control the crystal orientation of the n-channel region and the p-channel region and to form them simultaneously. Then, as a result of controlling the crystal orientation in each region, a high mobility of 200 cm ² / V · s or more is obtained in the n-channel transistor and 100 cm ² / V in the p-channel transistor.
・ High mobility of s or more can be obtained at the same time. Therefore, the structure and process of the transistor described above can be applied to, for example, a driving transistor and a driver circuit in an active matrix liquid crystal display device.

[0047]

According to the present invention, the crystal orientations of the polycrystalline silicon films constituting the n-channel region and the p-channel region can be controlled independently of each other, and can be formed simultaneously in a series of processes. I can do it.

[Brief description of the drawings]

FIG. 1 is a view for explaining a step of forming a polycrystalline silicon thin film.

FIG. 2 shows a result of X-ray diffraction measurement of a typical polycrystalline silicon film.

FIG. 3 is a diagram showing a relationship between crystallization conditions (irradiation energy density) by laser light and crystal orientation of a polycrystalline silicon film.

FIG. 4 is a view for explaining the crystal orientation of a polycrystalline silicon film after ion implantation.

FIG. 5 is a sectional structural view of a CMOS thin film transistor using a polycrystalline silicon film.

FIG. 6 is a diagram illustrating a process of forming a CMOS thin film transistor.

FIG. 7 is a diagram for explaining the relationship between the crystal orientation of the n-channel region and the field-effect mobility.

FIG. 8 is a diagram for explaining the relationship between the crystal orientation of the p-channel region and the field-effect mobility.

[Explanation of symbols]

Reference numeral 101: substrate, 102: first underlayer, 103: second underlayer, 104: amorphous silicon layer, 105: insulating film layer, 1
06 ... polycrystalline silicon layer, 201 ... substrate, 202 ... first
Underlayer, 203: second underlayer, 204: amorphous silicon layer, 205: insulating film layer, 207: insulating layer, 208: electrode layer, 209: insulating layer, 210: contact hole, 21
1: electrodes, 220, 230 ... silicon layers, 221, 23
1 polycrystalline silicon layer, 221a, 231a channel region, 221b, 231b source, drain

Continuing from the front page (72) Inventor Yukio Takasaki 3300 Hayano, Mobara-shi, Chiba Prefecture, Hitachi, Ltd.Display Group (72) Inventor Jun Goto 3300, Hayano, Mobara-shi, Chiba Prefecture, Hitachi, Ltd. Person Katsutoshi Saito 3300 Hayano, Mobara-shi, Chiba Prefecture F-term in Display Group, Hitachi, Ltd. (reference) CC02 DD01 DD02 DD03 DD13 DD14 DD17 EE06 EE44 FF02 FF30 GG02 GG13 GG17 GG25 GG42 GG43 GG45 GG47 HJ01 HJ13 HJ23 HL03 HL06 HL11 NN04 NN23 NN35 NN78 PP01 PP02 PP03 PP04 PP05 PP13 PP29 PP32 Q

Claims (14)

[Claims] 1. A semiconductor device comprising: a semiconductor thin film laminated on a substrate; a channel region; an insulating film; a gate electrode; a source electrode; and a drain electrode, wherein the source electrode and the drain electrode are A thin film transistor connected to a source region and a drain region provided at least in part of the semiconductor thin film with the channel region interposed therebetween, wherein the thin film transistor is an n-channel type field effect thin film transistor using electrons as carriers. And a p-channel field-effect thin film transistor having holes as carriers, wherein the n-channel field-effect thin film transistor has, at least in part, a crystal that is (111) preferentially oriented in a direction substantially parallel to the surface of the substrate. And the p-channel field effect thin film transistor is substantially parallel to the surface of the substrate. CMOS thin film transistor, wherein (110) to become by endogenous to at least a portion thereof preferentially oriented crystal to the direction. 2. The CMOS thin film transistor according to claim 1, wherein said semiconductor thin film is a polycrystalline silicon thin film. 3. The polycrystalline silicon thin film according to claim 1, wherein (11)
1) The crystal orientation index A obtained from the X-ray diffraction intensity by the crystal lattice plane and the X-ray diffraction intensity by the (220) crystal lattice plane is:
3. The range of 0.75 ≦ A ≦ 1.0 in the n-channel field-effect transistor region and the range of A ≦ 0.3 in the p-channel field-effect transistor region. 4. CMOS described in
Type thin film transistor. Where A = {(111) diffraction intensity / 100} /｝ (111) diffraction intensity / 100 + (22
0) Diffraction intensity / 55 ° 4. An n-channel type field effect transistor semiconductor thin film having an average electron mobility of at least 200 cm ² /
V · S or more, and the average hole mobility of the p-channel field effect transistor semiconductor thin film is at least 100.
^2. The CMOS thin film transistor according to claim 1, wherein the thickness is not less than cm ² / V · S. 5. A first step of forming an amorphous silicon thin film above a substrate, and irradiating the amorphous silicon thin film with a laser beam to crystallize at least a part of the amorphous silicon thin film. A second step of forming a silicon nitride thin film, a third step of forming a thin film of an arbitrary thickness on the silicon thin film, and passing the specific atoms through the thin film formed in the third step. A fourth step of implanting ions into the crystallized silicon thin film, a fifth step of removing the thin film formed in the third step, and a step of recrystallizing the crystallized silicon thin film after the ion implantation by heat treatment. 6. A method for manufacturing a CMOS thin film transistor, comprising: 6. The method according to claim 5, wherein the thin film formed in the third step is a silicon oxide film. 7. The CMOS according to claim 5, wherein the depth of the ion implantation performed in the fourth step is controlled by changing the thickness of the thin film formed in the third step. Method of manufacturing a thin film transistor. 8. A first region having a large thickness and a second region having a small thickness are selectively formed on the thin film formed in the third step by using an etching method. 6. The crystal orientation of the crystallized silicon film located below the second region and the crystal orientation of the polycrystalline silicon film located below the second region are different from each other.
3. The method for manufacturing a CMOS thin film transistor according to item 1. 9. The method according to claim 4, wherein the ion implantation energy is changed in the fourth step to change the depth of ions implanted into the crystallized silicon film and to control the crystal orientation of the crystallized silicon film. 6. The method for manufacturing a CMOS thin film transistor according to claim 5, wherein 10. A first region having a large implantation energy and a second region having a small implantation energy in said crystallized silicon film by controlling ion energy to be implanted into said crystallized silicon film in said fourth step. Are selectively formed, and the crystal orientation of the crystallized silicon film located below the first region and the crystal orientation of the crystallized silicon film located below the second region are different. 6. The CMOS according to claim 5, wherein the CMOSs are different from each other.
Method of manufacturing a thin film transistor. 11. The method according to claim 5, wherein in the fourth step, Si is used as an ion implantation element. 12. The method according to claim 5, wherein, in the sixth step, the crystallized silicon film is recrystallized by using a rapid thermal annealing method. 13. The method according to claim 6, wherein in the sixth step, 450
6. The method according to claim 5, wherein the crystallized silicon film is recrystallized in an atmosphere at a temperature equal to or lower than C. 14. The method according to claim 5, wherein, in the sixth step, the crystallized silicon film is recrystallized using a laser beam.