JP2852855B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an insulating substrate made of glass or the like,
Alternatively, a semiconductor device having a non-single-crystal silicon film provided over an insulating film formed over various substrates, for example, a thin film transistor (TFT) or a thin film diode (TFD),
Also, the present invention relates to a method of manufacturing a thin film integrated circuit using the same, particularly a thin film integrated circuit for an active liquid crystal display device (liquid crystal display).

[0002]

2. Description of the Related Art In recent years, semiconductor devices having TFTs on an insulating substrate such as glass, for example, active type liquid crystal display devices and image sensors using TFTs for driving pixels have been developed.

[0003] Thin film silicon semiconductors are generally used for TFTs used in these devices. Thin-film silicon semiconductors are roughly classified into two types: those made of an amorphous silicon semiconductor (a-Si) and those made of a crystalline silicon semiconductor. Amorphous silicon semiconductors are most commonly used because they have a low manufacturing temperature, can be manufactured relatively easily by a gas phase method, and have high mass productivity. Since it is inferior to a silicon semiconductor having
In order to obtain higher-speed characteristics in the future, it has been strongly required to establish a method for manufacturing a TFT made of a crystalline silicon semiconductor. In addition, as a silicon semiconductor having crystallinity, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystal component, semi-amorphous silicon having an intermediate state between crystalline and amorphous, and the like are known. .

A method for obtaining a silicon semiconductor in the form of a thin film having crystallinity is as follows: (1) A film having crystallinity is directly formed at the time of film formation. (2) An amorphous semiconductor film is formed, and crystallinity is imparted by the energy of laser light. (3) An amorphous semiconductor film is formed in advance, and crystallinity is imparted by applying thermal energy (annealing) for a long time. The method is known.

However, using either method,
Crystalline silicon having good characteristics comparable to single crystal silicon has not been obtained. This is because a grain boundary was generated inside the coating film by any of the methods, and there was no means for controlling the grain boundary.

[0006]

SUMMARY OF THE INVENTION The present invention provides means for solving the above problems. More specifically, an object of the present invention is to control crystal grains generated from amorphous silicon, and to make a specific portion of the crystal controlled as such a channel forming region of a TFT or TFD.

[Means for Solving the Problems]

According to the present invention, a crystal nucleus is selectively generated by selectively implanting silicon ions into an amorphous silicon film and thereafter heating at 500 to 700 ° C., preferably 550 to 600 ° C. The crystal is grown by thermal annealing for a time. After crystallizing a part or all of the coating in this way, irradiate with strong light (lamp annealing step),
Further, it promotes crystallinity and at the same time densifies the film quality. Then, a channel formation region of a TFT is formed using a crystal region of a region in which silicon ions have been implanted in the thus obtained crystalline silicon film.

[0008]

According to the present invention, the density of crystal nuclei in the ion-implanted region is significantly reduced by the selective ion implantation of silicon. On the other hand, the density of the crystal nuclei in the region where the ions have not been implanted is the same as the conventional one. Therefore, in the thermal annealing step after the ion implantation, nuclei are generated from the regions where the ions have not been implanted, and the crystals grow laterally from the nuclei as starting points into the regions where the ions are implanted. The dose of the ion implantation depends on the thickness of the film, but is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² , preferably 5 × 10 ¹⁶ cm ⁻² .
× 10 ^{14 to} 5 × 10 ¹⁵ cm ^-2 is good. Also, it is preferable to select the acceleration energy so that the most is implanted into the bottom surface of the film.

In the region where the crystal is grown in the lateral direction, the film and the interface between the film and the underlayer are damaged by silicon ion implantation.
It is difficult to obtain completely good crystals by annealing at 500 to 700 ° C., and contains many defects inside. In order to improve such defects, annealing at a higher temperature is necessary. In addition, it is necessary to perform annealing so as not to affect the substrate. For such a purpose, lamp annealing is required.

In the lamp annealing step of the present invention, specifically, light ranging from near-infrared light to visible light, preferably light having a wavelength of 4 μm to 0.5 μm (for example, 1.3 μm
Irradiation of infrared light having a peak at a relatively short time of about 10 to 1000 seconds has a meaning of heating the silicon film to promote crystallinity. It is desirable that the wavelength of light used be absorbed by the silicon film and not substantially absorbed by the glass substrate.

Further, in such a heat treatment, the silicon film often peels due to a difference in thermal expansion coefficient between the silicon film and the substrate and a difference in temperature between the surface of the silicon film and the interface between the silicon film and the substrate. is there. In particular, this is remarkable when the area of the film is large over the entire surface of the substrate. Therefore, by dividing the film into a sufficiently small area, and by making the distance between the films sufficiently large so as not to absorb extra heat,
Peeling of the film can be prevented. Further, since the entire surface of the substrate is not heated through the silicon film, thermal contraction of the substrate can be minimized.

In particular, a crystallized intrinsic or substantially intrinsic (phosphorus or boron of 10 ¹⁷ cm ⁻³ or less) silicon film absorbs visible and infrared light having a wavelength of 0.5 to 4 μm, and has a thickness of 10 μm.
Far-infrared light having a wavelength of m or more is absorbed by the glass substrate and heated, but when the wavelength of 4 μm or less is in most cases, the glass is hardly heated. That is, a wavelength of 0.5 to 4 μm is effective for further crystallizing the crystallized silicon film.

In the present invention, a portion where a crystal has grown laterally from the crystal nucleus region where silicon ions have not been implanted is used as a channel forming region of a TFT or TFD. This is because the crystal orientation is random in the crystal nucleus region,
In addition, the size of the crystal grains varies. On the other hand, in the laterally grown region, the crystals are aligned in the growth direction, and the size of the crystals is also uniform. Therefore, the orientation of the crystal and the TFT
The characteristics can be improved by optimizing the direction of the drain current.

[0014]

[Embodiment 1] This embodiment is directed to a P-channel TFT (PT) using a crystalline silicon film formed on a glass substrate.
FT) and N-channel TFT (NTFT)
This is an example of forming a circuit in which are combined in a complementary manner. The configuration of this embodiment can be used for a switching element of a pixel electrode and a peripheral driver circuit of an active type liquid crystal display device, as well as an image sensor and an integrated circuit.

FIG. 1 is a sectional view showing a manufacturing process of this embodiment. First, a 2000-nm-thick silicon oxide base film 102 was formed on a substrate (Corning 7059) 101 by a sputtering method. The substrate is annealed at a temperature higher than the strain temperature before or after the formation of the base film, and then slowly cooled to a strain temperature or lower at 0.1 to 1.0 ° C./min. Substrate shrinkage in the accompanying steps (including the infrared light irradiation of the present invention) is small, and mask alignment is ready. For the Corning 7059 substrate, 620-66
After annealing at 0 ° C. for 1 to 4 hours, 0.1 to 1.0 ° C. /
Min, preferably 0.1 to 0.3 ° C./min.
It is good to take out at the stage when the temperature has dropped to 0 to 590 ° C.

After the formation of the base film, an intrinsic (I-type) amorphous silicon film 103 having a thickness of 300 to 1500 °, for example, 800 ° was formed by a plasma CVD method. And
A mask 104 formed of a photoresist was provided. This mask 104 has a slit-like shape of the amorphous silicon film 1.
03 is exposed. That is, when the state of FIG. 1A is viewed from above, the amorphous silicon film 103 is exposed in a slit shape, and the other portions are masked. After providing the mask 104, 5
Silicon ions were implanted into the amorphous silicon film 103 at a dose of × 10 ¹⁵ cm ^-2 . The acceleration voltage was set to 40 to 150 keV, for example, 80 keV. (Fig. 1 (A))

Next, the mask 104 was removed. Then, it was crystallized by thermal annealing at 600 ° C. for 24 hours in a nitrogen inert atmosphere (atmospheric pressure). At this time, many crystal nuclei were generated in the region 105 into which silicon ions had not been implanted, and crystal growth proceeded from the region 105 in a lateral direction (a direction parallel to the substrate) as indicated by arrows. Area 10
The region 103 ′ sufficiently far from 5 remained amorphous. (FIG. 1 (B))

After this step, the silicon film was patterned to form a TFT island-shaped active layer 104 '. At this time, it is important that the region 105 in which a crystal nucleus is generated and the amorphous region 103 'do not exist in a portion to be a channel formation region. By doing so, the direction and the grain size of the silicon crystal in the active layer can be made uniform, and T
An FT can be made. The size of the active layer 104 'is determined in consideration of the channel length and channel width of the TFT. The size was 50 μm × 20 μm for the small one and 100 μm × 1000 μm for the large one.

Many such active layers were formed on the substrate. And, 0.5 to 4 μm, here 0.8 to 1.4 μm
Visible / infrared light having a peak at m was irradiated for 30 to 180 seconds to further promote crystallization of the active layer. The temperature is 800
To 1300 ° C, typically 900 to 1200 ° C, for example 1100 ° C. Irradiation was performed in an H ₂ atmosphere to improve the condition of the surface of the active layer. In this step, since the active layer is selectively heated, heating of the glass substrate can be minimized. And, it is very effective in reducing defects and unbound bonds in the active layer. (Fig. 1 (C))

As a visible / infrared light source, a halogen lamp was used. The intensity of visible / near-infrared light was adjusted so that the temperature of the monitor on the single crystal silicon wafer was 800 to 1300 ° C, typically 900 to 1200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. In the present embodiment, the temperature rise / fall is performed as shown in FIG.
(A) or (B). The temperature rise is constant, the speed is 50-200 ° C./sec, and the temperature fall is 20 by natural cooling.
１００100 ° C.

FIG. 4A shows a general temperature cycle, which comprises three steps of a temperature rising time a, a holding time b, and a temperature falling time c. However, in this case, since the sample is rapidly heated and cooled from room temperature to as high as 1000 ° C., and further from the high temperature state to room temperature, the influence on the silicon film and the substrate is large, and the possibility of peeling of the silicon film is also high. high. In order to solve this problem, as shown in FIG. 4 (B), a preheating time d and a post-heating time f are provided before reaching the holding time, and before reaching the holding time, the substrate or film at 200 to 500 ° C. It is desirable to keep it at a temperature that does not have a significant effect.

It is preferable to form a silicon oxide or silicon nitride film as a protective film on the surface of the substrate when the infrared light is irradiated. This is to improve the state of the surface of the silicon film 104 '. In order to improve the state of the surface of the silicon film 104 'was performed in H ₂ atmosphere. H ₂
0.1 to 10% HCl, a compound of hydrogen halide, fluorine, chlorine or bromine may be mixed in the atmosphere.

This visible / near-infrared light irradiation selectively heats the crystallized silicon film, so that the heating of the glass substrate can be minimized. And it is very effective in reducing the defects and the dangling bonds in the silicon film. It is important that the visible / near-infrared light irradiation is performed after the crystallization step by heating. When the amorphous silicon film was immediately irradiated with infrared light without being previously crystallized by thermal annealing, good crystals could not be obtained.

Next, a thickness of 10
A silicon oxide film 106 having a thickness of 00 ° was formed as a gate insulating film. TEOS (tetraethoxysilane, Si (OC ₂ H ₅ ) ₄ ) and oxygen are used as source gases for CVD.
The substrate temperature during film formation is 300 to 550 ° C., for example, 400 ° C.
And After the formation of the silicon oxide film 106 serving as the gate insulating film, light annealing by irradiation with visible / near infrared light was performed again. By this annealing, mainly the silicon oxide film 10
The level at the interface between the silicon film 6 and the silicon film 104 and in the vicinity thereof could be eliminated. This is extremely useful for an insulated gate field effect semiconductor device in which the interface characteristics between the gate insulating film and the channel formation region are extremely important.

Subsequently, by a sputtering method,
Aluminum (including 0.01 to 0.2% scandium) having a thickness of 6000 to 8000 °, for example, 6000 ° was deposited. Then, the aluminum film was patterned to form gate electrodes 107 and 109. Further, the surface of the aluminum electrode was anodized to form oxide layers 108 and 110 on the surface. This anodization was performed in an ethylene glycol solution containing tartaric acid at 1 to 5%. The thickness of the obtained oxide layers 108 and 110 is 200
It was 0 °. Note that these oxides 108 and 110
In the later ion doping step, the thickness is such that the offset gate region is formed, so that the length of the offset gate region can be determined in the anodic oxidation step.

Next, by an ion doping method (also referred to as a plasma doping method), a gate electrode portion, that is, a gate electrode 107 and an oxide layer 108 around the gate electrode portion, 109 and the surrounding oxide layer 110 as a mask,
Impurities that impart P or N conductivity type are added in a self-aligned manner. Phosphine (PH) as doping gas
₃ ) and diborane (B ₂ H ₆ ) are used. In the former case, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and in the latter case, the acceleration voltage is 40 to 80 kV, for example, 65 kV. The dose was 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, phosphorus was 2 × 10 ¹⁵ cm ⁻² and boron was 5 × 10 ¹⁵ . At the time of doping, each element was selectively doped by covering one region with a photoresist. As a result, N-type impurity regions 114 and 116 and P-type impurity regions 111 and 113 are formed, and a P-channel TFT (PTFT) region and an N-channel TFT (NTT) are formed.
FT).

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser light is such that the energy density is 200 to 400 mJ / cm.
² , for example, 250 mJ / cm ² ,
Irradiation was performed for 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light. (Figure 1
(D))

This step may be performed by lamp annealing using visible / near infrared light. Visible and near-infrared light is crystallized silicon or phosphorus or boron in 10 ¹⁹ to 10
It is easily absorbed by amorphous silicon to which ²¹ cm ^{-3 is} added.
Effective annealing comparable to thermal annealing of 000 ° C. or more can be performed. When phosphorus or boron is added, light is sufficiently absorbed even in the near infrared due to the impurity scattering. This can be fully guessed from the fact that it is black even with the naked eye. On the other hand, since it is hardly absorbed by the glass substrate, it is not necessary to heat the glass substrate to a high temperature, and the process can be performed in a short time. .

Subsequently, a silicon oxide film 11 having a thickness of 6000.degree.
8 was formed as an interlayer insulator by a plasma CVD method. As the interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, a contact hole is formed, and a metal material, for example, a multilayer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 1.
17, 120 and 119 were formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm.
Was completed in a complementary type. (Figure 1
(E)) In particular, in the present invention, dangling bonds generated in the step of optical annealing with visible / near infrared light are neutralized by heating at 250 to 400 ° C. in a hydrogen atmosphere in a subsequent step. This is very important.

The circuit shown above has a CMOS structure in which a PTFT and an NTFT are provided in a complementary manner. In the above-described process, two TFTs are formed at the same time and cut at the center, whereby two independent TFTs are formed at the same time. It is also possible to produce.

[Embodiment 2] This embodiment is an example in which an N-channel TFT is provided in each pixel as a switching element in an active liquid crystal display device. Hereinafter, one pixel will be described, but a large number (generally, hundreds of thousands) of other pixels are formed in a similar structure. Also, N
It goes without saying that a P-channel TFT may be used instead of a channel TFT. Further, it can be used not only for the pixel portion of the liquid crystal display device but also for the peripheral circuit portion. Further, it can be used for image sensors and other devices. That is, as long as it is used as a thin film transistor, its use is not particularly limited.

FIG. 2 shows an outline of the manufacturing process of this embodiment.
In this embodiment, the substrate 201 is Corning 70
59 glass substrate (1.1 mm thick, 300 × 400 m
m) was used. First, a base film 202 (silicon oxide) was formed to a thickness of 2000 ° by a plasma CVD method. CVD
TEOS and oxygen were used as raw material gases for the above. After the formation of the base film, the thickness is 300 to 150 by the plasma CVD method.
Intrinsic (I-type) amorphous silicon film 2 of 0 °, for example, 800 °
03 was formed. Then, a mask 204 formed of a photoresist was provided. Further, silicon ions were implanted into the amorphous silicon film 103 at a dose of 1 × 10 ¹⁵ cm ⁻² by an ion implantation method. Acceleration voltage is 40-150
keV, for example, 80 keV. (Fig. 2 (A))

After that, the photoresist mask 204 was removed, the amorphous silicon film 203 was dehydrogenated at 450 ° C. for 1 hour, and then crystallized by heat annealing.
This annealing step was performed at 600 ° C. for 48 hours in a nitrogen atmosphere. In this annealing step, the region 205 below the photoresist mask 204 was not doped with silicon ions, and crystallization occurred from this portion.
During this crystallization, the growth expanded from the region 205 in the lateral direction as shown by the arrow in FIG. Region 203 '
Is an uncrystallized region. (FIG. 2 (B))

After this thermal annealing step, the crystallized silicon film was patterned to leave only the TFT island-like active layer 205 ', and to remove the others. At this time, it is important that the region 205 where the crystal nuclei are generated does not exist in the active layer, especially in the channel formation region. Of course, it is not desirable that the uncrystallized region 203 ′ also exists in the channel formation region. That is, the silicon film 203 shown in FIG.
Of these, at least the uncrystallized region 203 'and the region 205 where the crystal nuclei are generated are removed by etching, and the intermediate portion of the crystalline silicon film 203 crystal-grown in a direction parallel to the substrate is used as an active layer. Is preferred. This is because the direction and the size of the crystal grains in the region 205 where the crystal nuclei are generated are random. After patterning in this manner, visible / near-infrared light was applied to the island-shaped active layer 205 ', and light annealing was performed. The temperature was 1100 ° C. and the time was 30 seconds. (Fig. 2 (C))

Further, tetraethoxysilane (TEO)
S) as a raw material, a gate insulating film of silicon oxide (thickness of 70 to 120 n) is formed by a plasma CVD method in an oxygen atmosphere.
m, typically 120 nm) 206 was formed. The substrate temperature was 350 ° C. Next, a gate electrode 207 was formed by forming a known film containing polycrystalline silicon as a main component by a CVD method and performing patterning. Phosphorous is added to polycrystalline silicon as an impurity in an amount of 0.1 to 5 to improve conductivity.
% Introduced.

Thereafter, phosphorus is implanted as an N-type impurity by ion doping, and the source region 20 is self-aligned.
8, a channel formation region 209 and a drain region 210 were formed. By irradiating a KrF laser beam, the crystallinity of the silicon film having deteriorated crystallinity due to ion implantation was improved. At this time, the energy density of the laser beam was set to 250 to 300 mJ / cm ² . Due to this laser irradiation, the source / drain sheet resistance of this TFT became 300 to 800 Ω / cm ² . Also,
This step may be performed by lamp annealing of visible / near infrared light. (FIG. 2 (D))

Thereafter, an interlayer insulator 211 is formed of silicon oxide or polyimide, and further, a pixel electrode 212 is formed.
Was formed by ITO. Then, a contact hole is formed, and a chromium /
The electrodes 213 and 214 are formed of an aluminum multilayer film, and one of the electrodes 214 is also connected to the ITO 212. Finally, hydrogenation was performed by annealing in hydrogen at 200 to 400 ° C. for 2 hours. In this way,
The TFT was completed. This process is performed simultaneously in many other pixel regions. In order to further improve the moisture resistance, a passivation film may be formed on the entire surface using silicon nitride or the like. (FIG. 2 (E))

In the TFT manufactured in this embodiment, a crystalline silicon film grown in the direction in which carriers flow is used as an active layer constituting a source region, a channel formation region, and a drain region. Is not traversed by the carrier, that is, the carrier moves along the crystal grain boundary of the needle-like crystal, so that a TFT having high carrier mobility can be obtained. TFT manufactured in this example
Is an N-channel type, and its mobility is 90 to 130.
(Cm ² / Vs). Movement to an N-channel TFT using a crystalline silicon film obtained by crystallization by conventional thermal annealing without paying attention to the size and direction of the crystal is 50%.
This is a great improvement in characteristics as compared with being about 70 (cm ² / Vs). Furthermore, unless annealing by irradiation with visible / near infrared light is performed after the crystallization step by thermal annealing, generally only those having low mobility and low on / off ratio can be obtained. From this, it was found that the step of promoting crystallization by intense light irradiation is useful for improving the reliability of the TFT.

[Embodiment 3] This embodiment will be described with reference to FIG. First, a base film 302 is formed on a glass substrate 301, and a thickness of 300 to 8
An amorphous silicon film 303 of 00 ° was formed. Then, silicon ions are selectively implanted using a photoresist mask in the same manner as in the first embodiment.
Heat annealing for 8 hours was performed to crystallize the silicon film 303. At this time, as indicated by the arrow, crystal growth progressed in the lateral direction from the region 304 into which silicon ions had not been implanted. The region 303 'is an uncrystallized region. (FIG. 3
(A))

Next, the silicon film 303 is patterned
Island-shaped active layer regions 305 and 306 were formed. At this time, a region indicated by 304 in FIG. 3A is a region where silicon ions have not been implanted, and is a region in which the size and direction of crystal grains are random. Therefore, also in this embodiment, the active layer regions 305 and 306, which are regions for forming an active element, for example, a TFT, are patterned avoiding the region 304. The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction. (FIG. 3
(B))

Next, a silicon oxide or silicon nitride film 307 having a thickness of 200 to 3000 ° was formed by a plasma CVD method. Then, lamp annealing of visible / near-infrared light was performed in the same manner as in Example 1. The conditions were the same as in Example 1. In this embodiment, when irradiating visible / near infrared light,
Since a protective film of silicon oxide or silicon nitride was formed on the surface of the active layer, it was possible to prevent the surface from being roughened and contaminated upon irradiation with infrared light. (FIG. 3 (C))

After irradiation with visible / near infrared light, the protective film 307 was removed. Thereafter, as in the first embodiment, the gate insulating film 30 is formed.
8. Form gate electrodes 309 and 310 (FIG. 3 (D))
Then, an interlayer insulator 311 was formed, a contact hole was formed therein, and metal wirings 312, 313, and 314 were formed. (FIG. 3E) Thus, a complementary TFT circuit was formed. In the present embodiment, a protective film is formed on the surface of the active layer upon irradiation with visible / near infrared light, so that surface roughness and contamination are prevented. Therefore, the characteristics (electric field mobility and threshold voltage) and reliability of the TFT of this example were extremely good.

[0043]

According to the present invention, the crystallinity of a crystalline silicon film which has been laterally crystallized by silicon ion implantation and heat annealing is increased by additionally performing light annealing of visible / near infrared light irradiation. At the same time, the film quality could be densified, and a silicon film having good crystallinity could be obtained. Furthermore, after an insulating film is formed on the silicon film, annealing is performed by irradiating infrared light, whereby interface states can be reduced. After these steps, hydrogenation annealing is performed in a hydrogen atmosphere. 200-450
By the treatment at ℃, dangling bonds could be removed and neutralized. As described above, the present invention is extremely effective for forming an insulating gate type semiconductor device.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of a TFT of Example 1.

FIG. 2 illustrates a manufacturing process of a TFT of Example 2.

FIG. 3 illustrates a manufacturing process of a TFT according to a third embodiment.

FIG. 4 shows an example of temperature setting in the first embodiment.

[Explanation of symbols]

 Reference Signs List 101 glass substrate 102 base film (silicon oxide film) 103 silicon film 103 ′ uncrystallized silicon region 104 mask 104 ′ island-like silicon film (active layer) 105 region where crystal nuclei are generated 106 gate insulating film (silicon oxide film) 107 , 109 Gate electrode (aluminum) 108, 110 Anodized layer (aluminum oxide) 111, 114 Source (drain) region 112, 115 Channel formation region 113, 116 Drain (source) region 117, 119 Electrode 118 Interlayer insulator 120 Electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 29/786 H01L 21/20 H01L 21/268 H01L 21/336 H01L 27/12

Claims (4)

(57) [Claims] 1. A first step of forming an amorphous silicon film on a glass substrate, a second step of pre-crystallized Ki珪 Motomaku by thermal annealing, crystallized by the second step Pattern the silicon film
A third step of forming a plurality of island-shaped regions by performing cleaning, and a wavelength of 0.5
The method for manufacturing a semiconductor device having the fourth step for promoting crystallization by irradiating intense light Myuemu～4myuemu. 2. A step according to claim 1, wherein after the second step or the third step, an insulating film that covers the island region and transmits strong light used in the fourth step is formed. A method for manufacturing a semiconductor device having: 3. The method for manufacturing a semiconductor device according to claim 2, wherein the insulating film is a film containing silicon nitride or silicon oxide as a main component. 4. The method according to claim 1, wherein after the fourth step,
A method for manufacturing a semiconductor device, comprising a step of neutralizing dangling bonds of silicon by performing thermal annealing at 200 to 450 ° C. in a hydrogen atmosphere.