JPS59182569A - Polycrystalline silicon thin-film transistor - Google Patents
Polycrystalline silicon thin-film transistorInfo
- Publication number
- JPS59182569A JPS59182569A JP5510383A JP5510383A JPS59182569A JP S59182569 A JPS59182569 A JP S59182569A JP 5510383 A JP5510383 A JP 5510383A JP 5510383 A JP5510383 A JP 5510383A JP S59182569 A JPS59182569 A JP S59182569A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- hydrogen
- film transistor
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 38
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 239000010408 film Substances 0.000 claims abstract description 34
- 239000001257 hydrogen Substances 0.000 claims abstract description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000007789 gas Substances 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 18
- 238000010438 heat treatment Methods 0.000 abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract description 3
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000000415 inactivating effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000002779 inactivation Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は多結晶シリコン薄膜トランジスタ、特に良好な
出力特性が得られる多結晶シリコン薄膜トランジスタに
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a polycrystalline silicon thin film transistor, and particularly to a polycrystalline silicon thin film transistor that provides good output characteristics.
薄膜トランジスタは、絶縁体基板上に蒸着等によシ、半
導体薄膜を被着形成して能動素子を作ったもので、通常
は電界効果形でオシ、構造および動作ともにMOS−F
ETに類以している。しかしながらM9S−FETが通
常単結晶基板を用いて形成されるのに対して仁の薄膜ト
ランジスタは絶縁体基板上に形成した半導体薄膜によっ
て構成されるために大面積トランジスタプレイを製作で
きるという利点を有している。このため、例えば、液晶
マトリックスディスプレイのクロストーク防止用スイッ
チング素子として極めて好適である。すなわち液晶マト
リックスディスプレイは近年ポケットテレビやコンピュ
ータ端末用機器として開発が進められ、画像の一層の精
細化が求められているが、画素子数の増加に伴なうクロ
ストークを防止するためには、各画素にスイツチンク素
子を旧設する手段が有効である。この場合、渦膜トラン
ジスタを用いれはディスプレイパネルの一方の基板上に
形成できるので不利である。またこの場合、薄膜を構成
する半導体としては、c(1s l Cd86等の化合
物やアモルファスシリコン等も用いられるが、特性の安
定性や無公害の観点から多結晶シリコンが最もすぐれて
いる〇
第1図および第2図は、通常用いられているこの種の薄
膜トランジスタの一例を示す要部断面図である。同図に
おいて、1はガラス等からなる絶縁体基板、2は半導体
膜、3は絶縁膜、495はソース、ドレイン電極、6は
ゲート電極である。A thin film transistor is an active element made by depositing a semiconductor thin film on an insulating substrate by vapor deposition or other methods.
Similar to ET. However, unlike M9S-FETs, which are usually formed using a single crystal substrate, NIN thin film transistors have the advantage of being able to fabricate large-area transistor layers because they are constructed from a semiconductor thin film formed on an insulator substrate. ing. Therefore, it is extremely suitable as, for example, a switching element for preventing crosstalk in a liquid crystal matrix display. In other words, in recent years, liquid crystal matrix displays have been developed as devices for pocket TVs and computer terminals, and there is a need for even higher definition images, but in order to prevent crosstalk due to the increase in the number of pixels, An effective method is to provide a switching element in each pixel. This is disadvantageous because the vortex film transistor can be formed on one substrate of the display panel. In this case, compounds such as c(1s l Cd86) and amorphous silicon can also be used as the semiconductor constituting the thin film, but polycrystalline silicon is the best from the viewpoint of stability of characteristics and non-polluting. 2 and 2 are main part sectional views showing an example of this type of thin film transistor that is commonly used. In the figure, 1 is an insulating substrate made of glass or the like, 2 is a semiconductor film, and 3 is an insulating film. , 495 are source and drain electrodes, and 6 is a gate electrode.
しかしながら、上記構成を肩する薄膜トランジスタにお
いて、半導体膜2が多結晶シリコンの場合、膜厚が薄い
と結晶性が不十分で良好な動作特性が得られず、良好な
動作特性を得るためには膜である。ところが、半導体膜
2の膜厚をこのように厚くすると、第1図、第2図の構
造の場合、ゲートに′社1三を印加してもソース電極4
およびドレイン電極t1近傍の半導体膜2にキャリアが
十分に励起されず、動作しにくくなるという欠点があっ
た。そこで半導体膜2として多結晶シリコンを用いる場
合には、キャリア励起上、有利な第3図。However, in a thin film transistor that has the above structure, when the semiconductor film 2 is made of polycrystalline silicon, if the film is thin, the crystallinity is insufficient and good operating characteristics cannot be obtained. It is. However, if the thickness of the semiconductor film 2 is increased in this way, in the structure shown in FIGS.
Another disadvantage is that carriers are not sufficiently excited in the semiconductor film 2 near the drain electrode t1, making it difficult to operate. Therefore, when polycrystalline silicon is used as the semiconductor film 2, it is advantageous in terms of carrier excitation as shown in FIG.
第4図の構造が望ましいと考えられる。なお、第3図、
第11図において、第1図、第2図と同一部を形成、後
、多結晶シリコンの半導体膜2を形成することになるが
、多結晶シリコン膜を形成するためには基板温度を約5
00℃あるいはそれ以−りに上げる必要があり、シリコ
ン膜4形、成する時点で電。The structure shown in FIG. 4 is considered desirable. In addition, Figure 3,
In FIG. 11, the same part as in FIGS. 1 and 2 will be formed, and later a polycrystalline silicon semiconductor film 2 will be formed.
It is necessary to raise the temperature to 00°C or higher, and the temperature is high when the silicon film is formed.
極材料がシリコン中に拡散、あるいはシリコンと反応し
てしまい、実際上採用できないという欠点がある。結局
半導体膜2として多結晶シリコンを用いる場合には第4
図の構造をとらざるを得なくなる。The disadvantage is that the electrode material diffuses into the silicon or reacts with the silicon, making it practically unusable. After all, when polycrystalline silicon is used as the semiconductor film 2, the fourth
I am forced to adopt the structure shown in the figure.
第4図の構造の場合、ソース電極4.ドレイン電極5の
形成は、マスク蒸着でも可能であるが、電極パターンの
精度が不十分であり、ソース電極4とドレイン電極5間
のリークが起シやすいなどの欠点がある。これに対して
フォトエツチングでは容易に所定の電極パターンを形成
することができて望ましい結果を得ることができる。ま
た、電極材料としては多結晶シリコンと反応しにくいこ
と、良好な電気的コンタクトがとれることなどの条件を
考慮すると、はぼM仄限定される。結局多結晶シリコン
薄膜トランジスタのソース電稜4゜ドレイン電極5とし
てはフォトエツチングでAtのパターンを形成したもの
が望ましいことになる。In the case of the structure shown in FIG. 4, the source electrode 4. Although the drain electrode 5 can be formed by mask vapor deposition, there are drawbacks such as insufficient precision of the electrode pattern and leakage between the source electrode 4 and the drain electrode 5. On the other hand, photoetching can easily form a predetermined electrode pattern and produce desirable results. Further, considering the conditions that the electrode material should not easily react with polycrystalline silicon and that good electrical contact can be made, the electrode material is limited to M. As a result, it is desirable that the source electrode 4° drain electrode 5 of the polycrystalline silicon thin film transistor be formed with an At pattern formed by photoetching.
しかしながら、このよう彦多結晶シリコン薄膜トランジ
スタを製作したところ、以下の問題があることがわかっ
た。すなわち、ソース電極4.ドレイン電極5形成後の
多結晶シリコン表面は極めて活性であるため、ゲート絶
縁膜3が形成されるまでの間に外気にさらされると、伺
等かの変質を生じ、完成した多結晶シリコン薄膜トラン
ジスタの出力特性が変化する。その結果、多結晶シリコ
ン薄膜トランジスタを再現性よく製造することは極めて
困難であった。However, when such a Hiko polycrystalline silicon thin film transistor was manufactured, the following problems were found. That is, the source electrode 4. Since the polycrystalline silicon surface after forming the drain electrode 5 is extremely active, if it is exposed to the outside air before the gate insulating film 3 is formed, it will undergo some deterioration, causing damage to the completed polycrystalline silicon thin film transistor. Output characteristics change. As a result, it has been extremely difficult to manufacture polycrystalline silicon thin film transistors with good reproducibility.
したがって本発明は前述した問題点に・鑵みてなされた
ものであシ、その目的とするところは、良好な出力特性
を有し、かつ再現性良く得られる多結晶シリコン薄膜ト
ランジスタを提供することにある。Therefore, the present invention has been made in consideration of the above-mentioned problems, and its purpose is to provide a polycrystalline silicon thin film transistor that has good output characteristics and can be obtained with good reproducibility. .
このような目的を達成するために本発明は、ソース電極
、ドレイン電極を形成した後に多結晶シリコンの表面を
不活性化処理するものである。In order to achieve this object, the present invention subjects the surface of polycrystalline silicon to inactivation treatment after forming the source and drain electrodes.
次に図面を用いて本発明の実施例を詳細に説明する。 Next, embodiments of the present invention will be described in detail using the drawings.
まず、第4図において、ソース電極4.ドレイン電極5
を形成した後、多結晶シリコン半導体膜2の表面を水素
あるいは水素と不活性ガス、例えば窒素との混合ガス中
で熱処理する。このような方法によれは多結晶シリコン
半導体膜20表面が不活性化され、その後に多結晶シリ
コン半導体膜2の表面をゲート絶縁膜3が形成されるま
での間に外気にさらされても汚染させない限シ完成した
多結晶シリコン薄膜トランジスタの出力特性が変化する
ことがない。この結果、多結晶シリコン薄膜トランジス
タを再現性良く製造することが可能となる。First, in FIG. 4, the source electrode 4. Drain electrode 5
After forming the polycrystalline silicon semiconductor film 2, the surface of the polycrystalline silicon semiconductor film 2 is heat-treated in hydrogen or a mixed gas of hydrogen and an inert gas, such as nitrogen. With this method, the surface of the polycrystalline silicon semiconductor film 20 is inactivated, and even if the surface of the polycrystalline silicon semiconductor film 2 is exposed to the outside air until the gate insulating film 3 is formed, it will not be contaminated. As long as this is not done, the output characteristics of the completed polycrystalline silicon thin film transistor will not change. As a result, it becomes possible to manufacture polycrystalline silicon thin film transistors with good reproducibility.
なお、ここで、処理雰囲気は100moz%水素であれ
ば何隻問題なく、イ・活性ガスとの混合ガスの場合は水
素量が1m□t%以上であれば、良好な結果を得ること
ができる。また、熱処理温度は120℃を下まわると、
十分な効果が得られず、また440℃を超えると、ソー
ス、ドレイン′電極のAtが多結晶シリコンの粒界中に
拡散して多結晶シリコン薄膜トランジスタの出力特性を
劣化させるため、120℃から440℃の範囲、より望
ましくは250℃から380℃の範囲が適邑である。Here, if the processing atmosphere is 100 moz% hydrogen, there will be no problem, and in the case of a mixed gas with active gas, good results can be obtained if the hydrogen amount is 1 m□t% or more. . In addition, when the heat treatment temperature is lower than 120℃,
If a sufficient effect is not obtained, and if the temperature exceeds 440°C, At in the source and drain' electrodes will diffuse into the grain boundaries of polycrystalline silicon and deteriorate the output characteristics of the polycrystalline silicon thin film transistor. A suitable temperature range is 250°C to 380°C, more preferably 250°C to 380°C.
fた、水素あるいは水素と不活性カスとの混合ガス中で
熱処理する以前あるいは以後に多結晶シリコン半導体膜
の表面を酸素プラズマ処理すると、完成後の多結晶シリ
コン薄膜トランジスタの出力特性を長期間にわたって安
定化石せることかできる。Furthermore, if the surface of the polycrystalline silicon semiconductor film is treated with oxygen plasma before or after heat treatment in hydrogen or a mixed gas of hydrogen and inert residue, the output characteristics of the completed polycrystalline silicon thin film transistor can be stabilized for a long period of time. It is possible to turn it into a fossil.
以上説明したように本発明によれは、ソース電極、ドレ
イン電極形成後に多結晶シリコン半導体膜の素面を水素
あるいは水素と不活性ガスとの混合カス−1で熱処理す
ることによって、多結晶シリコン生駒1i : Mの表
面を安定化できるので、出力特性の良好・′f多結晶シ
リコン薄膜トランジスタを再現性良、く得られるという
罹めて優れた効果を有する。As explained above, according to the present invention, after forming the source electrode and the drain electrode, the bare surface of the polycrystalline silicon semiconductor film is heat-treated with hydrogen or a mixture of hydrogen and an inert gas. : Since the surface of M can be stabilized, it has an extremely excellent effect in that a polycrystalline silicon thin film transistor with good output characteristics and high reproducibility can be obtained.
第1図ないし第3図は従来の多結晶シリコン(1(膜ト
ランジスタの要部断面図、第4図は本発明(でよる多結
晶シリコン薄膜トランジスタの一例を説5明するための
要部断面図である。
1・・・・絶縁体基板、2・・・・多結晶:/ IJコ
ン半導体膜、3・・・・絶縁膜、4・・・・ソース電極
、5・・・・ ド1/イン電極 6 a * +1 ・
ゲート電極。1 to 3 are cross-sectional views of main parts of conventional polycrystalline silicon thin film transistors, and FIG. 4 is a cross-sectional view of main parts for explaining an example of a polycrystalline silicon thin film transistor according to the present invention. 1... insulator substrate, 2... polycrystalline:/ IJ contact semiconductor film, 3... insulating film, 4... source electrode, 5... do 1/ In-electrode 6 a * +1 ・
gate electrode.
Claims (1)
晶シリコン薄膜トランジスタにおいて、前記多結晶シリ
コン膜上にソース、ドレイン電極を形成した後に少なく
とも水素を含む混合ガス中で熱処理して該多結晶シリコ
ン膜の表面を不活性化させたことを特徴とする多結晶シ
リコン薄膜トランジスタ。In a polycrystalline silicon thin film transistor made of a polycrystalline silicon film formed on an insulating substrate, after forming source and drain electrodes on the polycrystalline silicon film, the polycrystalline silicon film is heat-treated in a mixed gas containing at least hydrogen. A polycrystalline silicon thin film transistor characterized by having an inactivated surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5510383A JPS59182569A (en) | 1983-04-01 | 1983-04-01 | Polycrystalline silicon thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5510383A JPS59182569A (en) | 1983-04-01 | 1983-04-01 | Polycrystalline silicon thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59182569A true JPS59182569A (en) | 1984-10-17 |
Family
ID=12989408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5510383A Pending JPS59182569A (en) | 1983-04-01 | 1983-04-01 | Polycrystalline silicon thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59182569A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0540163A2 (en) * | 1991-09-23 | 1993-05-05 | Xerox Corporation | Switched capacitor analog circuits |
JPH0745839A (en) * | 1993-07-31 | 1995-02-14 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
-
1983
- 1983-04-01 JP JP5510383A patent/JPS59182569A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0540163A2 (en) * | 1991-09-23 | 1993-05-05 | Xerox Corporation | Switched capacitor analog circuits |
EP0540163A3 (en) * | 1991-09-23 | 1994-06-15 | Xerox Corp | Switched capacitor analog circuits |
US5589847A (en) * | 1991-09-23 | 1996-12-31 | Xerox Corporation | Switched capacitor analog circuits using polysilicon thin film technology |
JPH0745839A (en) * | 1993-07-31 | 1995-02-14 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3864817A (en) | Method of making capacitor and resistor for monolithic integrated circuits | |
US6570184B2 (en) | Thin film transistor and method for manufacturing the same | |
JPS58115864A (en) | Semiconductor device | |
EP0051940B1 (en) | Annealing process for a thin-film semiconductor device and obtained devices | |
JPS59182569A (en) | Polycrystalline silicon thin-film transistor | |
US20030150383A1 (en) | Semiconductor device or thin-film transistor manufacturing apparatus and manufacturing method | |
JPH0564862B2 (en) | ||
JPH0351094B2 (en) | ||
JPH0554271B2 (en) | ||
JPH05275702A (en) | Thin-film transistor | |
JPH0740607B2 (en) | Method of manufacturing thin film transistor | |
JPS61150278A (en) | Thin film transistor | |
JPH0616560B2 (en) | Method of manufacturing thin film transistor | |
JP3325664B2 (en) | Thin film transistor and method of manufacturing the same | |
KR900008942B1 (en) | Poly-crystal thin-film transistor | |
JPS62105474A (en) | Semiconductor device | |
KR910001910B1 (en) | Surface display device | |
JP3016486B2 (en) | Thin film transistor | |
KR100301852B1 (en) | Method for fabricating tft | |
JPS5821868A (en) | Manufacture of thin polycrystalline silicon film transistor | |
JPH01103888A (en) | Switching element | |
JPH0330296B2 (en) | ||
JPH0336313B2 (en) | ||
JPH04233738A (en) | Manufacture of thin-film transistor | |
JPH077156A (en) | Thin film field effect transistor |