JPH0616560B2 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistorInfo
- Publication number
- JPH0616560B2 JPH0616560B2 JP57221565A JP22156582A JPH0616560B2 JP H0616560 B2 JPH0616560 B2 JP H0616560B2 JP 57221565 A JP57221565 A JP 57221565A JP 22156582 A JP22156582 A JP 22156582A JP H0616560 B2 JPH0616560 B2 JP H0616560B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- forming
- gate insulating
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000010408 film Substances 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Description
【発明の詳細な説明】 本発明は、スレツシヨールド電圧が低く、そのばらつき
も小さい薄膜トランジスタの製造方法に関する。The present invention relates to a method of manufacturing a thin film transistor having a low threshold voltage and a small variation in the threshold voltage.
近年、絶縁物基板上に形成できる薄膜トランジスタの開
発が、各所で盛んである。絶縁物基板（ガラス等）上
に、薄膜トランジスタからなるスイツチ素子をアレイ状
に設けたマトリクス液晶表示装置は、ＴＶ画像の表示を
可能にする。しかし、現在のところ、ＴＶ画像の表示を
行なうのに充分な性能を持つた薄膜トランジスタは、得
られていない。その理由としては、薄膜トランジスタの
ゲート絶縁膜は、通常、低温ＣＶＤ法による二酸化ケイ
素膜あるいは、多結晶シリコンの熱酸化膜などが用いら
れる。これらのゲート絶縁膜を用いて形成した薄膜トラ
ンジスタは、ゲート絶縁膜中の固定電荷が２×１０11コ
／cm2以上になるので、トランジスタのスレツシヨール
ド電圧も大きく、ばらつきも大きくなる。また、これら
のゲート絶縁膜は、絶縁破壊耐圧も５０Ｖ／０．１μｍ
程度と低いので、信頼性にも欠けることになる。In recent years, the development of thin film transistors that can be formed on an insulating substrate has been active in various places. A matrix liquid crystal display device in which switch elements made of thin film transistors are arranged in an array on an insulating substrate (such as glass) enables display of TV images. However, at present, a thin film transistor having sufficient performance to display a TV image has not been obtained. The reason is that the gate insulating film of the thin film transistor is usually a silicon dioxide film formed by a low temperature CVD method or a thermal oxide film of polycrystalline silicon. In a thin film transistor formed using these gate insulating films, the fixed charge in the gate insulating film is 2 × 10 11 co / cm 2 or more, so that the threshold voltage of the transistor is large and the variation is large. Further, these gate insulating films have a breakdown voltage of 50 V / 0.1 μm.
Since it is low, it is not reliable.
本発明は、上記のごとき従来の欠点を除去し、高品質の
ゲート絶縁膜の開発により、安定で低い動作電圧の薄膜
トランジスタを製造することを目的としたものである。The present invention aims to eliminate the above-mentioned conventional defects and to manufacture a thin film transistor having a stable and low operating voltage by developing a high-quality gate insulating film.
以下、実施例に基づいて、図面により本発明を説明す
る。Hereinafter, the present invention will be described with reference to the drawings based on examples.
第１図は本発明の製造方法により得られたトランジスタ
の平面図、第２図は、第１図のＡ−Ａ′線に沿った断面
図である。これらの図面に示した薄膜トランジスタを構
成する各層の配置構造、製造工程の順序においては、従
来のものと特に変わることはない。FIG. 1 is a plan view of a transistor obtained by the manufacturing method of the present invention, and FIG. 2 is a sectional view taken along the line AA ′ of FIG. The arrangement structure of each layer forming the thin film transistor shown in these drawings and the order of manufacturing steps are not particularly different from those of the conventional one.
即ち、絶縁物基板１の上に、多結晶シリコンよりなるゲ
ート電極２、ゲート電極２の上に、ＣＶＤ法で形成した
絶縁膜上の多結晶シリコン、または、単結晶シリコン薄
膜よりなる半導体膜４、半導体膜上に形成されたソース
電極６とその接合層５、ドレイン電極８とその接合層７
からなる電界効果型薄膜トランジスタであり、 その製造工程として、基板上にゲート電極を設ける工
程、ゲート絶縁膜を形成する工程、半導体膜を形成する
工程、前記半導体膜上にソース電極及びドレイン電極を
形成する工程を経る点など従来のものと基本的に変わら
ない。That is, the gate electrode 2 made of polycrystalline silicon on the insulating substrate 1, the polycrystalline silicon on the insulating film formed by the CVD method on the gate electrode 2, or the semiconductor film 4 made of a single crystal silicon thin film. A source electrode 6 and its bonding layer 5 and a drain electrode 8 and its bonding layer 7 formed on a semiconductor film.
A field effect thin film transistor comprising: a step of forming a gate electrode on a substrate, a step of forming a gate insulating film, a step of forming a semiconductor film, and forming a source electrode and a drain electrode on the semiconductor film. Basically, there is no difference from the conventional ones in that the process of performing
ただ、本発明では、ゲート絶縁膜を形成する工程が、８
５０℃の温度雰囲気で、化学気相成長法（ＣＶＤ）法に
よって形成された二酸化ケイ素を形成することにあり、
実施例では、ガスとして、ジクロルシランと亜酸化チッ
ソの混合ガスを用いた。これにより形成された二酸化ケ
イ素の固定電荷密度は５×１０10／cm2以下であった。However, in the present invention, the step of forming the gate insulating film is 8
To form silicon dioxide formed by a chemical vapor deposition (CVD) method in a temperature atmosphere of 50 ° C.,
In the example, a mixed gas of dichlorosilane and nitrogen suboxide was used as the gas. The fixed charge density of the silicon dioxide thus formed was 5 × 10 10 / cm 2 or less.
この固定電荷密度の少ないゲート絶縁膜を用いた薄膜ト
ランジスタが、そのスレッシュホールド電圧が３Ｖ以下
で、そのバラツキが、±０．１Ｖ以内の値のものを得る
ことができた。It was possible to obtain a thin film transistor using the gate insulating film having a small fixed charge density, in which the threshold voltage was 3 V or less and the variation was within ± 0.1 V.
このような薄膜トランジスタの特性は、液晶表示装置の
スイッチ素子として特に好適である。The characteristics of such a thin film transistor are particularly suitable as a switch element of a liquid crystal display device.
なお、本発明の実施例では、ゲート絶縁膜の形成に際し
て、ジクロルシランと亜酸化チッソの混合ガスを用いて
説明したが、この混合ガスに限らず、要は、二酸化ケイ
素からなる絶縁膜を、８５０℃以上の温度雰囲気で化学
気相成長法（ＣＶＤ）法によって形成すれば、本発明の
特性を得ることができる。In the embodiments of the present invention, a mixed gas of dichlorosilane and nitrogen suboxide is used for forming the gate insulating film, but the present invention is not limited to this mixed gas. The characteristics of the present invention can be obtained by forming by a chemical vapor deposition (CVD) method in a temperature atmosphere of ℃ or more.
第１図は本発明の実施例の平面図、第２図は第１図のＡ
−Ａ′線に沿つた断面図である。 １……ガラス基板、２……電極 ３……絶縁膜、４……半導体膜 ５……接合層、６……電極、 ７……接合層、８……電極FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is A of FIG.
FIG. 6 is a cross-sectional view taken along the line A ′. 1 ... Glass substrate, 2 ... Electrode 3 ... Insulating film, 4 ... Semiconductor film 5 ... Bonding layer, 6 ... Electrode, 7 ... Bonding layer, 8 ... Electrode
Claims (1)
程、前記工程を経た絶縁物基板上にゲート絶縁膜を形成
する工程、前記ゲート絶縁膜上に半導体膜を形成する工
程、さらに、前記半導体膜上にソース電極及びドレイン
電極を形成する工程からなる薄膜トランジスタの製造方
法において、 前記ゲート絶縁膜を形成する工程が、８５０℃以上の温
度で化学気相成長法によって二酸化ケイ素を形成するも
のであり、これにより形成された固定電荷密度が５×１
０10個／cm2以下であることを特徴とする薄膜トランジ
スタの製造方法。1. A step of providing a gate electrode on the surface of an insulating substrate, a step of forming a gate insulating film on the insulating substrate that has undergone the steps, a step of forming a semiconductor film on the gate insulating film, and In the method of manufacturing a thin film transistor, which comprises the step of forming a source electrode and a drain electrode on a semiconductor film, the step of forming the gate insulating film forms silicon dioxide by chemical vapor deposition at a temperature of 850 ° C. or higher. Yes, the fixed charge density formed by this is 5 × 1
A method of manufacturing a thin film transistor, characterized in that the number is 10 / cm 2 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57221565A JPH0616560B2 (en) | 1982-12-17 | 1982-12-17 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57221565A JPH0616560B2 (en) | 1982-12-17 | 1982-12-17 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59111368A JPS59111368A (en) | 1984-06-27 |
| JPH0616560B2 true JPH0616560B2 (en) | 1994-03-02 |
Family
ID=16768717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57221565A Expired - Lifetime JPH0616560B2 (en) | 1982-12-17 | 1982-12-17 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0616560B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4821091A (en) * | 1986-07-22 | 1989-04-11 | The United States Of America As Represented By The United States Department Of Energy | Polysilicon photoconductor for integrated circuits |
| US4948741A (en) * | 1986-07-22 | 1990-08-14 | The United States Of America As Represented By The United States Department Of Energy | Polysilicon photoconductor for integrated circuits |
| US5859444A (en) * | 1991-08-08 | 1999-01-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2901163B2 (en) * | 1991-08-08 | 1999-06-07 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4254161A (en) * | 1979-08-16 | 1981-03-03 | International Business Machines Corporation | Prevention of low pressure chemical vapor deposition silicon dioxide undercutting and flaking |
| JPS56142642A (en) * | 1980-04-07 | 1981-11-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5730882A (en) * | 1980-07-31 | 1982-02-19 | Suwa Seikosha Kk | Active matrix substrate |
| JPS5769778A (en) * | 1980-10-17 | 1982-04-28 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1982
- 1982-12-17 JP JP57221565A patent/JPH0616560B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59111368A (en) | 1984-06-27 |
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