JPH0397271A - Image sensor - Google Patents
Image sensorInfo
- Publication number
- JPH0397271A JPH0397271A JP1235304A JP23530489A JPH0397271A JP H0397271 A JPH0397271 A JP H0397271A JP 1235304 A JP1235304 A JP 1235304A JP 23530489 A JP23530489 A JP 23530489A JP H0397271 A JPH0397271 A JP H0397271A
- Authority
- JP
- Japan
- Prior art keywords
- sensor
- layer
- tft
- forming
- sheets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 28
- 238000000034 method Methods 0.000 abstract description 14
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 239000010453 quartz Substances 0.000 abstract description 3
- 230000004913 activation Effects 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 3
- 238000001994 activation Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 102220043690 rs1049562 Human genes 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、光読取装置等において使用されるイメージセ
ンサに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image sensor used in an optical reading device or the like.
従来の代表的なイメージセンサの製造工程は,トランジ
スタ部を形成した後で、センサ部の感光層を形成してい
たため、トランジスタ部の形成工程数に加えてセンサ部
の形成工程数が加わった大へん多くの工程数を必要とし
ていた。これを第1図を参照して説明する。In the typical conventional image sensor manufacturing process, the photosensitive layer for the sensor section was formed after the transistor section was formed, so the number of steps for forming the sensor section was increased in addition to the number of steps for forming the transistor section. It required a very large number of steps. This will be explained with reference to FIG.
第1図■は薄膜トランジスタ(TPT)活性層の形成工
程であり、IIAs基板1上にTFT活性層としての多
結晶シリコン(Poly−Si)層2を形成する.■は
ゲート電極の形成工程であり、Poly−Si層2上に
ゲート酸化膜(Sin2膜)3とPoly−Siよりな
るゲート電極4を形成する.■はソース・ドレイン領域
へのイオン注入による活性化工程である.■は層間絶縁
膜5とコンタクトホール6の形成工程を示す.■は配線
電極(センサの下部電極に相当)7の形成工程であり、
■は光電変換機能をもつa一Si層(センサ感光層)8
の形成工程であり、■はエッチングによるセンサ部の形
或工程である.■はセンサ部のコンタクトホール9の形
或工程であり,■はセンサ部の電極10の形成工程であ
る.
このように、従来式のものは、薄膜トランジスタ部とセ
ンサ部を別々に形成しなければならず,このことは工程
数が多くなるのみならず、レジスト、エッチングのため
に使用するマスクの枚数もの,■,■,■,■,■,■
の工程で必要となり合,計7枚が必要である。1 shows the process of forming a thin film transistor (TPT) active layer, in which a polycrystalline silicon (Poly-Si) layer 2 as a TFT active layer is formed on an IIAs substrate 1. (2) is a step of forming a gate electrode, in which a gate oxide film (Sin2 film) 3 and a gate electrode 4 made of Poly-Si are formed on the Poly-Si layer 2. ■ is an activation process by ion implantation into the source and drain regions. 3 shows the process of forming the interlayer insulating film 5 and the contact hole 6. ■ is the formation process of the wiring electrode (corresponding to the lower electrode of the sensor) 7;
■ is a-Si layer (sensor photosensitive layer) 8 with photoelectric conversion function
(2) is the process of forming the sensor part by etching. (2) is the shape or process of the contact hole 9 in the sensor section, and (2) is the formation process of the electrode 10 in the sensor section. As described above, in the conventional method, the thin film transistor section and the sensor section must be formed separately, which not only increases the number of steps but also increases the number of resists, masks used for etching, etc. ■、■、■、■、■、■
A total of 7 sheets are required in this process.
このことはコスト高になるうえ,各工程での制約条件が
ふえることによりどうしても信頼性の低下をきたす。This not only increases costs, but also reduces reliability due to increased constraints in each process.
本発明の目的は、前記工程数を低減させ,使用マスクの
枚数を減らすことにより,低コスト化をはかり、かつ製
品の信頼性を高く保つ点にある。An object of the present invention is to reduce the number of steps and the number of masks used, thereby reducing costs and maintaining high product reliability.
本発明は、絶縁基板上に設けた薄膜トランジスタ部と、
それと同一基板上に形成されたセンサ部からなるイメー
ジセンサにおいて、トランジスタおよびセンサ共に多結
晶あるいは単結晶シリコンよりなる同一の用材を使用し
ていることを特徴とするものである.また、前記薄膜ト
ランジスタ部のゲート絶縁膜上に透明導電層を設けるこ
とは好ましい。The present invention includes a thin film transistor section provided on an insulating substrate;
An image sensor consisting of a sensor section formed on the same substrate is characterized in that both the transistor and the sensor use the same material made of polycrystalline or single crystal silicon. Further, it is preferable that a transparent conductive layer is provided on the gate insulating film of the thin film transistor section.
本発明を第2図を参照して説明する。The invention will be explained with reference to FIG.
■は石英やガラス等の絶縁基板1上にTFT活性層2と
センサ部感光N2’を形或するため多結晶シリコン層又
は単結晶シリコン層を形成する工程である。これにより
、TFT部とセンサ部の活性層が同一工程で形成される
.■はTFT部とセンサ部に同時にゲート絶縁膜3,3
′およびゲート電極4,4′を形或する工程である.■
はソース・ドレイン領域を形成するためのイオン注入に
よる活性化工程である。■は眉間絶縁層5の形成とコン
タクトホール6の形成工程である。■は配線電極7の形
一或工程である.これにより、使用マスク枚数は4枚に
おさえることができる。(2) is a step of forming a polycrystalline silicon layer or a single crystalline silicon layer on an insulating substrate 1 made of quartz, glass, etc. in order to form a TFT active layer 2 and a sensor part photosensitive layer N2'. As a result, the active layers of the TFT section and the sensor section are formed in the same process. ■ is the gate insulating film 3, 3 on the TFT part and the sensor part at the same time.
This is the step of forming the gate electrodes 4 and 4'. ■
is an activation step using ion implantation to form source/drain regions. (2) is the step of forming the glabella insulating layer 5 and the contact hole 6. (2) is a process for forming the wiring electrode 7. This allows the number of masks to be used to be reduced to four.
センサ部のゲート電極を透明電極にする場合,あるいは
、センサ部にH0イオン注入を行い光感度の向上を行う
場合には、使用マスク枚数は最大6枚を必要とするが,
前述の従来型の場合に較べれば,工程数、使用マスク枚
数共に低減している。When using a transparent electrode as the gate electrode of the sensor section, or when implanting H0 ions into the sensor section to improve photosensitivity, a maximum of 6 masks are required.
Compared to the conventional method described above, both the number of steps and the number of masks used are reduced.
まず石英基板上にLP−CVD法でPoly−SL層を
3000λ厚に形或する。形戊条件はSiH.100%
、600℃, 0.1torrであり、これにより粒径
500A前後のPoly−Si膜が形成される。その後
叶y02下、1000℃に2時間保つことにより約10
00人のゲート酸化膜が形成される。ついで、LP−C
VD法により、n”−Poly−Silを約3000入
厚に形或する。形或条件はPH33%を含有するS i
H 4を用い600℃, 0.1torrであった。ゲ
ート@極のバターニングはSF630SCCM, 0,
ltorrのドライエッチングにより行った。その後,
リンをSin2膜を通して1XIO”am−”ドーズイ
オン注入により注入し、900℃で30分活性化を行い
,TFT部とセンサ部のソース・ドレイン領域の形或を
行った.その後,ゲートのセルファラインを利用して,
HF:H20=1:6で60秒浸漬して、イオン注入時
にソース・ドレイン領域をカバーしていたSin,層を
エッチング除去し、ついで、コンタクトホール用層間絶
1#層を形成する.すナワチ、LP−CVD法によりS
iH4/o2= 80/200(SCCM)の条件下で
約5000 A厚のSi02層を形成するものである。First, a Poly-SL layer with a thickness of 3000λ is formed on a quartz substrate by the LP-CVD method. The forming conditions are SiH. 100%
, 600° C., and 0.1 torr, thereby forming a Poly-Si film with a grain size of approximately 500 Å. After that, by keeping it at 1000℃ for 2 hours under the leaves
00 gate oxide is formed. Next, LP-C
By VD method, n''-Poly-Sil is formed to a thickness of about 3000 mm.The conditions for forming are Si containing 33% PH.
The temperature was 600° C. and 0.1 torr using H 4 . Gate @ pole buttering is SF630SCCM, 0,
This was done by ltorr dry etching. after that,
Phosphorus was implanted through the Sin2 film by 1XIO "am-" dose ion implantation, and activated at 900°C for 30 minutes to form the source/drain regions of the TFT section and sensor section. After that, using the self-line of the gate,
It is immersed in HF:H20=1:6 for 60 seconds to etch away the Sin layer that covered the source/drain regions during ion implantation, and then forms a contact hole interlayer 1# layer. Sunawachi, S by LP-CVD method
A Si02 layer with a thickness of about 5000 A is formed under the condition of iH4/o2=80/200 (SCCM).
ついで,ウェットエッチングによりコンタクトホールを
形成する。エッチング条件は通常の熱Sin2除去の条
件と同一である。Next, contact holes are formed by wet etching. The etching conditions are the same as those for normal thermal Sin2 removal.
その後、AQをマグネトロンスパッタリングで約1μm
厚に形成し、Cx F t + S I C Q 4系
でドライエッチングし、本発明のイメージセンサを得た
.
〔効 果〕
本発明の層構戒を採ることにより、従来のものに較べて
その製造工程数を大巾に低減でき,使用マスクの枚数も
大巾に減すことができた。その結果,イメージセンサの
コストが下り、信頼性の高い製品を得ることができた。After that, AQ was applied to about 1 μm by magnetron sputtering.
The image sensor of the present invention was obtained by forming a thick film and dry etching with a Cx F t + SIC Q 4 system. [Effects] By adopting the layered structure of the present invention, the number of manufacturing steps can be greatly reduced compared to conventional products, and the number of masks used can also be greatly reduced. As a result, we were able to reduce the cost of image sensors and obtain highly reliable products.
第1図■〜■は従来型イメージセンサの製造工程を示し
、第2図■〜■は本発明イメージセンサの製造工程を示
す6
1:絶縁基板 6:コンタクトホール2:TFT
活性層 7:配線電極
2′:センサ部感光層 8:センサ感光層3:ゲート酸
化膜 9:コンタクトホール4:ゲート電極 1
0:電極
5:眉間絶縁層1: Insulating substrate 6: Contact hole 2: TFT
Active layer 7: Wiring electrode 2': Sensor part photosensitive layer 8: Sensor photosensitive layer 3: Gate oxide film 9: Contact hole 4: Gate electrode 1
0: Electrode 5: Insulating layer between eyebrows
Claims (1)
同一基板上に形成されたセンサ部からなるイメージセン
サにおいて、トランジスタおよびセンサ共に多結晶ある
いは単結晶シリコンよりなる同一の用材を使用している
ことを特徴とするイメージセンサ。 2、前記薄膜トランジスタ部のゲート絶縁膜上に透明導
電層を設けたことを特徴とする請求項1記載のイメージ
センサ。[Claims] 1. In an image sensor consisting of a thin film transistor section provided on an insulating substrate and a sensor section formed on the same substrate, both the transistor and the sensor are made of the same material made of polycrystalline or single crystal silicon. An image sensor characterized by its use. 2. The image sensor according to claim 1, further comprising a transparent conductive layer provided on the gate insulating film of the thin film transistor section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1235304A JPH0397271A (en) | 1989-09-11 | 1989-09-11 | Image sensor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1235304A JPH0397271A (en) | 1989-09-11 | 1989-09-11 | Image sensor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0397271A true JPH0397271A (en) | 1991-04-23 |
Family
ID=16984134
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1235304A Pending JPH0397271A (en) | 1989-09-11 | 1989-09-11 | Image sensor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0397271A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5525527A (en) * | 1992-02-20 | 1996-06-11 | Minnesota Mining And Manufacturing Company | Process for producing a solid state radiation detector |
US6020581A (en) * | 1998-02-24 | 2000-02-01 | International Business Machines Corporation | Solid state CMOS imager using silicon-on-insulator or bulk silicon |
US20180258834A1 (en) * | 2015-12-21 | 2018-09-13 | Mitsubishi Heavy Industries Engine & Turbocharger Ltd. | Precombustion-chamber engine |
-
1989
- 1989-09-11 JP JP1235304A patent/JPH0397271A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5525527A (en) * | 1992-02-20 | 1996-06-11 | Minnesota Mining And Manufacturing Company | Process for producing a solid state radiation detector |
US5818053A (en) * | 1992-02-20 | 1998-10-06 | Imation Corp. | Multi-module solid state radiation detector with continuous photoconductor layer and fabrication method |
US5942756A (en) * | 1992-02-20 | 1999-08-24 | Imation Corp. | Radiation detector and fabrication method |
US6262421B1 (en) | 1992-02-20 | 2001-07-17 | Imation Corp. | Solid state radiation detector for x-ray imaging |
US6020581A (en) * | 1998-02-24 | 2000-02-01 | International Business Machines Corporation | Solid state CMOS imager using silicon-on-insulator or bulk silicon |
US20180258834A1 (en) * | 2015-12-21 | 2018-09-13 | Mitsubishi Heavy Industries Engine & Turbocharger Ltd. | Precombustion-chamber engine |
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