JPH05173184A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To improve the formation efficiency of a trench formed on a driving substrate of an active matrix type liquid crystal display device, and also, to taper the trench. CONSTITUTION:The liquid crystal display device is constituted of a pair of substrates 1 and 2 and a liquid crystal layer 3 inserted and held between both of them. On the surface of the driving substrate 1, a picture element electrode 5 arrayed like a matrix, a thin film transistor 6 connected to this picture element electrode 5, and an addition capacity 7 for holding charge through the thin film transistor 6 are formed. This driving substrate 1 has a laminated structure consisting of an insulating base material 8 consisting of quartz, etc., and a transparent insulating film 9 consisting of silicon nitride, etc., formed on this insulating base material. The thin film transistor 6 is formed along a groove part 10, whose side face is tapered, formed to the laminated structure of the insulating base material 8 and the transparent insulating film 9. The transparent insulating film 9 has a etching rate higher than that of the insulating base material 8 and the groove part 10 can be formed at a high speed, and also, it can be tapered simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device. More specifically, the present invention relates to a trench structure of a driving substrate in which a pixel electrode, a thin film transistor, an additional capacitor and the like are formed.

[0002]

2. Description of the Related Art FIG. 10 shows an equivalent circuit of a general active matrix type liquid crystal display device. At the intersection of m gate lines (G1, G2 ... Gm) and n source lines (S1, S2 ... Sn) arranged orthogonal to each other, a thin film transistor 101 (MOS-FET) and a charge storage capacitor as an additional capacitance. 102, a liquid crystal cell 103 that constitutes a pixel
Are formed. The liquid crystal display device having such a configuration is driven in a dot-sequential manner, for example. That is, the gate lines G1 and G2
A scanning signal whose pulse width is set to one horizontal scanning cycle is sequentially applied to Gm. During the period when one gate line is selected, the sampled display signal is the source line S
1, S2 ... Sn are sequentially held. Immediately after that, the display signal is written through the transistor 101 corresponding to each pixel. The display signal written in the pixel is held for one field period by the liquid crystal cell 103 and the capacitor 102, and is rewritten to a signal of opposite polarity in the next field. As a result, the liquid crystal is AC driven.

The larger the pixel capacity of the liquid crystal cell 103, the more reliably the sampling and holding of the display signal can be performed, so that the display contrast unevenness is less likely to occur and the image quality is improved. However, in the case of a small-sized display device, if pixels are made finer or finer, the pixel electrode area becomes, for example, 100 μm square or less, and sufficient pixel capacitance cannot be obtained. Therefore, generally, the additional capacitance is connected in parallel to the pixel. In the case of high-definition pixels, the additional capacity usually needs to be about 5 times the pixel capacity. If such a capacitance is formed in a plane, there is a drawback that the occupation ratio on the screen becomes high and the effective aperture ratio of pixels (the ratio of the pixel electrode occupying the screen) decreases. In view of this point, a conventional example using a so-called trench type additional capacitance is disclosed in, for example, Japanese Patent Laid-Open No. 64-81262. This conventional example will be briefly described with reference to FIG. A groove or trench 105 is formed on the surface of the insulating substrate 104. The first electrode 106, the dielectric film 107, and the second electrode 108 are sequentially arranged along the inner wall thereof.
Are formed. The trench-type additional capacitance 109 thus obtained can have a large electrode area as compared with the plane area thereof, and thus is small and has a large capacitance. On the other hand, the pixel driving transistor 110 is formed using the semiconductor thin film 111. That is, the gate insulating film 11 is formed on the semiconductor thin film 111.
The gate electrode 114 is patterned through 2, 113, so that a so-called field effect type thin film MOS transistor can be obtained. The pixel electrode 116 is connected to the drain region of the transistor 110 via the first interlayer insulating film 115, and the source line 117 is electrically connected to the source region of the transistor 110 via the interlayer insulating film 115. .. A passivation film 118 is coated so as to protect these laminated structures.

[0004]

Problems to be solved by the invention will be briefly described with reference to FIG. In the above-mentioned conventional example, the trench is formed in the insulating substrate made of quartz or the like. The trench formation is generally performed by using plasma etching or the like. As shown in the upper part of FIG. 12, a patterned resist 119 is formed on the surface of the insulating substrate 104 made of quartz. Next, FIG.
As shown in the lower side of the figure, reactive plasma is irradiated through the opening 120 provided in the resist 119 to remove the quartz. Generally, the trench 105 is used to form additional capacitance.
Requires a depth of about 3 μm. However, a large selection ratio between the insulating substrate 104 and the resist 119 in the etching process (ratio of the etching rate of the resist 119 to the etching rate of the insulating substrate 104 made of quartz) cannot be secured. While quartz that forms the insulating substrate 104 has a dense structure, the organic material that forms the resist 119 cannot withstand the etching process for a long time. For example, the resist 119 disappears when a trench is dug up to about 1 μm in the substrate 104. Therefore, the resist formation and etching must be repeated until the target trench depth of 3 μm is obtained, which causes a problem of poor production efficiency.

Further, the conventional trench 105 has a substantially vertical inner wall. For this reason, when a semiconductor film or an electrode film is deposited along the inner wall, step coverage is poor, which causes a failure such as step breakage.

[0006]

SUMMARY OF THE INVENTION In view of the above-mentioned problems or problems of the conventional technique, an object of the present invention is to improve the production efficiency of trench formation. At the same time, it is an object to provide a trench shape with good step coverage. Means taken to achieve such an object will be described with reference to FIG. The liquid crystal display device according to the present invention comprises a pair of substrates 1 and 2 arranged to face each other, and a liquid crystal layer 3 sandwiched between the substrates. A counter electrode 4 is formed on the entire inner surface of the upper substrate 2. On the other hand, on the lower drive substrate 1, the pixel electrodes 5 arranged in a matrix are formed.
And a thin film transistor 6 connected to this pixel electrode,
An additional capacitor 7 for holding electric charge is formed via the thin film transistor.

The driving substrate 1 has a laminated structure including a transparent insulating base material 8 made of quartz or the like and a transparent insulating film 9 made of silicon nitride or the like formed on the base material. The thin film transistor 6 includes a semiconductor layer 11 formed along a groove portion 10 having a tapered side surface formed in a laminated structure of the insulating base material 8 and the transparent insulating film 9, and a gate insulation formed on the semiconductor layer. A film 12 and a gate electrode 1 formed on the gate insulating film and arranged so as to fill the groove 10.
3 and 3. A source line 15 is connected to the source region S of the thin film transistor 6 via the first interlayer insulating film 14. On top of this, the second interlayer insulating film 1
6 are deposited. The pixel electrode 5 is electrically connected to the drain region D of the thin film transistor 6 via the first interlayer insulating film 14.

On the other hand, the additional capacitor 7 is provided via a dielectric film 19 and a first electrode 18 formed along the inner wall of another groove 17 formed in the driving substrate 1 at the same time as the groove 10 described above. The second electrode 20 is formed. Preferably, the first electrode 18 is formed of the same material as the semiconductor layer 11, and for example, first polysilicon is used. or,
The dielectric film 19 is also made of the same material as the gate insulating film 12. Further, the second electrode 20 is formed of the same material as the gate electrode 13, and for example, a second polysilicon deposited film is used.

In FIG. 1, both the thin film transistor 6 and the additional capacitor 7 have a trench structure. However, the present invention is not limited to this, and it is sufficient that at least one element has a trench structure. In particular,
Unlike the conventional example, in addition to the additional capacitor 7, the thin film transistor 6
At the same time, by adopting the trench structure, the pixel aperture ratio can be further improved.

[0010]

The operation of the present invention will be described in detail with reference to FIG. FIG. 2 is a schematic cross-sectional view showing the shape and the forming process of the trench or groove portion 10. As described above, the insulating base material 8 is made of, for example, a quartz substrate. The quartz substrate is, for example, 1
Since it is manufactured at a processing temperature of about 200 ° C., it has a very fine microstructure. On the other hand, the transparent insulating film 9 is formed on the quartz substrate. This insulating film 9 is, for example, silicon nitride,
Materials such as silicon dioxide, silicon nitride, and tantalum oxide can be used. Low pressure chemical vapor deposition (LPCV
D) or using a sputtering method to deposit these materials. It is preferable to use silicon nitride because it has a gettering effect on impurities such as sodium ions contained in the quartz substrate. For example, LPCVD is used to deposit silicon nitride to a thickness of 1 to 2 μm. If the film thickness increases, cracks may occur due to internal stress, so the film thickness is preferably suppressed to about 1 μm. Since this film formation is performed at a processing temperature of about 600 ° C., it has a porous fine structure and has a higher etching rate than a quartz substrate. On the surface of the transparent insulating film 9, a resist film 21 patterned in a predetermined shape is formed. The thickness of the resist film 21 is usually 1 μm
It is set to ˜2 μm. If the thickness is larger than this, it becomes difficult to maintain the uniformity of the film thickness.

When anisotropic etching such as plasma etching is performed through the opening 22 formed in the resist film 21, the transparent insulating film 9 having a porous structure is quickly etched. Since the selection ratio of the resist film 21 to the insulating film 9 is high, the resist film 21 is not damaged during this period. In addition, even in the case of anisotropic etching, since the etching rate of the insulating film 9 is high, the wraparound of the reaction plasma occurs and the tapered shape can be easily obtained. When the plasma etching is further continued, a trench is formed on the surface of the insulating base material 8 and finally the groove portion 10 having a depth of about 3 μm is obtained. Although the taper angle of the trench formed in the insulating base material 8 is steeper than the taper angle of the trench formed in the insulating film 9, the groove portion 10 has a tapered shape as a whole.

According to the present invention, the etching process can be sped up by the amount of the transparent insulating film having a high etching rate interposed, and the resist film 21 need not be repeatedly formed. Therefore, the throughput of the trench forming process is improved. In addition, since the cross-sectional shape of the groove 10 is tapered, the step coverage is improved, disconnection failure and the like can be effectively prevented, and the yield is improved.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. 3 to 9 are process diagrams showing the manufacturing process of the pixel driving substrate of the liquid crystal display device according to the present invention. First, FIG. 3 shows a step of forming a trench and a step of forming a first polysilicon film. First, a quartz substrate 3 whose surface is covered with a transparent insulating film, for example, a silicon nitride film 30.
Prepare 1. Although a silicon nitride film is used in this example, the material is not limited to this, and a transparent insulating material such as silicon dioxide, silicon nitride, or tantalum oxide may be used. The silicon nitride film 30 is formed by LPCVD to have a film thickness of 1 μm to 2 μm. Next, a resist film 32 is patterned on the surface of the silicon nitride film 30. Plasma etching is performed through the opening formed in the resist film 32 to simultaneously form the trenches 33T and 33C having a tapered shape. The one trench 33T is for forming a thin film transistor, and the other trench 33C is for forming an additional capacitance. For plasma etching, a 95: 5 mixed gas of CF ₄ and O ₂ was selected as a reaction gas, and the gas pressure was 0.6 To.
Set to rr and set high frequency power to generate plasma to 10
The temperature was set to 00 W and the substrate temperature was set to 60 ° C. The etching rate of the silicon nitride film obtained at this time was 583 Å / min, and the etching rate of the quartz substrate 31 was 341 Å / min. The silicon nitride film 30 formed by the low pressure chemical vapor deposition had a porous structure and its etching rate was about 1.7 times that of the quartz substrate 31 having a dense structure. Therefore, the silicon nitride film 30 was quickly etched and a desired taper shape could be obtained. At this point, since the resist film 32 is hardly damaged, plasma etching is continued, and the trench 33T,
It was possible to form 33C. After forming the trench,
The unnecessary resist film 32 is ashed and removed using, for example, plasma ashing. Then, a first polysilicon film 34 is deposited on the entire surface of the substrate. This film formation is L
A PCVD method was used to obtain a film thickness of 800 Å. After that, Si ⁺ ions are implanted to once bring the polysilicon close to an amorphous state. This ion implantation was performed with an acceleration energy of 30 keV and a dose of 1 × 10 ¹⁵ / cm ² . Alternatively, the acceleration energy may be set to 50 keV and the dose may be set to 1 × 10 ¹⁵ / cm ² . After this, 620 ℃
Heat treatment or annealing is performed to cause solid phase growth of silicon crystals. By this treatment, the crystal grain size is expanded in the first polysilicon layer which has been made amorphous, and high-performance electrical characteristics close to those of a single crystal are obtained. On this occasion,
Since the trench has a tapered shape, the first polysilicon film 34 deposited on the trench is also exposed to incident ions. Therefore, there is an advantage that uniform Si ⁺ ion implantation can be performed and solid phase growth can be uniformly performed. Finally, the first polysilicon film 34 is patterned to form the semiconductor layer 35 inside the one trench 33T and form the first electrode 36 inside the other trench 33C.

Next, the step of forming the gate insulating film will be described with reference to FIG. First, the surface of the first polysilicon film 34 is thermally oxidized to form a silicon dioxide film 37 having a film thickness of about 500 angstroms. Next, after masking the portion of the one trench 33T with the resist 38, As ⁺ ions are implanted into the first electrode 36 formed in the other trench 33C to reduce its efficiency. The conditions of the ion implantation at this time were such that the acceleration energy was set to 30 keV and the dose was set to 5 × 10 ¹⁴ / cm ² . After removing the resist 38, a silicon nitride film is deposited by LPCVD to a thickness of 300 angstroms, and its surface is thermally oxidized to form a thin silicon dioxide film with a thickness of 20 angstroms. In this way, the gate insulating film 39 having a three-layer structure was obtained.
Since it has a multi-layer structure, the withstand voltage characteristic is improved.

Next, the step of forming the second polysilicon film will be described with reference to FIG. First, the second polysilicon film 40 is deposited on the entire surface of the gate insulating film 39 by the LPCVD method. The thickness at this time was, for example, 3500 angstroms. Although not shown, glass doped with phosphorus (PS) is formed on the second polysilicon film 40.
G) is deposited. A heat treatment was performed to diffuse phosphorus into the second polysilicon film to reduce the resistance. Finally, the second
The polysilicon film 40 is patterned to form one trench 33.
The gate electrode 41 buried in T and the other trench 33
The second electrode 42 embedded in C is formed. This patterning is performed by plasma etching using, for example, a mixed gas of 95: 5 CF ₄ and O ₂ as a reaction gas. As a result, the semiconductor layer 3 is formed inside the trench 33T.
5, the basic structure of the thin film transistor including the gate insulating film 34 and the gate electrode 41 can be formed. On the other hand, trench 3
Inside 3C, an additional capacitor 56 including the first electrode 36, the dielectric film 34, and the second electrode 42 is formed.

Next, the process of forming the source and drain regions of the thin film transistor will be described with reference to FIG. First,
After coating the upper portion of the trench 33T with the resist 43, As
^{Implanting +} ions to form a lightly doped drain region. The conditions for ion implantation at this time were to set the acceleration energy to 160 keV and the dose to 1
It was set to × 10 ¹³ / cm ² . The so-called LDD structure can effectively prevent the short channel effect and the like. However, in the case of this example, the LDD structure is not necessarily required because a sufficient channel length can be obtained along the inner wall portion of the trench 33T. Then, As ⁺ ions are implanted through the resist 44 having a wider mask area to form N-type source and drain regions. The condition of ion implantation at this time is that the acceleration energy is 140 keV,
The dose was 2 × 10 ¹⁵ / cm ² . As a result, an N-channel pixel driving transistor is formed in the trench 33T. In addition to the driving transistors, peripheral circuits are also formed on the substrate at the same time. Since this peripheral circuit has a CMOS structure, it is also necessary to form a P-channel type transistor. In this case, B ⁺ ions are implanted through the resist film 45. The conditions at this time are, for example, acceleration energy of 30 keV and dose of 2 × 10 ¹⁵ /
Set to cm ² . As a result, P-type source regions S and drain regions D are formed on the surface of the semiconductor film 35.

Next, the wiring process will be described with reference to FIG. First, using the LPCVD method, a first PSG
The interlayer insulating film 46 is deposited on the upper surface of the gate insulating film 39.
Subsequently, the first contact hole 47 is formed by selectively patterning the first interlayer insulating film 46 by wet etching using a mixed solution of HF and NH ₄ F. After that, a conductive film 48 of aluminum or silicon is formed by using sputtering. The film thickness is 6
000 angstroms. As a result, the conductive film 48
Is electrically connected to the source region S of the transistor 49 through the contact hole 47. Finally, H ₃ PO ₄ and H ₂
Electrode patterning of the conductive film 48 is performed by wet etching using a 2:10 mixed solution of O to form the source line 50.

Further, the hydrogen diffusion process for the first polysilicon film 34 will be described with reference to FIG. First, the first
A second interlayer insulating film 51 made of PSG is deposited on the interlayer insulating film 46 by the LPCVD method. Next, the hydrogen diffusion source 52 is formed so as to overlap the second interlayer insulating film 51. The diffusion source 52 is formed by depositing a silicon nitride film in a thickness of, for example, 4000 angstrom by using a physical chemical vapor deposition method. This silicon nitride film contains a large amount of hydrogen atoms. By performing the heat treatment, hydrogen atoms diffuse into the first polysilicon film 34 through the second interlayer insulating film 51, the first interlayer insulating film 46, the gate insulating film 39, etc., and fill the trap. As a result, the charge mobility of the first polysilicon film 34 is improved. Finally, the hydrogen diffusion source 5 is no longer needed
2 is entirely removed by plasma etching.

Finally, the process of forming the pixel electrode will be described with reference to FIG. First, the second contact hole 53 is formed by plasma etching using a 95: 5 mixed gas of CF ₄ and O ₂ or wet etching using a mixed solution of HF and NF ₄ F. Subsequently, a transparent electrode film 54 made of ITO or the like is deposited to a film thickness of 1400 angstroms by sputtering at a film forming temperature of 400 ° C.
As a result, a part of the transparent conductive film 54 is electrically connected to the drain region D of the transistor 49 through the second contact hole 53. Finally, 300 pairs of HCl and between H ₂ O and NO ₃ 3
The transparent conductive film 54 is patterned using a mixed solution of 00:50 to obtain a pixel electrode 55 having a predetermined shape and area.

[0020]

As described above, according to the present invention, an insulating film having an etching rate higher than that of a quartz substrate is deposited to form a two-layer structure to form a trench. Therefore, the etching rate is higher than in the conventional case, and the groove having a predetermined depth can be formed by one-time treatment, so that the throughput is improved. At this time, even if anisotropic etching is used, since the etching rate is relatively high, a trench having a desired taper shape is obtained, and the step coverage is improved. Therefore, it is possible to prevent a failure such as a disconnection in advance, and there is an effect that the yield rate is improved. In addition, since the polysilicon layer is deposited along the tapered surface, positive ion implantation for solid phase growth can be uniformly performed, and a semiconductor layer having excellent electric characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a basic structure of a liquid crystal display device according to the present invention.

FIG. 2 is a schematic cross-sectional view for explaining the operation of the present invention.

FIG. 3 is a process chart showing a process for forming a trench on a driving substrate of a liquid crystal display device according to the present invention.

FIG. 4 is also a process drawing showing a process of forming a gate insulating film.

FIG. 5 is also a process drawing showing a process of forming a gate electrode.

FIG. 6 is also a process drawing showing a process of forming source and drain regions.

FIG. 7 is also a process drawing showing a process of forming wiring electrodes.

FIG. 8 is likewise a process drawing showing a hydrogen diffusion treatment process for a semiconductor layer.

FIG. 9 is also a process drawing showing a process of forming a pixel electrode.

FIG. 10 is a circuit diagram showing a general equivalent circuit of an active matrix type liquid crystal display device.

FIG. 11 is a cross-sectional view showing a structural example of a conventional liquid crystal display device driving substrate.

FIG. 12 is an explanatory diagram showing a conventional trench forming step.

[Explanation of symbols]

 1 Substrate 2 Substrate 3 Liquid Crystal Layer 4 Counter Electrode 5 Pixel Electrode 6 Thin Film Transistor 7 Additional Capacitance 8 Insulating Base Material 9 Transparent Insulating Film 10 Groove Part 11 Semiconductor Layer 12 Gate Insulating Film 13 Gate Electrode 14 First Interlayer Insulating Film 15 Source Line 16 Second Interlayer insulating film 17 Groove 18 First electrode 19 Dielectric film 20 Second electrode

Claims (3)

[Claims] 1. A substrate having a counter electrode and one substrate provided with pixel electrodes arranged in a matrix, thin film transistors connected to the pixel electrodes, and an additional capacitor for holding an electric charge through the thin film transistor. In a liquid crystal display device including the other substrate opposite to the one substrate and a liquid crystal layer sandwiched between the two substrates, the one substrate is formed on an insulating base material and the insulating base material. And a gate insulating film formed on the semiconductor layer, wherein the thin film transistor includes a semiconductor layer formed along the insulating base material and a groove having a tapered side surface formed on the insulating film, and a gate insulating film formed on the semiconductor layer. A liquid crystal display device, comprising: a gate electrode formed on the gate insulating film and arranged so as to fill the groove. 2. The additional capacitance is formed of the same material as a first electrode formed along the inner wall of another groove formed on one substrate at the same time as the groove and a dielectric material formed of the same material as the gate insulating film of the thin film transistor. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device comprises a gate electrode of the thin film transistor provided through a body film and a second electrode made of the same material. 3. One substrate having pixel electrodes arranged in a matrix, thin film transistors connected to the pixel electrodes, and an additional capacitor for holding charges via the thin film transistors, and a counter electrode. In a liquid crystal display device including the other substrate opposite to the one substrate and a liquid crystal layer sandwiched between the two substrates, the one substrate is formed on an insulating base material and the insulating base material. A first electrode layer formed along an inner wall of a groove portion having a tapered side surface formed on the insulating base material and the insulating film, and the first electrode layer. A liquid crystal display device comprising: a dielectric film formed on the dielectric film; and a second electrode layer formed on the dielectric film and arranged to fill the groove.