JP2572379B2 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistorInfo
- Publication number
- JP2572379B2 JP2572379B2 JP61178888A JP17888886A JP2572379B2 JP 2572379 B2 JP2572379 B2 JP 2572379B2 JP 61178888 A JP61178888 A JP 61178888A JP 17888886 A JP17888886 A JP 17888886A JP 2572379 B2 JP2572379 B2 JP 2572379B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon layer
- layer
- polycrystalline silicon
- tft
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 title claims description 19
- 239000010409 thin film Substances 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 239000010408 film Substances 0.000 claims description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 239000001257 hydrogen Substances 0.000 claims description 10
- 229910052739 hydrogen Inorganic materials 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 9
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 66
- 108091006146 Channels Proteins 0.000 description 14
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、MOS型薄膜トランジスタに係り、特に液晶
平面デイスプレイ用アクテイブマトリツクスに用いて好
適な薄膜トランジスタの製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS thin film transistor, and more particularly to a method for manufacturing a thin film transistor suitable for use in an active matrix for a liquid crystal flat display.
液晶平面デイスプレイ用アクテイブマトリツクスに用
いつ薄膜トランジスタ（以下単にTFTという）に関する
従来技術として、「日経エレクトロニクス（1984年９月
10日号）」における小口、村田氏等による「商品化され
た液晶ポケツト・カラー・テレビ」と題する文献に開示
された技術がある。この従来技術によるTFTは、チヤネ
ル領域およびソース・ドレイン領域の全てが、多結晶シ
リコンにより形成されており、さらに、そのソース・ド
レイン層は、イオン打込み法によるドーピングによつて
形成している。As a conventional technology related to a thin film transistor (hereinafter simply referred to as a TFT) used in an active matrix for a liquid crystal flat display, Nikkei Electronics (September 1984
10th issue)), a technique disclosed in a document entitled "Commercialized liquid crystal pocket color television" by Oguchi and Murata et al. In this conventional TFT, all of the channel region and the source / drain region are formed of polycrystalline silicon, and the source / drain layers are formed by doping by ion implantation.
前記従来技術によるTFTは、半導体層を全て多結晶シ
リコンで形成しているため、その製造時におけるプロセ
ス温度を非晶質シリコンの場合に比較して高くする必要
がある。このため、多結晶シリコン中には、水素がほと
んど含まれず、ソース・ドレイン領域とチヤネル領域間
のpn接合が不完全となり、このTFTは、TFTTがオフとな
つた時のリーク電流が増加するという問題点を有してい
る。また、TFTの製造時において、pn接合形成後に新た
に水素を含ませる手段を導入することもできるが、プロ
セス数が増加するという点で、このような製造方法を取
ることは好ましくない。さらに、前記従来技術は、ソー
ス・ドレイン層の不純物ドーピング法として、イオン打
込み法を採用しているため、TFTによる液晶平面デイス
プレイ用アクテイブマトリツクス基板の大画面化、高ス
ループツト化が困難であるという問題点を有する。In the TFT according to the prior art, since the semiconductor layers are all formed of polycrystalline silicon, it is necessary to increase the process temperature at the time of its manufacture as compared with the case of amorphous silicon. For this reason, polycrystalline silicon hardly contains hydrogen, and the pn junction between the source / drain region and the channel region becomes incomplete, and this TFT increases leakage current when the TFTT is turned off. Has problems. In the manufacture of the TFT, a means for newly adding hydrogen after the formation of the pn junction can be introduced, but it is not preferable to adopt such a manufacturing method in view of an increase in the number of processes. Furthermore, since the prior art employs an ion implantation method as an impurity doping method for the source / drain layers, it is difficult to increase the screen size and the throughput of the active matrix substrate for liquid crystal flat display by TFT. Has problems.
本発明の目的は、チヤネル領域の電解効果移動度が高
く、しかも、逆方向ゲート電圧印加時のリーク電流が少
ないTFTの製造方法を提供することにある。さらに、本
発明の他の目的は、大面積のTFTによる液晶平面デイス
プレイ用アクテイブマトリツクス基板をも量産性よく、
低コストで容易に製造可能とするTFTの製造方法を提供
することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a TFT having a high field effect mobility in a channel region and a small leak current when a reverse gate voltage is applied. Another object of the present invention is to provide an active matrix substrate for a liquid crystal flat display using a large area TFT with good mass productivity.
An object of the present invention is to provide a TFT manufacturing method which can be easily manufactured at low cost.
本発明によれば、前記目的は、チヤネル領域を結晶性
の良い多結晶シリコン層で形成し、次に、ソース・ドレ
イン領域を、水素を含んだ非晶質シリコンまたは微結晶
シリコンをドーピングガスを導入しながらデポジシヨン
し積層して形成することにより達成される。According to the present invention, the object is to form a channel region with a polycrystalline silicon layer having good crystallinity, and then form a source / drain region with amorphous silicon or microcrystalline silicon containing hydrogen by doping gas. This is achieved by depositing and laminating while introducing.
チヤネル領域を形成する結晶性の良い多結晶シリコン
層は、非晶質シリコンに比べて電界効果移動度を高める
作用が大きい。さらに、この多結晶シリコン層の上に形
成され、ソース・ドレイン層を形成する非晶質シリコン
層または微結晶シリコン層は、多量の水素を含んでいる
ので、この水素が多結晶シリコン層の結晶粒界の未結合
手と結合して、多結晶シリコン層との間に良好なpn接合
を形成する。このため、ゲート電圧が逆方向に印加され
たとき、このpn接合の良否によつて決まるリーク電流
は、きわめて小さなものとなる。A polycrystalline silicon layer having good crystallinity that forms a channel region has a greater effect of increasing field-effect mobility than amorphous silicon. Further, the amorphous silicon layer or the microcrystalline silicon layer which is formed on the polycrystalline silicon layer and forms the source / drain layers contains a large amount of hydrogen. It combines with the dangling bonds at the grain boundaries to form a good pn junction with the polycrystalline silicon layer. For this reason, when the gate voltage is applied in the reverse direction, the leakage current determined by the quality of the pn junction becomes extremely small.
以下、本発明による薄膜トランジスタの製造方法の一
実施例を図面について詳細に説明する。Hereinafter, an embodiment of a method of manufacturing a thin film transistor according to the present invention will be described in detail with reference to the drawings.
第１図は本発明の第１実施例により製造されたTFTの
縦断面図、第２図はその製造プロセス毎の縦断面図であ
り、両図において、１は透明絶縁基板、２は多結晶シリ
コン層、３は非晶質シリコン層、４はゲート絶縁膜、５
はゲート電極、６は層間絶縁膜、20はチヤネル領域、30
はソース層、31はドレイン層、70はソース電極、71はド
レイン電極である。FIG. 1 is a longitudinal sectional view of a TFT manufactured according to a first embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of each manufacturing process. In both figures, 1 is a transparent insulating substrate, and 2 is a polycrystalline. A silicon layer, 3 an amorphous silicon layer, 4 a gate insulating film, 5
Is a gate electrode, 6 is an interlayer insulating film, 20 is a channel region, 30
Is a source layer, 31 is a drain layer, 70 is a source electrode, and 71 is a drain electrode.
本発明により製造されたTFTは、第１図に示すよう
に、ガラス，石英等の透明絶縁基板１上に設けた、チヤ
ネル領域20を形成する結晶性のよい多結晶シリコン層２
と、該多結晶シリコン層２の上部に設けた、ソース層30
およびドレイン層31を形成する水素を含む非晶質シリコ
ン層または微結晶シリコン層３と、ソース層30とドレイ
ン層31の間に多結晶シリコン層２と接して設けたゲート
絶縁膜４と、該ゲート絶縁膜の上に設けたゲート電極５
と、ソース層30およびドレイン層31の上に設けられ、こ
れらの層30,31にのみ接触しているソース電極70および
ドレイン電極71とにより構成される。As shown in FIG. 1, a TFT manufactured according to the present invention comprises a polycrystalline silicon layer 2 having good crystallinity and forming a channel region 20 provided on a transparent insulating substrate 1 such as glass or quartz.
And a source layer 30 provided on the polycrystalline silicon layer 2.
An amorphous silicon layer or a microcrystalline silicon layer 3 containing hydrogen forming the drain layer 31 and a gate insulating film 4 provided between the source layer 30 and the drain layer 31 in contact with the polycrystalline silicon layer 2; Gate electrode 5 provided on gate insulating film
And a source electrode 70 and a drain electrode 71 provided on the source layer 30 and the drain layer 31 and in contact with only these layers 30 and 31.
次に、このTFTの製造プロセスについて、各プロセス
毎の縦断面図を示す第２図により説明する。Next, the TFT manufacturing process will be described with reference to FIG. 2 showing a longitudinal sectional view of each process.
ガラスまたは石英等の透明絶縁基板１に不純物をドー
ピングしないで、多結晶シリコン層２を減圧CVD方（基
板温度600℃）で成長させた後、フオトレジスタ膜を用
いて該シリコン層２を島状にエツチングし、その後、将
来n+層のソース・ドレインとなる非晶質シリコン層３を
プラズマCVD方（基板温度300℃）でｎ形不純物をドープ
して形成する〔第２図（ａ）〕。A polycrystalline silicon layer 2 is grown by a low pressure CVD method (substrate temperature 600 ° C.) without doping impurities into a transparent insulating substrate 1 such as glass or quartz, and then the silicon layer 2 is formed into an island shape using a photo resister film. Then, an amorphous silicon layer 3 which will be the source / drain of the n + layer in the future is formed by doping an n-type impurity by a plasma CVD method (substrate temperature 300 ° C.) (FIG. 2 (a)). .
次に、チヤネル領域20となる箇所の非晶質シリコン層
３をドライエツチング法で除去し、同時にソース層30,
ドレイン層31をパターンニングする〔第２図（ｂ）〕。Next, the portion of the amorphous silicon layer 3 that will become the channel region 20 is removed by dry etching, and at the same time, the source layer 30 and the source layer 30 are removed.
The drain layer 31 is patterned [FIG. 2 (b)].
次いで、将来ゲート絶縁膜４となるSiO2膜を減圧CVD
法，プラズマCVD法あるいは高CVD法等の低温酸化膜形成
法で形成した後、ゲート電極となる多結晶シリコン層５
を高不純物濃度に堆積し、フオトレジスト膜をマスクと
してドライエツチング法により、ゲート領域以外を除去
する〔第２図（ｃ）〕。Then, reduced pressure CVD and S i O 2 film serving as the future gate insulating film 4
Polycrystalline silicon layer 5 to be a gate electrode after being formed by a low temperature oxide film forming method such as a plasma CVD method or a high CVD method.
Is deposited at a high impurity concentration, and the portions other than the gate region are removed by dry etching using the photoresist film as a mask [FIG. 2 (c)].
次に、層間絶縁膜６として、PSG膜あるいはSiO2膜６
を全面にデポジシヨンした後、配線のためのスルーホー
ルを開ける〔第２図（ｄ）〕。Next, as an interlayer insulating film 6, PSG film or S i O 2 film 6
Is deposited on the entire surface, and through holes for wiring are opened (FIG. 2 (d)).
配線用金属として、例えばAl−２％Siをスパツタリン
グ法で形成した後、ソース電極70およびドレイン電極71
のパターンを形成する〔第２図（ｅ）〕。As the wiring metal, for example, after the Al-2% S i is formed by Supatsutaringu method, the source electrode 70 and drain electrode 71
[FIG. 2 (e)].
前述した本発明の第１実施例によるTFTは、チヤネル
領域を形成する層に結晶性のよい多結晶シリコンを用い
ているので、電界効果移動度が大きく、また、水素を含
んだ非晶質シリコンを用いて、ソース・ドレイン層を形
成するため、この層を積層する工程中に、水素が前記多
結晶シリコン層の結晶粒界に入り込み、多結晶シリコン
内の未結合手を減少させ、結果的に、ソース層30および
ドレイン層31と、ノンドープの多結晶シリコン層２との
接合特性が向上したものとなる。この接合特性の向上
は、TFTのゲード電圧が逆方向に印加されたときのリー
ク電流を少なくできるという効果を生じさせる。さら
に、この実施例のTFTの製造時のソース層およびドレイ
ン層の形成は、ドーピングガスを用いて積層して行く方
法であるため、イオン打込み法と比較して、その下にあ
る多結晶シリコン層に与える損傷が少なく、イオン打込
み法のときに損傷を除去する目的で行われるアニーリン
グ工程を省略でき、プロセスの簡略化を図ることができ
るという効果を生じる。The above-described TFT according to the first embodiment of the present invention uses polycrystalline silicon having high crystallinity for a layer forming a channel region, and thus has a large field-effect mobility and an amorphous silicon containing hydrogen. In order to form a source / drain layer using, during the step of laminating this layer, hydrogen enters the crystal grain boundaries of the polycrystalline silicon layer and reduces dangling bonds in the polycrystalline silicon, resulting in In addition, the junction characteristics between the source layer 30 and the drain layer 31 and the non-doped polycrystalline silicon layer 2 are improved. This improvement in the junction characteristics produces an effect that the leakage current when the gate voltage of the TFT is applied in the reverse direction can be reduced. Further, since the source layer and the drain layer are formed by using a doping gas to form the source layer and the drain layer at the time of manufacturing the TFT of this embodiment, the underlying polycrystalline silicon layer is compared with the ion implantation method. And the annealing step performed for the purpose of removing the damage in the ion implantation method can be omitted, and the process can be simplified.
なお、前述の実施例において、チヤネル領域20を形成
するためのn+非晶質シリコン層３を除去する工程は、多
結晶シリコン層２が薄い場合に、精度よくこの非晶質シ
リコン層３を除去する制御が難しいと予想されるが、ド
ライエツチング法を用いた場合、そのエツチング速度
は、非晶質シリコンが多結晶シリコンに比較して約２倍
〜４倍速く行われ、この工程は、極めて高い精度で行う
ことが可能である。In the above-described embodiment, the step of removing the n + amorphous silicon layer 3 for forming the channel region 20 is performed when the polycrystalline silicon layer 2 is thin. Although it is expected that the removal is difficult to control, when a dry etching method is used, the etching speed of amorphous silicon is about two to four times faster than that of polycrystalline silicon. It can be performed with extremely high precision.
前述した本発明の実施例は、本発明をコプレナー型の
TFTに適用したものであるが、本発明は、TFTのもう一つ
の典型的構造である逆スタガ型のTFTに適用することも
可能である。The above-described embodiment of the present invention relates to a coplanar type of the present invention.
Although applied to a TFT, the present invention can also be applied to an inverted stagger type TFT which is another typical structure of the TFT.
第３図は、本発明を逆スタガ型のTFTに適用した第２
実施例を示す製造プロセス毎の縦断面図であり、以下こ
れについて説明する。第３図における各符号は、第１図
および第２図の場合と同じである。FIG. 3 shows a second embodiment in which the present invention is applied to an inverted stagger type TFT.
It is a longitudinal section for every manufacturing process showing an example, and this is explained below. The reference numerals in FIG. 3 are the same as those in FIGS. 1 and 2.
第３図に示す逆スタガ型のTFTは、そのゲート電極５
の位置が透明絶縁基板上にある点で、コプレナー型のTF
Tと相異する。その製造プロセスは以下の通りである。The inverted staggered TFT shown in FIG.
Is located on the transparent insulating substrate.
Different from T. The manufacturing process is as follows.
透明絶縁基板１上にCr等から成るゲート電極５をスパ
ツタリング法で堆積させた後パターンニングし、全面に
SiO2あるいはSiN膜等ゲート絶縁膜４を形成する〔第３
図（ａ）〕。The gate electrode 5 made of C r, etc. on a transparent insulating substrate 1 is patterned after depositing at Supatsutaringu method, on the entire surface
Forming an S i O 2 or S i N film such as a gate insulating film 4 Third
Figure (a)].
次に、減圧CVD法等で多結晶シリコン層２を堆積さ
せ、所定の形にパターンニングする〔第３図（ｂ）〕。Next, a polycrystalline silicon layer 2 is deposited by a low pressure CVD method or the like and patterned into a predetermined shape (FIG. 3B).
次いで、全面に将来n+層のソース30、ドレイン層31と
なる非晶質シリコン層または微結晶シリコン層をホスフ
イン（PH3）等をドーパントしながらプラズマCVD法で形
成し、パターンニングする〔第３図（ｃ）〕。Next, an amorphous silicon layer or a microcrystalline silicon layer that will become the source 30 and drain layer 31 of the n + layer in the future is formed by plasma CVD using phosphine (PH 3 ) as a dopant and patterned. FIG. 3 (c)].
その後、層間絶縁膜６としてPSG膜あるいはSiN膜を全
面にデポジシヨンした後、配線のためのスルーホールを
開ける〔第３図（ｄ）〕。Then, after Depojishiyon a PSG film or S i N film on the entire surface as an interlayer insulating film 6 is opened through holes for wiring Third diagram (d)].
最後に配線用金属として例えばAl−２％Siをスパツタ
リング法で形成後、ソース電極70およびドレイン電極71
をパターンニングして形成する〔第３図（ｅ）〕。After formation in the last Supatsutaringu method, for example Al-2% S i as a wiring metal, the source electrode 70 and drain electrode 71
Is formed by patterning [FIG. 3 (e)].
この本発明の第２実施例によれば、前述した第１実施
例と同等の効果がある他、逆スタガ型特有の効果を有す
る。この点に関して、以下第４図により説明する。According to the second embodiment of the present invention, in addition to the same effects as those of the above-described first embodiment, there are also effects peculiar to the inverted stagger type. This will be described below with reference to FIG.
第４図は、ゲート電圧印加時の本発明による第１およ
び第２の実施例のTFTの模式的な縦断面を示す図であ
り、図において、Ｓはソース端子、Ｄはドレイン端子、
Ｇはゲート端子、100はチヤネル層、710はドレイン接合
である。FIG. 4 is a diagram showing a schematic vertical cross section of a TFT of the first and second embodiments according to the present invention when a gate voltage is applied, where S is a source terminal, D is a drain terminal,
G is a gate terminal, 100 is a channel layer, and 710 is a drain junction.
第４図（ａ），（ｂ）は、夫々、コプレーナー型およ
び逆スタガ型のTFTにおいて、ゲート端子Ｇを電池−VG
により逆バイアスした場合について、チヤネル領域の状
態に着目して示している。FIGS. 4 (a) and 4 (b) show a gate terminal G and a battery-V G in a coplanar type and an inverted stagger type TFT, respectively.
, The case where the reverse bias is applied is shown focusing on the state of the channel region.
ゲートが逆バイアスされている状態では、チヤネル層
のｉ層（多結晶シリコン層）には正孔が誘起され、見か
け上ｐ形のチヤネル層100が形成される。このとき、ド
レイン側の接合710は逆バイアスされるが、（ａ）のコ
プレナー型ではこの接合710がn+p接合となり、（ｂ）の
逆スタガ型ではこの接合710がn+ip接合となる。従つ
て、（ｂ）の逆スタガ型のTFTは、この接合710にｐチヤ
ネル層とn+層との間に、低不純物濃度のｉ層が介在さて
いる分だけ、このドレイン接合710の電界が緩和され、
この接合を流れるリーク電流が（ａ）のコプレナー型TF
Tの場合より少ないという特徴を有する。When the gate is reverse-biased, holes are induced in the i-layer (polycrystalline silicon layer) of the channel layer, and an apparent p-type channel layer 100 is formed. At this time, the junction 710 on the drain side is reverse-biased. However, in the coplanar type shown in (a), this junction 710 becomes an n + p junction, and in the inverted staggered type shown in (b), this junction 710 becomes an n + ip junction. . Accordingly, the inverted staggered TFT of FIG. 3B has an electric field of the drain junction 710 corresponding to the low impurity concentration of the i-layer between the p-channel layer and the n + layer. Relaxed,
The leak current flowing through this junction is the coplanar type TF of (a).
It has the feature that it is less than the case of T.
以上説明したように、本発明によれば、ドレイン接合
を、水素によつて未結合手の少ない構造とすることがで
き、逆方向ゲート電圧印加時のリーク電流を低減した薄
膜トランジスタを製造することができる。このリーク電
流は、従来技術によるTFTに比較して約10％程度に低減
することができる。また、TFTの製造プロセス数を最小
限にすることが可能となり、TFTの製造コストの低減お
よび信頼性の向上を図ることができる。さらに、本発明
によれば、大面積のTFTによる液晶平面デイスプレイ用
アクテイブマトリツクス基板をも低コストで容易に製造
可能である。As described above, according to the present invention, it is possible to manufacture a thin film transistor in which a drain junction can have a structure with a small number of dangling bonds by hydrogen and a leakage current when a reverse gate voltage is applied is reduced. it can. This leakage current can be reduced to about 10% as compared with the conventional TFT. Further, the number of TFT manufacturing processes can be minimized, so that TFT manufacturing cost can be reduced and reliability can be improved. Further, according to the present invention, an active matrix substrate for a liquid crystal flat display using a large area TFT can be easily manufactured at low cost.
第１図は本発明の第１実施例により製造されたTFTの縦
断面図、第２図（ａ）〜（ｅ）はその製造プロセス毎の
縦断面図、第３図（ａ）〜（ｅ）は本発明の第２実施例
のTFTの製造プロセス毎の縦断面図、第４図（ａ），
（ｂ）はゲート電圧印加時の本発明の第１および第２の
実施例のTFTの模式的な縦断面図である。 １……透明絶縁基板、２……多結晶シリコン層、３……
非晶質シリコン層、４……ゲート絶縁膜、５……ゲート
電極、６……層間絶縁膜、20……チヤネル領域、30……
ソース層、31……ドレイン層、70……ソース電極、71…
…ドレイン電極。FIG. 1 is a longitudinal sectional view of a TFT manufactured according to the first embodiment of the present invention, FIGS. 2 (a) to 2 (e) are longitudinal sectional views for respective manufacturing processes, and FIGS. 3 (a) to 3 (e). 4) is a longitudinal sectional view of each TFT manufacturing process according to the second embodiment of the present invention.
(B) is a schematic longitudinal sectional view of the TFT of the first and second embodiments of the present invention when a gate voltage is applied. 1 ... transparent insulating substrate, 2 ... polycrystalline silicon layer, 3 ...
Amorphous silicon layer, 4 ... gate insulating film, 5 ... gate electrode, 6 ... interlayer insulating film, 20 ... channel region, 30 ...
Source layer, 31 drain layer, 70 source electrode, 71
... Drain electrode.
フロントページの続き (72)発明者 三村 秋男 日立市久慈町4026番地 株式会社日立製 作所日立研究所内 (72)発明者 鈴木 誉也 日立市久慈町4026番地 株式会社日立製 作所日立研究所内 (72)発明者 宮田 健治 日立市久慈町4026番地 株式会社日立製 作所日立研究所内 (56)参考文献 特開 昭58−93276（ＪＰ，Ａ) 特開 昭60−260155（ＪＰ，Ａ) 特開 昭58−219767（ＪＰ，Ａ)Continued on the front page (72) Inventor Akio Mimura 4026 Kuji-cho, Hitachi, Japan Inside Hitachi, Ltd.Hitachi, Ltd. (72) Inventor Takaya Suzuki 4026, Kuji-cho, Hitachi, Japan Inside Hitachi, Ltd.Hitachi, Ltd. 72) Inventor Kenji Miyata 4026 Kuji-cho, Hitachi City Inside Hitachi Research Laboratory, Hitachi Ltd. (56) References JP-A-58-93276 (JP, A) JP-A-60-260155 (JP, A) 58-219767 (JP, A)
Claims (2)
膜上に多結晶シリコン層を形成する工程と、前記多結晶
シリコン層を島状にエッチングする工程と、前記島状に
エッチングした多結晶シリコン層を覆うように水素を含
んだ非晶質シリコン層または微結晶シリコン層を形成す
ると共に前記多結晶シリコン層内に水素を導入する工程
と、チャネル領域となる前記多結晶シリコン層上の箇所
の前記非晶質シリコン層または微結晶シリコン層を除去
すると共にソース領域およびドレイン領域をパターンニ
ングする工程とを含むことを特徴とする薄膜トランジス
タの製造方法。A step of forming a polycrystalline silicon layer on an insulating film provided on an insulating substrate or a semiconductor substrate; a step of etching the polycrystalline silicon layer into islands; and a step of etching the polycrystalline silicon layer into islands. Forming an amorphous silicon layer or a microcrystalline silicon layer containing hydrogen so as to cover the silicon layer, and introducing hydrogen into the polycrystalline silicon layer; and forming a channel region on the polycrystalline silicon layer. Removing said amorphous silicon layer or microcrystalline silicon layer and patterning a source region and a drain region.
上の箇所の非晶質シリコン層または微結晶シリコン層を
除去する工程の後、ゲート絶縁膜およびゲート電極を形
成することを特徴とする特許請求の範囲第１項記載の薄
膜トランジスタの製造方法。2. A gate insulating film and a gate electrode are formed after a step of removing an amorphous silicon layer or a microcrystalline silicon layer at a position on a polycrystalline silicon layer to be a channel region. A method for manufacturing a thin film transistor according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61178888A JP2572379B2 (en) | 1986-07-31 | 1986-07-31 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61178888A JP2572379B2 (en) | 1986-07-31 | 1986-07-31 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6336574A JPS6336574A (en) | 1988-02-17 |
| JP2572379B2 true JP2572379B2 (en) | 1997-01-16 |
Family
ID=16056452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61178888A Expired - Fee Related JP2572379B2 (en) | 1986-07-31 | 1986-07-31 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2572379B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3685623T2 (en) * | 1985-10-04 | 1992-12-24 | Hosiden Corp | THIN FILM TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF. |
| US4994401A (en) * | 1987-01-16 | 1991-02-19 | Hosiden Electronics Co., Ltd. | Method of making a thin film transistor |
| JPH01217421A (en) * | 1988-02-26 | 1989-08-31 | Seikosha Co Ltd | Amorphous silicon thin film transistor array substrate and its production |
| DE69125886T2 (en) | 1990-05-29 | 1997-11-20 | Semiconductor Energy Lab | Thin film transistors |
| US5610737A (en) * | 1994-03-07 | 1997-03-11 | Kabushiki Kaisha Toshiba | Thin film transistor with source and drain regions having two semiconductor layers, one being fine crystalline silicon |
| KR100223591B1 (en) * | 1996-11-20 | 1999-10-15 | 윤종용 | Thin film transistors and the manufacturing method thereof |
| US20060118869A1 (en) * | 2004-12-03 | 2006-06-08 | Je-Hsiung Lan | Thin-film transistors and processes for forming the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893276A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Thin film semiconductor device |
| JPS58219767A (en) * | 1982-06-14 | 1983-12-21 | Matsushita Electric Ind Co Ltd | Manufacture of mis type transistor |
| JPS60260155A (en) * | 1984-06-06 | 1985-12-23 | Seiko Instr & Electronics Ltd | Thin film transistor |
-
1986
- 1986-07-31 JP JP61178888A patent/JP2572379B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6336574A (en) | 1988-02-17 |
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