JP2777101B2 - Transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method for manufacturing the same, and more particularly, to a method suitable for manufacturing a thin film transistor having a CMOS structure.

[0002]

2. Description of the Related Art In general, a polysilicon thin film transistor has higher electric mobility than an amorphous silicon thin film transistor and has the same process sequence as a single crystal silicon device. Is growing. In particular, since the peripheral circuits of a pixel switch element in a display can be simultaneously realized and have many advantages in terms of cost and the like, research is being actively conducted.

FIGS. 1A to 1E show a method of manufacturing a thin film transistor in the order of steps and will be described. In FIG. 1A, a predetermined region is etched after depositing polysilicon on a substrate 2 made of quartz, glass, sapphire, or the like, and the active region 4 is patterned.
In FIG. 1B, a gate insulating film 6 and polysilicon 8 are sequentially deposited on the active region 4 and then etched and patterned.
Each element region is separately formed. As a result, the active region 4 forming the source, drain and channel regions is separated into active regions 4a and 4b for each element, and the gate insulating film 6 and polysilicon 8 are also separated from the gate insulating films 6a and 6b for each element. 8a and 8b.

FIG. 1C shows a step of performing ion implantation 10 (indicated by an arrow) on an active region 4a of the active regions 4a and 4b where an N-type MOSTFT is to be formed. In this step, a source and a drain are formed by implanting N-type ions by self-alignment using the gate 8a as a mask.
Accordingly, a channel is formed. The other active region 4b is a region where a P-type MOSTFT is formed, and is covered by the photoresist 12. In FIG. 1D, the photoresist 12 is removed and the active region 4a is now covered with the photoresist 14, and ion implantation 16 (indicated by an arrow) of a P-type impurity is performed on the active region 4b. Also in this case, a source, a drain, and a channel are formed using self-alignment using the gate 8b as a mask.
A P-type MOSTFT is created.

FIG. 1E shows an N-type MOSTF in the active region 4a.
A schematic cross section of a thin film transistor circuit having a CMOS structure in which T and a P-type MOSTFT in an active region 4b have been formed is shown. Sources and drains 18 and 20 of the N-type MOSTFT are formed in the active region 4a, and sources and drains 22 and 24 of the P-type MOSTFT are formed in the active region 4b. Gate insulating films 6a and 6b and gates 8a and 8b are provided on the channel between these regions, and C
The MOSTFT is completed. Thereafter, a process of applying an insulating film to form a contact, wiring a metal or the like through the contact to form a pad, and the like need not be particularly described, and will not be described.

The polysilicon thin film CMOS transistor manufactured as described above can be formed in a planar structure unlike an amorphous silicon thin film transistor. Therefore, ion implantation can be used for forming the drain and source regions of the device. That is, since the drain and the source can be doped by the self-alignment method, the overlap capacitance between the gate, the drain and the source is small, and the deterioration of the image quality caused by the parasitic capacitance when used as a display pixel element can be minimized. There is.

[0007]

Generally, ion implantation is a step of implanting high-energy ions from the surface of a silicon wafer. The implanted ions reach a depth determined by the incident energy, the type of ions, the state of the substrate, and the like, and at that time, damage the crystal structure of silicon.
The damaged regions overlap with each other to form a defective layer over the entire surface layer of the implanted region of the wafer. To recover this, a heat treatment is performed to anneal the implanted ions to activate them as carriers in the semiconductor. Must be performed for each ion implantation step. this is,
The same applies to the case of manufacturing a thin film transistor.

The method of forming a source and a drain by ion implantation is suitable for a small display smaller than 5 inches, but has a disadvantage in that the uniformity of doping rapidly deteriorates as the screen size increases. It is said that it is not very suitable for screen displays. In order to solve this problem, ion shower doping has recently been researched and developed. However, there are many problems that need to be solved before practical use, such as additional baking of photoresist and ion diffusion in the doping process. Have problems.

Therefore, the present invention provides a manufacturing method suitable for a thin-film CMOS transistor which does not require ion implantation and an annealing step accompanying the ion implantation. Further, the present invention provides a manufacturing method suitable for a thin-film CMOS transistor which can be a simpler manufacturing process without requiring a mask for ion doping in forming a source and a drain. Further, the present invention provides a method of manufacturing a thin film transistor capable of eliminating a thin film kink (twist, defect) which may be generated by ion implantation. Further, a method for manufacturing a thin film transistor which is suitable for a display with a larger screen is provided.

[0010]

According to the present invention, a first conductive type amorphous silicon layer, a first insulating layer, a second conductive type amorphous silicon layer, and a second insulating layer are sequentially formed on a substrate. A second step of patterning the second insulating layer and the second conductive type amorphous silicon layer to form a second conductive type source and drain region and a buffer layer; A third step of patterning the insulating layer and the amorphous silicon layer of the first conductivity type to form source and drain regions and a buffer layer of the first conductivity type, and a fourth step of forming a channel layer after the third step. And a fifth step of forming a gate insulating layer and a gate electrode layer on the channel layer by the fourth step.

Alternatively, an N-type amorphous silicon layer is formed on a substrate,
A first step of stacking a first insulating film, a P-type amorphous silicon layer, and a second insulating layer; forming source and drain regions from the P-type amorphous silicon layer; A second step of forming a buffer layer from the second insulating film; forming a source and drain region from the N-type amorphous silicon layer; and forming a buffer layer on the source and drain region from the first insulating film. The third to form
Performing a fourth step of forming a channel layer after the third step, and a fifth step of forming a gate insulating layer and a gate electrode layer on the channel layer by the fourth step. A method for manufacturing a thin film transistor is provided.

Further, according to the present invention, the source and drain electrodes, the channel region connecting the source electrode and the drain electrode, and the first region formed between the upper end of the source electrode and the lower end of the channel region. First and second transistors having a buffer layer, a second buffer layer formed between an end of the drain electrode and below an end of the channel region, and a gate electrode above the channel region are provided. A featured CMOS transistor is provided.

Further, a source and drain layer formed on the substrate, a channel layer connecting between the source layer and the drain layer, and an interlayer formed between the source and drain layers and the channel layer are formed. A thin film transistor comprising: a buffer layer formed above; and a gate electrode above the channel layer. Alternatively, a gate electrode, a gate insulating layer below the gate electrode,
A first element comprising: a semiconductor layer below the gate insulating layer; a first conductivity type silicon layer having the semiconductor layer as a channel region; and a buffer layer in an overlapping portion between the semiconductor layer and the first conductivity type silicon layer. And a gate electrode, a gate insulating layer below the gate electrode, formed on the silicon layer and the insulating layer for forming the first conductivity type silicon layer and the buffer layer separated from the first element; A second element comprising: a semiconductor layer below the gate insulating layer; a second conductivity type silicon layer having the semiconductor layer as a channel region; and a buffer layer in an overlapping portion of the semiconductor layer and the second conductivity type silicon layer. And a thin film transistor characterized by having:

[0014]

2 to 6 illustrate a manufacturing method according to this embodiment in the order of steps.

In FIG. 2, first, 50
A thermal oxide film 26 having a thickness of about 0 nm (a target value of 500 nm, but of course having ± due to fineness) is grown to be a substrate. In addition, quartz, glass, sapphire, or the like can be used as the substrate. Then, an N-type amorphous silicon layer 28 is doped on the substrate. Further, on the N-type amorphous silicon layer 28, an insulating layer 3 of a nitride film or an oxide film is formed.
A 0, P-type amorphous silicon layer 32 and an insulating layer 34 similar to the insulating layer 30 are sequentially deposited and patterned.

At this time, the N-type amorphous silicon layer 28 is formed using in-situ doping. This in-situ doping step is a step in which N-type amorphous silicon is grown in a thermal atmosphere, and at the same time, a gas containing impurities is injected to perform doping. Insulating layer 30,
34 and P-type amorphous silicon 32 are formed by LPCVD (decompression C
VD) or APCVD (normal pressure CVD). These four thin film layers 28, 30, 32, 34
Have the same thickness of about 100 nm.

In FIG. 3, the insulating layer 34 and the P-type amorphous silicon 32 are etched into a predetermined pattern by using photolithography. The P-type amorphous silicon 32a, 32b patterned by this process becomes the source and drain regions of the P-type MOSTFT, and the patterned insulating layers 34a, 34b become the buffer layer.

In FIG. 4, the buffer oxide film 30 and the N-type amorphous silicon 28 are etched into a predetermined pattern by using photolithography. At this time, the portion of the P-type MOS TFT formed in the step of FIG. 3 is protected by a photoresist 37 '. Thus, the patterned N-type amorphous silicon 28a, 28b becomes the source and drain regions of the N-type MOSTFT, and the patterned insulating layers 30a, 30b become the buffer layer.

The insulating layer 30 using these two masks,
34 and amorphous silicon 28, 32, the CMO
The portion that becomes the channel region of the STFT is also etched.

In FIG. 5, after the step of FIG. 4, an amorphous silicon channel layer 42 to be a semiconductor layer for a channel region is formed by doping, and a solid phase crystallization method (SPD: Solid Phase
For example, annealing is performed at a setting of 600 ° C. for a predetermined time (for example, about 30 hours) to convert amorphous silicon into polysilicon. The formed channel layer 42
On the gate insulating layers 38 and 30n of about 100 nm.
m of gate electrode layer 40 of polysilicon or metal
Is deposited at about 550 ° C.

In FIG. 6, the gate electrode layer 40, the gate insulating layer 38, the polysilicon channel layer 42, and the buffer layers 30a, 30b, 34a, 34b are sequentially etched by using a gate mask after the step of FIG. Pattern. As a result, N-type MOSTFT and P-type MOSTFT
Can be obtained on one substrate.

After FIG. 6, 500 nm at 380 ° C. setting
Deposit a protective oxide film to form contacts by etching,
An element electrode is formed using a metal such as aluminum at about 1000 nm. After the above steps, a hydrogenation treatment with a power density of 2.5 w / cm ² and a frequency of about 13.56 MHz at a temperature of 300 ° C. and a pressure of 0.5 torr is performed to improve the electrical characteristics of the device. Good.

The element structure obtained in this manner is such that the source and drain regions 28a-28b and 32a-32b are connected by the channel layer 42, and the buffer layers 30a, 30b, 34a, 34
b.

[0024]

According to the present invention described above, the source and the drain formed by the N-type ion implantation and the P-type ion implantation and the accompanying annealing process in the prior art are replaced with the conductive layer using photolithography. Since it is formed by an etching process, the manufacturing process is much simpler. Further, since ion implantation is not used, there is no need to worry about a thin film kink phenomenon, and annealing for each ion implantation is not required. Since the conductive layer is used for the source and drain regions after the entire conductive layer is formed on the substrate surface, the uniformity of doping is excellent and the device is suitable for a large screen. In addition, the buffer layer makes it possible to suppress the parasitic capacitance generated in the source / drain region and the channel region, improve the on / off current ratio characteristics due to the uniformly diffused ions, and achieve the passivation characteristics due to the rapid hydrogenation effect. Can also be improved. Further, since the channel region and the source and drain regions are formed separately from each other, an ultrathin film of about 500 ° can be obtained.

[Brief description of the drawings]

FIG. 1 is a process chart illustrating a conventional method for manufacturing a thin film transistor.

FIG. 2 is a process chart illustrating a method of manufacturing a thin-film CMOS transistor according to the present invention.

FIG. 3 is a process chart for explaining a process following the process in FIG. 2;

FIG. 4 is a process chart for explaining a process following the process in FIG. 3;

FIG. 5 is a process chart for explaining a process following the process in FIG. 4;

FIG. 6 is a process chart for explaining a process following the process in FIG. 5;

[Explanation of symbols]

28 N-type amorphous silicon layer (first conductive type amorphous silicon layer) 30, 34 Insulating layer (buffer layer) 32 P-type amorphous silicon layer (second conductive type amorphous silicon layer) 36, 37 Photomask 38 Gate insulating layer 40 Gate electrode layer 42 Channel layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/336 H01L 29/786 H01L 21/8238 H01L 27/092

Claims (13)

(57) [Claims] A first conductivity type amorphous silicon layer on a substrate;
A first step of sequentially forming a first insulating layer, a second conductivity type amorphous silicon layer, and a second insulating layer;
Patterning the conductive type amorphous silicon layer to form a source and drain region and a buffer layer of the second conductive type, and patterning the first insulating layer and the first conductive type amorphous silicon layer. A third step of forming a source and drain region and a buffer layer of the first conductivity type, a fourth step of forming a channel layer after the third step, a gate insulating layer and a gate insulating layer on the channel layer by the fourth step. A fifth step of forming a gate electrode layer.
A method for manufacturing a transistor. 2. The method according to claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type. 3. The method according to claim 1, wherein in the first step, the first conductivity type amorphous silicon layer is formed by in-situ doping. 4. The method according to claim 1, wherein the fourth step is a step of forming a channel layer using amorphous silicon and converting the amorphous silicon into polysilicon. Production method. 5. An amorphous silicon is converted into polysilicon by annealing at 600 ° C. for about 30 hours.
The manufacturing method as described. 6. The method according to claim 1, further comprising a hydrotreating step after the fifth step. 7. The method according to claim 1, wherein the buffer layer is a nitride film or an oxide film. 8. The method according to claim 1, wherein the substrate is made of quartz, glass, or sapphire. 9. A first step of stacking an N-type amorphous silicon layer, a first insulating film, a P-type amorphous silicon layer, and a second insulating layer on a substrate, and the P-type amorphous silicon layer Forming a source and drain region from the second insulating film and forming a buffer layer on the source and drain region from the second insulating film; and forming a source and drain region from the N-type amorphous silicon layer. A third step of forming a buffer layer on the source and drain regions from the first insulating film, a fourth step of forming a channel layer after the third step, and a gate on the channel layer by the fourth step. A fifth step of forming an insulating layer and a gate electrode layer. 10. In a first step, the first and second insulating layers and the P-type amorphous silicon layer are formed by LPCVD or APCV.
The manufacturing method according to claim 9, wherein the forming is performed at D. 11. An N-type amorphous silicon layer, a first insulating layer,
The method according to claim 9, wherein the P-type amorphous silicon layer and the second insulating layer are formed with the same thickness of about 100 nm. 12. The method according to claim 9, further comprising the step of forming a contact by depositing a protective oxide film of about 500 nm at 380 ° C. after forming the gate electrode layer in the fifth step.
12. The production method according to any one of items 11 to 11. 13. The method according to claim 9, wherein, in the fifth step, the gate insulating layer is formed with a thickness of about 100 nm.