JPH05102483A - Film transistor and its manufacturing method - Google Patents
Film transistor and its manufacturing methodInfo
- Publication number
- JPH05102483A JPH05102483A JP26226391A JP26226391A JPH05102483A JP H05102483 A JPH05102483 A JP H05102483A JP 26226391 A JP26226391 A JP 26226391A JP 26226391 A JP26226391 A JP 26226391A JP H05102483 A JPH05102483 A JP H05102483A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor layer
- channel region
- source region
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、液晶表示装置のスイッ
チング素子、或はスタティックＲＡＭ（ＳＲＡＭ）のメ
モリセル内の負荷素子等に用いられる薄膜トランジスタ
（以下では、ＴＦＴと称す）及びその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter referred to as a TFT) used as a switching element of a liquid crystal display device or a load element in a memory cell of a static RAM (SRAM) and a manufacturing method thereof. ..
【０００２】[0002]
【従来の技術】上記ＴＦＴとして、図５又は図６に示す
ものが知られている。図５に示すＴＦＴは、絶縁性基板
３１の上にポリシリコンからなる半導体層３２が形成さ
れている。この半導体層３２は、３つの帯状領域に区分
され、両端部がＮ+のソース・ドレイン領域４０ａ、４
０ｂとなっており、その間がチャネル領域３９となって
いる。上記半導体層３２が形成された基板３１の上に
は、２箇所に設けたコンタクトホール３７ａ、３７ｂを
除く全面にわたりゲート絶縁膜３３が形成され、このゲ
ート絶縁膜３３の上であって、前記チャネル領域３９の
上方部分にはゲート電極３４が形成されている。2. Description of the Related Art As the above TFT, one shown in FIG. 5 or 6 is known. In the TFT shown in FIG. 5, a semiconductor layer 32 made of polysilicon is formed on an insulating substrate 31. The semiconductor layer 32 is divided into three strip-shaped regions, both ends of which are N + source / drain regions 40a and 4a.
0b and a channel region 39 between them. A gate insulating film 33 is formed on the entire surface of the substrate 31 on which the semiconductor layer 32 is formed except for the contact holes 37a and 37b provided at two locations. The gate electrode 34 is formed in the upper portion of the region 39.
【０００３】この状態の基板３１の上には、前記コンタ
クトホール３７ａ、３７ｂを除いて層間絶縁膜３６が形
成されている。コンタクトホール３７ａ、３７ｂは、層
間絶縁膜３６及び上記ゲート絶縁膜３３を貫通してい
る。層間絶縁膜３６の上には、コンタクトホール３７
ａ、３７ｂに一部充填して電極３８ａ、３８ｂが或る範
囲に形成されている。An interlayer insulating film 36 is formed on the substrate 31 in this state except the contact holes 37a and 37b. The contact holes 37a and 37b penetrate the interlayer insulating film 36 and the gate insulating film 33. A contact hole 37 is formed on the interlayer insulating film 36.
Electrodes 38a and 38b are formed in a certain range by partially filling a and 37b.
【０００４】一方、図６に示すＴＦＴは、半導体層３２
を除いて図５のものと同様に形成されており、異なって
いる半導体層３２の部分は次のようになっている。即
ち、半導体層３２のゲート電極３４と対向する中央部に
形成されたチャネル領域３９と左端部にあるＮ+のソー
ス領域４０ａとの間に、ソース領域４０ａよりも不純物
濃度が低いＮ-の低濃度ソース領域４１ａが形成され、
チャネル領域３９と右端部にあるＮ+のドレイン領域４
０ｂとの間に、ドレイン領域４０ｂよりも不純物濃度が
低いＮ-の低濃度ドレイン領域４１ｂが形成された、い
わゆるＬＤＤ構造となっている。On the other hand, the TFT shown in FIG. 6 has a semiconductor layer 32.
The semiconductor layer 32 is formed in the same manner as that of FIG. 5 except for the above, and the different portions of the semiconductor layer 32 are as follows. That is, between the N + source region 40a on the left end portion and a channel region 39 formed in a central portion facing the gate electrode 34 of the semiconductor layer 32, a lower impurity concentration than the source region 40a N - low The concentration source region 41a is formed,
The channel region 39 and the N + drain region 4 at the right end
0b, a so-called LDD structure is formed in which a low-concentration drain region 41b of N − having an impurity concentration lower than that of the drain region 40b is formed.
【０００５】ところで、ＴＦＴは、リーク電流（オフ電
流）が小さく、オン電流が大きいという特性、即ちオン
・オフ電流比が高いことが要求される。By the way, the TFT is required to have a small leak current (off current) and a large on current, that is, a high on / off current ratio.
【０００６】その理由は、液晶表示装置に用いた場合に
は、短時間に絵素電極へ電荷を充電する必要がある為に
大きなオン電流が、また充電された電荷を１フレームの
間保持する必要がある為に低いオフ電流が要求されるか
らである。また、ＳＲＡＭに用いた場合には、消費電流
を低減する為に低オフ電流が、また耐ノイズ性や耐放射
線性を良くしてメモリセルを安定化させる為に大きなオ
ン電流が要求されるからである。The reason for this is that when used in a liquid crystal display device, it is necessary to charge the pixel electrodes with electric charge in a short time, so that a large on-current is held and the charged electric charge is held for one frame. This is because a low off current is required because of the necessity. Further, when used in SRAM, a low off current is required to reduce current consumption, and a large on current is required to improve noise resistance and radiation resistance and stabilize memory cells. Is.
【０００７】上述したオン・オフ電流比を高くする手法
としては、従来、以下のように行われていた。例えば、
ポリシリコンＴＦＴの場合、オン電流の増大について
は、結晶粒径を拡大する等して結晶性を改善することに
より行っている。一方のオフ電流の低減については、図
５の半導体層３２を薄膜化してチャネル領域３９を薄く
することにより、或は図６のように半導体層３２をＬＤ
Ｄ構造とすることにより行っている。As a method for increasing the above-mentioned on / off current ratio, the following has been conventionally performed. For example,
In the case of a polysilicon TFT, the on-current is increased by increasing the crystal grain size to improve the crystallinity. On the other hand, to reduce the off current, the semiconductor layer 32 of FIG. 5 is thinned to thin the channel region 39, or the semiconductor layer 32 is LDed as shown in FIG.
This is done by adopting a D structure.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上述し
た半導体層の薄膜化やＬＤＤ構造化による場合には、オ
ン電流の低下が招来されて、高いオン・オフ比を得るこ
とが出来ないという問題があった。However, in the case where the semiconductor layer is thinned or the LDD structure is formed as described above, there is a problem that a high on / off ratio cannot be obtained due to a decrease in on-current. there were.
【０００９】即ち、前者の半導体層の薄膜化による場合
は、半導体層が薄くなることにより結晶粒径の拡大化を
余り期待できず、結晶性を改善できにくくオン電流の増
大化を余り図れないでいた。加えて、ソース・ドレイン
領域も薄くなることにより、ソース・ドレイン領域の抵
抗が増加し、ＴＦＴがオン状態の時、ソース・ドレイン
領域の抵抗で電流が制限され、オン電流が低くなってい
た。That is, in the former case where the semiconductor layer is thinned, it is difficult to expect an increase in the crystal grain size due to the thinning of the semiconductor layer, and it is difficult to improve the crystallinity, and it is difficult to increase the on-current. I was out. In addition, since the source / drain regions also become thin, the resistance of the source / drain regions increases, and when the TFT is in the on state, the current is limited by the resistance of the source / drain regions, and the on-current is low.
【００１０】一方、後者のＬＤＤ構造化による場合は、
オフ電流を低くするためには、前記Ｎ-の低濃度ソース
領域４１ａ及び低濃度ドレイン領域４１ｂの不純物濃度
を低減すること、或は両領域４１ａ及び４１ｂの長さ
（ＬＮ-）を長くすることが必要となるが、いずれの場
合もオフ電流を低くできるもののオン電流も低下し、十
分に高いオン・オフ電流比を得ることが困難であった。On the other hand, in the case of the latter LDD structuring,
In order to reduce the off current, the impurity concentration of the low concentration source region 41a and the low concentration drain region 41b of N − is reduced, or the length (LN − ) of both regions 41a and 41b is increased. However, in each case, the off-current can be reduced, but the on-current also decreases, making it difficult to obtain a sufficiently high on-off current ratio.
【００１１】また、ＬＤＤ構造化に加えて半導体層を薄
膜化する場合には、ＴＦＴ特性を左右する低濃度ソース
領域４１ａ及び低濃度ドレイン領域４１ｂの濃度制御性
が損なわれるという別の問題もあった。その理由は、イ
オン注入による拡散においては、注入すべき半導体層の
厚さに比べ、イオン注入の飛程（Ｒｐ）のバラツキの方
が大きくなってしまい、濃度制御性が損なわれるからで
ある。Further, when the semiconductor layer is thinned in addition to the LDD structure, there is another problem that the concentration controllability of the low-concentration source region 41a and the low-concentration drain region 41b, which affects the TFT characteristics, is impaired. It was The reason is that in the diffusion by ion implantation, the variation of the ion implantation range (Rp) becomes larger than the thickness of the semiconductor layer to be implanted, and the concentration controllability is impaired.
【００１２】本発明は、このような従来技術の課題を解
決すべくなされたものであり、濃度制御性が損なわれる
ことがなく、またオン電流を低下させることなくオフ電
流を低減することによりオン・オフ電流比を高めること
ができる薄膜トランジスタ及びその製造方法を提供する
ことを目的とする。The present invention has been made to solve the problems of the prior art as described above, and does not impair the concentration controllability and reduces the on-current by reducing the off-current. An object of the present invention is to provide a thin film transistor capable of increasing the off current ratio and a method for manufacturing the thin film transistor.
【００１３】[0013]
【課題を解決するための手段】本発明の薄膜トランジス
タは、絶縁性基板上に半導体層、ゲート絶縁膜及びゲー
ト電極がこの順に、又は逆の順に積層形成され、該半導
体層の３つに区分された帯状領域の中央部がチャネル領
域となっており、両側の一方がソース領域、他方がドレ
イン領域となった薄膜トランジスタにおいて、該半導体
層のソース領域及びドレイン領域の厚さがチャネル領域
の厚さよりも厚く、かつ、ソース領域及びドレイン領域
のそれぞれがチャネル領域側を低濃度不純物領域とし、
反対側を高濃度不純物領域とした２つの領域を有してお
り、そのことにより上記目的が達成される。In the thin film transistor of the present invention, a semiconductor layer, a gate insulating film and a gate electrode are laminated on an insulating substrate in this order or in the reverse order, and are divided into three semiconductor layers. In the thin film transistor in which the central portion of the strip-shaped region is the channel region, one of both sides is the source region, and the other is the drain region, the thickness of the source region and the drain region of the semiconductor layer is larger than the thickness of the channel region. Each of the source region and the drain region is thick and the channel region side is a low concentration impurity region,
It has two regions having the high-concentration impurity region on the opposite side, whereby the above object is achieved.
【００１４】また、本発明の薄膜トランジスタの製造方
法は、絶縁性基板上に半導体層、ゲート絶縁膜及びゲー
ト電極がこの順に、又は逆の順に積層形成され、該半導
体層の３つに区分された帯状領域の中央部がチャネル領
域となっており、両側の一方がソース領域、他方がドレ
イン領域となった薄膜トランジスタの製造方法におい
て、半導体層を形成する工程と、形成された半導体層の
チャネル領域のみを選択酸化する工程と、該チャネル領
域に形成された酸化膜をマスクとして不純物を低濃度で
注入し、チャネル領域の両側の半導体層部分の一方にソ
ース領域を、他方にドレイン領域を形成する工程と、該
ソース領域及び該ドレイン領域それぞれのチャネル領域
側を低濃度不純物領域として残した状態で、該低濃度不
純物領域の外側に不純物を高濃度で注入して高濃度不純
物領域を形成する工程と、を含んでおり、そのことによ
り上記目的が達成される。In the method of manufacturing a thin film transistor according to the present invention, a semiconductor layer, a gate insulating film and a gate electrode are laminated on the insulating substrate in this order or in the reverse order, and the semiconductor layer is divided into three layers. In a method of manufacturing a thin film transistor in which a central portion of a strip-shaped region is a channel region, one of both sides is a source region, and the other is a drain region, a step of forming a semiconductor layer and only a channel region of the formed semiconductor layer And a step of forming a source region in one of the semiconductor layer portions on both sides of the channel region and a drain region in the other by implanting impurities at a low concentration using the oxide film formed in the channel region as a mask And a channel region side of each of the source region and the drain region is left as a low-concentration impurity region, and is left outside the low-concentration impurity region. Things and includes a step of forming an injection to the high concentration impurity regions at high concentration, the above-described object can be achieved.
【００１５】[0015]
【作用】本発明にあっては、半導体層のチャネル領域相
当部分に酸化を施して、半導体層のソース領域及びドレ
イン領域をチャネル領域よりも厚肉となす。よって、不
純物注入が行われるソース領域及びドレイン領域が厚い
ので、濃度制御性が損なわれることがない。また、予め
半導体層を厚く形成しておくと、半導体層は良好な結晶
状態となる。また、チャネル領域の薄肉化を酸化により
行うので、半導体層全体の結晶性が損なわれない。これ
によりオン電流が大きくなる。更に、ソース領域及びド
レイン領域は厚肉のまま残されるので、ソース領域及び
ドレイン領域の抵抗は十分に低い状態となる。これによ
り、オン電流が低くなり難い。In the present invention, the portion of the semiconductor layer corresponding to the channel region is oxidized to make the source region and the drain region of the semiconductor layer thicker than the channel region. Therefore, since the source region and the drain region in which the impurity is implanted are thick, the concentration controllability is not impaired. If the semiconductor layer is formed thick in advance, the semiconductor layer will be in a good crystalline state. Moreover, since the thinning of the channel region is performed by oxidation, the crystallinity of the entire semiconductor layer is not impaired. This increases the on-current. Further, since the source region and the drain region are left thick, the resistance of the source region and the drain region is sufficiently low. This makes it difficult for the on-current to be low.
【００１６】一方、チャネル領域が薄肉となっているの
で、オフ電流は低減される。更に、オフ電流は、半導体
層がＬＤＤ構造とされることで、より低減される。この
ため、オン・オフ電流比を高くすることができる。On the other hand, since the channel region is thin, the off current is reduced. Further, the off-current is further reduced because the semiconductor layer has the LDD structure. Therefore, the on / off current ratio can be increased.
【００１７】[0017]
【実施例】以下、本発明の実施例について説明する。EXAMPLES Examples of the present invention will be described below.
【００１８】（実施例１）図１に本実施例の薄膜トラン
ジスタを示す。この薄膜トランジスタは、絶縁性基板１
の上にポリシリコンからなる半導体層２が形成されてい
る。この半導体層２は３つに区分された帯状領域を有
し、両端部の一方が厚肉のソース領域１０ａ、他方が厚
肉のドレイン電極１０ｂとなっており、その間が薄肉の
チャネル領域９となっている。更に、ソース領域１０ａ
とドレイン電極１０ｂとは、それぞれ２つの帯状領域に
分かれていて、チャネル領域９側に低濃度不純物領域１
１ａ、１１ｂが、逆の外側に高濃度不純物領域１２ａ、
１２ｂが形成されている。Example 1 FIG. 1 shows a thin film transistor of this example. This thin film transistor has an insulating substrate 1
A semiconductor layer 2 made of polysilicon is formed on the above. The semiconductor layer 2 has a strip-shaped region divided into three parts, one of both ends being a thick source region 10a and the other being a thick drain electrode 10b, and a thin channel region 9 between them. Is becoming Further, the source region 10a
The drain electrode 10b and the drain electrode 10b are each divided into two strip-shaped regions, and the low-concentration impurity region 1 is formed on the channel region 9 side.
1a and 11b are the high-concentration impurity regions 12a and
12b is formed.
【００１９】上記半導体層２が形成された基板１の上に
は、２箇所に設けたコンタクトホール７ａ、７ｂを除く
全面にわたりゲート絶縁膜３が形成され、このゲート絶
縁膜３の上であって、前記チャネル領域９の上方部分に
はゲート電極４が、チャネル領域９よりも広い範囲にわ
たり形成されている。On the substrate 1 on which the semiconductor layer 2 is formed, a gate insulating film 3 is formed over the entire surface except for the contact holes 7a and 7b provided at two places. The gate electrode 4 is formed over the channel region 9 over a wider area than the channel region 9.
【００２０】この状態の基板１の上には、前記コンタク
トホール７ａ、７ｂを除いて層間絶縁膜６が形成されて
いる。コンタクトホール７ａ、７ｂは、層間絶縁膜６及
び上記ゲート絶縁膜３を貫通している。層間絶縁膜６の
上には、コンタクトホール７ａ、７ｂに一部充填して電
極８ａ、８ｂが或る範囲に形成されている。An interlayer insulating film 6 is formed on the substrate 1 in this state except the contact holes 7a and 7b. The contact holes 7a and 7b penetrate the interlayer insulating film 6 and the gate insulating film 3. Electrodes 8a and 8b are formed in a certain range on the interlayer insulating film 6 by partially filling the contact holes 7a and 7b.
【００２１】次に、この構造の薄膜トランジスタの製造
方法を図２に基づいて説明する。先ず、図２（ａ）に示
すように、絶縁性基板１上にポリシリコンからなる半導
体層２を形成する。絶縁性基板１としては、例えば石英
やＳｉＯ2、Ｓｉ3Ｎ4等の絶縁膜で覆われたＳｉ基板を
用いた。この上の半導体層２は、例えば原料ガスとして
のＳｉ2Ｈ6（ジシラン）にＮ2を加えたものを用い、か
つ、減圧ＣＶＤ法を使用し、４７０°Ｃの温度、５０Ｐ
ａの圧力で１０００オングストロームの非晶質シリコン
を堆積した後、熱処理して多結晶化させ形成する。熱処
理は、例えば温度を６００°Ｃ、雰囲気をＮ2とした熱
処理炉の中で２４時間アニールすることにより行った。
続いて、多結晶化した半導体層２を、一般的な手法を用
いて、島状に加工する。なお、非晶質シリコンの形成に
は、プラズマＣＶＤ法やスパッタリング法を使用しても
良い。また、多結晶化はレーザーアニール法を用いても
良い。 ところで、半導体層２は、その結晶性が非晶質
シリコンの膜厚が厚い程良好であるので、厚く形成す
る。Next, a method of manufacturing a thin film transistor having this structure will be described with reference to FIG. First, as shown in FIG. 2A, a semiconductor layer 2 made of polysilicon is formed on an insulating substrate 1. As the insulating substrate 1, for example, a Si substrate covered with an insulating film of quartz, SiO 2 , Si 3 N 4 or the like was used. As the semiconductor layer 2 on this, for example, Si 2 H 6 (disilane) as a source gas to which N 2 is added is used, and the low pressure CVD method is used, and the temperature is 470 ° C. and the pressure is 50 P.
After depositing 1000 angstrom of amorphous silicon under the pressure of a, it is heat treated to be polycrystallized to form. The heat treatment was performed by annealing for 24 hours in a heat treatment furnace having a temperature of 600 ° C. and an atmosphere of N 2 .
Then, the polycrystallized semiconductor layer 2 is processed into an island shape using a general method. Note that plasma CVD or sputtering may be used for forming amorphous silicon. A laser annealing method may be used for polycrystallization. By the way, since the crystallinity of the semiconductor layer 2 is better as the film thickness of the amorphous silicon is larger, the semiconductor layer 2 is formed thicker.
【００２２】次に、図２（ｂ）に示すように半導体層２
が形成された基板１上に、シリコン酸化膜（ＳｉＯ2）
２１及びシリコン窒化膜（Ｓｉ3Ｎ4）２２をこの順に形
成する。シリコン酸化膜２１及びシリコン窒化膜２２は
各々、例えば減圧ＣＶＤ法で２１０オングストローム、
４００オングストローム堆積した。Next, as shown in FIG. 2B, the semiconductor layer 2
A silicon oxide film (SiO 2 ) is formed on the substrate 1 on which
21 and a silicon nitride film (Si 3 N 4 ) 22 are formed in this order. Each of the silicon oxide film 21 and the silicon nitride film 22 is 210 angstroms by, for example, a low pressure CVD method,
400 Å was deposited.
【００２３】次いで、上側のシリコン窒化膜２２のみに
対し前記チャネル領域９を形成すべき部分をエッチング
して除去し、その後９５０°ＣのドライＯ2（酸素）を
使用して酸化を行い、図２（ｃ）に示すように、シリコ
ン窒化膜２２で覆われていない半導体層２部分を薄肉に
してチャネル領域９を形成すると共に、そのチャネル領
域９の上方に厚肉のポリシリコン酸化膜２３を形成す
る。これにより形成されたポリシリコン酸化膜２３は、
厚みが１６００オングストローム、残ったシリコン酸化
膜２１は厚みが２００オングストロームである。この酸
化のとき、シリコン窒化膜２２は酸化を抑止するので、
半導体層２のシリコン窒化膜２２で覆われていない部分
のみ酸化されていき、薄肉のチャネル領域９を形成でき
る。Then, only the upper silicon nitride film 22 is etched to remove the portion where the channel region 9 is to be formed, and thereafter, oxidation is performed using dry O 2 (oxygen) at 950 ° C. As shown in FIG. 2C, a portion of the semiconductor layer 2 not covered with the silicon nitride film 22 is thinned to form a channel region 9, and a thick polysilicon oxide film 23 is formed above the channel region 9. Form. The polysilicon oxide film 23 thus formed is
The thickness is 1600 Å, and the remaining silicon oxide film 21 is 200 Å. At the time of this oxidation, the silicon nitride film 22 suppresses the oxidation,
Only the portion of the semiconductor layer 2 that is not covered with the silicon nitride film 22 is oxidized and the thin channel region 9 can be formed.
【００２４】次いで、図２（ｄ）に示すようにシリコン
窒化膜２２のみを、例えば熱リン酸により除去したあ
と、チャネル領域９の上に形成した上記ポリシリコン酸
化膜２３をマスクとして、例えばリン（Ｐ+）を半導体
層２にイオン注入する。イオン注入条件としては、例え
ば電圧を４０ｋｅＶとし、イオンの注入密度を２×１０
13ｃｍ-2とした。半導体層２のイオン注入された部分が
ソース領域１０ａとドレイン領域１０ｂとなる。Then, as shown in FIG. 2D, only the silicon nitride film 22 is removed by, for example, hot phosphoric acid, and then the polysilicon oxide film 23 formed on the channel region 9 is used as a mask to remove, for example, phosphorus. (P + ) is ion-implanted into the semiconductor layer 2. The ion implantation conditions are, for example, a voltage of 40 keV and an ion implantation density of 2 × 10 5.
It was set to 13 cm -2 . The ion-implanted portions of the semiconductor layer 2 become the source region 10a and the drain region 10b.
【００２５】次いで、図２（ｅ）に示すように、ポリシ
リコン酸化膜２３を有するシリコン酸化膜２１をエッチ
ング等にて除去した後、基板１の上に、例えばＳｉＯ2
からなるゲート絶縁膜３を、ＣＶＤ法により１０００オ
ングストロームの厚みに形成し、そのゲート絶縁膜３の
上であって、チャネル領域９が形成された上方部分に、
前記ソース領域１０ａとドレイン領域１０ｂそれぞれの
一部の上方を覆って、リン（Ｐ）をドープしたポリシリ
コンからなるゲート電極４を、例えば４５００オングス
トローム程度形成する。続いて、このゲート電極４をマ
スクとして、前記半導体層２にリン（Ｐ+）をイオン注
入する。イオン注入条件としては、例えば電圧を１００
ｋｅＶとし、イオンの注入密度を１×１０15ｃｍ-2とし
た。この注入により、ソース領域１０ａとドレイン領域
１０ｂそれぞれの外側部分に高濃度不純物領域１２ａ、
１２ｂが形成され、前記ゲート電極４で覆われた部分が
低濃度不純物領域１１ａ、１１ｂとして残る。更に、両
低濃度不純物領域１１ａ、１１ｂで挟まれた部分が、チ
ャネル領域９として残る。このとき、ゲート電極４の下
方には、両低濃度不純物領域１１ａ、１１ｂと、チャネ
ル領域９とが存在する。Then, as shown in FIG. 2E, the silicon oxide film 21 having the polysilicon oxide film 23 is removed by etching or the like, and then, for example, SiO 2 is formed on the substrate 1.
Is formed to a thickness of 1000 angstrom by the CVD method, and is formed on the gate insulating film 3 on the upper portion where the channel region 9 is formed.
A gate electrode 4 made of polysilicon doped with phosphorus (P) is formed to cover, for example, about 4500 angstroms so as to cover a portion of each of the source region 10a and the drain region 10b. Subsequently, phosphorus (P + ) is ion-implanted into the semiconductor layer 2 using the gate electrode 4 as a mask. As the ion implantation conditions, for example, a voltage of 100
The ion implantation density was 1 × 10 15 cm -2 . By this implantation, the high-concentration impurity regions 12a are formed in the outer portions of the source region 10a and the drain region 10b, respectively.
12b is formed, and the portions covered with the gate electrode 4 remain as the low concentration impurity regions 11a and 11b. Further, the portion sandwiched between the both low-concentration impurity regions 11a and 11b remains as the channel region 9. At this time, both the low concentration impurity regions 11a and 11b and the channel region 9 exist below the gate electrode 4.
【００２６】次いで、図１に示すように、基板１上に層
間絶縁膜６を、例えばＣＶＤ法により６０００オングス
トロームの厚みに形成した後、不純物活性化の為の熱処
理を施した。熱処理条件としては、例えば温度を９５０
°Ｃとした窒素雰囲気中で３０分間加熱することにより
行った。その後、層間絶縁膜６及びゲート絶縁膜３を貫
通し、ソース領域１０ａ及びドレイン領域１０ｂに達す
るように、２箇所にコンタクトホール７ａ、７ｂを開口
した後、Ａｌ等からなる導電材料をコンタクトホール７
ａ、７ｂに一部充填して電極８ａ、８ｂを形成した。Next, as shown in FIG. 1, an interlayer insulating film 6 having a thickness of 6000 angstroms is formed on the substrate 1 by, for example, a CVD method, and then a heat treatment for activating impurities is performed. The heat treatment condition is, for example, a temperature of 950.
It was performed by heating for 30 minutes in a nitrogen atmosphere at a temperature of ° C. After that, contact holes 7a and 7b are opened at two places so as to penetrate the interlayer insulating film 6 and the gate insulating film 3 and reach the source region 10a and the drain region 10b, and then a conductive material such as Al is used for the contact hole 7
Electrodes 8a and 8b were formed by partially filling a and 7b.
【００２７】したがって、このように構成された薄膜ト
ランジスタにおいては、半導体層２のチャネル領域９相
当部分に酸化が施されて、半導体層２のソース領域１０
ａ及びドレイン領域１０ｂがチャネル領域９よりも厚肉
となっている。よって、不純物注入が行われるソース領
域１０ａ及びドレイン領域１０ｂが厚いので、濃度制御
性が損なわれることがない。また、予め半導体層２を厚
く形成しておくと、半導体層２は良好な結晶状態とな
る。また、チャネル領域９の薄肉化を酸化により行うの
で、半導体層２全体の結晶性が損なわれない。これによ
りオン電流が大きくなる。更に、ソース領域１０ａ及び
ドレイン領域１０ｂは厚肉のまま残されるので、ソース
領域１０ａ及びドレイン領域１０ｂの抵抗は十分に低い
状態となる。これにより、オン電流が低くなり難い。Therefore, in the thin film transistor having such a structure, the portion corresponding to the channel region 9 of the semiconductor layer 2 is oxidized to form the source region 10 of the semiconductor layer 2.
The a and drain regions 10b are thicker than the channel region 9. Therefore, since the source region 10a and the drain region 10b in which the impurity is implanted are thick, the concentration controllability is not impaired. If the semiconductor layer 2 is formed thick in advance, the semiconductor layer 2 will be in a good crystalline state. Moreover, since the channel region 9 is thinned by oxidation, the crystallinity of the entire semiconductor layer 2 is not impaired. This increases the on-current. Further, since the source region 10a and the drain region 10b are left thick, the resistance of the source region 10a and the drain region 10b is sufficiently low. This makes it difficult for the on-current to be low.
【００２８】一方、チャネル領域９が薄肉となっている
ので、オフ電流は低減される。更に、オフ電流は、半導
体層２がＬＤＤ構造とされることで、より低減される。
このため、オン・オフ電流比を高くすることができる。On the other hand, since the channel region 9 is thin, the off current is reduced. Further, the off-current is further reduced because the semiconductor layer 2 has the LDD structure.
Therefore, the on / off current ratio can be increased.
【００２９】（実施例２）図３に本発明の他の実施例を
示す。本実施例は、実施例１の場合とは逆に、ゲート電
極４上にゲート絶縁膜３を介して半導体層２が設けられ
た構造としてある。かかる構造の薄膜トランジスタの製
造方法を、図４に基づいて説明する。(Embodiment 2) FIG. 3 shows another embodiment of the present invention. In contrast to the case of the first embodiment, the present embodiment has a structure in which the semiconductor layer 2 is provided on the gate electrode 4 with the gate insulating film 3 interposed therebetween. A method of manufacturing a thin film transistor having such a structure will be described with reference to FIG.
【００３０】先ず、図４（ａ）に示すように絶縁性基板
１上の所定範囲に、リンがドープされたポリシリコンか
らなるゲート電極４を形成し、ゲート電極４が形成され
た基板１上の全面にゲート絶縁膜３を形成する。ゲート
電極４の形成は、例えばリンをドープしたポリシリコン
を４５００オングストローム堆積して行い、ゲート絶縁
膜３の形成は、例えばＣＶＤ法によりＳｉＯ2を１００
０オングストローム堆積して行った。First, as shown in FIG. 4A, a gate electrode 4 made of phosphorus-doped polysilicon is formed in a predetermined area on the insulating substrate 1, and the substrate 1 on which the gate electrode 4 is formed is formed. A gate insulating film 3 is formed on the entire surface of the. The gate electrode 4 is formed by depositing, for example, phosphorus-doped polysilicon at 4500 angstroms, and the gate insulating film 3 is formed by, for example, CVD using SiO 2 of 100.
0 angstrom deposition was performed.
【００３１】次いで、図４（ｂ）に示すように基板１の
上にポリシリコンからなる半導体層２を形成する。この
半導体層２は、実施例１と同様にして形成する。即ち、
原料ガスとしてのＳｉ2Ｈ6（ジシラン）にＮ2を加えた
ものを用い、かつ、減圧ＣＶＤ法を使用し、４７０°Ｃ
の温度、５０Ｐａの圧力で１０００オングストロームの
非晶質シリコンを堆積した後、熱処理して多結晶化させ
形成する。熱処理条件としては、例えば温度を６００°
Ｃ、雰囲気をＮ2とした熱処理炉の中で２４時間アニー
ルすることにより行った。続いて、多結晶化した半導体
層２を、一般的な手法を用いて、島状に加工する。な
お、非晶質シリコンの形成には、プラズマＣＶＤ法やス
パッタリング法を使用しても良い。また、多結晶化はレ
ーザーアニール法を用いても良い。Next, as shown in FIG. 4B, a semiconductor layer 2 made of polysilicon is formed on the substrate 1. This semiconductor layer 2 is formed in the same manner as in the first embodiment. That is,
Using Si 2 H 6 (disilane) with N 2 added as a raw material gas and using a low pressure CVD method at 470 ° C.
After depositing 1000 Å of amorphous silicon at a temperature of 50 Pa and a pressure of 50 Pa, it is heat-treated to be polycrystallized and formed. As the heat treatment condition, for example, a temperature of 600 °
It was performed by annealing for 24 hours in a heat treatment furnace in which the atmosphere was C and the atmosphere was N 2 . Then, the polycrystallized semiconductor layer 2 is processed into an island shape using a general method. Note that plasma CVD or sputtering may be used for forming amorphous silicon. A laser annealing method may be used for polycrystallization.
【００３２】次いで、同図に示すように、半導体層２の
チャネル領域９相当部分を薄肉化する。この薄肉化は、
実施例１と同様に行う。即ち、半導体層２が形成された
基板１上に、シリコン酸化膜（ＳｉＯ2）２１及び図示
しないシリコン窒化膜（Ｓｉ3Ｎ4）をこの順に形成し、
上側のシリコン窒化膜のみに対してチャネル領域９を形
成すべき部分をエッチングして除去し、その後９５０°
ＣのドライＯ2（酸素）を使用して酸化を行い、シリコ
ン窒化膜で覆われていない半導体層２部分を薄肉にして
チャネル領域９を形成する。このとき、チャネル領域９
の上方には、厚肉のポリシリコン酸化膜２３が形成され
る。Then, as shown in the same figure, the portion of the semiconductor layer 2 corresponding to the channel region 9 is thinned. This thinning is
The same procedure as in Example 1 is performed. That is, a silicon oxide film (SiO 2 ) 21 and a silicon nitride film (Si 3 N 4 ) not shown are formed in this order on the substrate 1 on which the semiconductor layer 2 is formed,
The portion where the channel region 9 is to be formed is removed by etching only the upper silicon nitride film, and then 950 °
Oxidation is performed by using dry O 2 (oxygen) of C to thin the semiconductor layer 2 portion not covered with the silicon nitride film to form the channel region 9. At this time, the channel region 9
A thick polysilicon oxide film 23 is formed above.
【００３３】次いで、上側のシリコン窒化膜のみを熱リ
ン酸を用いて除去した後、上記ポリシリコン酸化膜２３
をマスクとして、半導体層２にリン（Ｐ+）をイオン注
入し、ソース領域１０ａとドレイン領域１０ｂを形成す
る。残った部分が前記チャネル領域９となる。イオン注
入条件としては、例えば電圧を４０ｋｅＶとし、イオン
の注入密度を２×１０13ｃｍ-2とした。Next, only the upper silicon nitride film is removed by using hot phosphoric acid, and then the polysilicon oxide film 23 is formed.
Using as a mask, phosphorus (P + ) is ion-implanted into the semiconductor layer 2 to form the source region 10a and the drain region 10b. The remaining portion becomes the channel region 9. The ion implantation conditions were, for example, a voltage of 40 keV and an ion implantation density of 2 × 10 13 cm −2 .
【００３４】次いで、図４（ｃ）に示すように、ポリシ
リコン酸化膜２３を有するシリコン酸化膜２１の上に、
レジスト２４をパターン形成し、このレジスト２４をマ
スクとしてリン（Ｐ+）をソース領域１０ａとドレイン
領域１０ｂにイオン注入する。イオン注入条件として
は、例えば電圧を４０ｋｅＶとし、イオンの注入密度を
１×１０15ｃｍ-2とした。これにより、ソース領域１０
ａとドレイン領域１０ｂの外側部分に高濃度不純物領域
１２ａ、１２ｂが形成される。ソース領域１０ａ及びド
レイン領域１０ｂのレジスト２４にて覆われた部分に
は、低濃度不純物領域１１ａ、１１ｂが残る。更に、両
低濃度不純物領域１１ａ、１１ｂで挟まれた部分にはチ
ャネル領域９が残る。このとき、ゲート電極４の上方
に、両低濃度不純物領域１１ａ、１１ｂと、チャネル領
域９とが存在するようになすと共に、レジスト２４を形
成する。Next, as shown in FIG. 4C, on the silicon oxide film 21 having the polysilicon oxide film 23,
The resist 24 is patterned, and phosphorus (P + ) is ion-implanted into the source region 10a and the drain region 10b using the resist 24 as a mask. The ion implantation conditions are, for example, a voltage of 40 keV and an ion implantation density of 1 × 10 15 cm -2 . Thereby, the source region 10
High-concentration impurity regions 12a and 12b are formed on the outer side of a and the drain region 10b. The low-concentration impurity regions 11a and 11b remain in the portions of the source region 10a and the drain region 10b covered with the resist 24. Further, the channel region 9 remains in the portion sandwiched by the low concentration impurity regions 11a and 11b. At this time, both the low-concentration impurity regions 11a and 11b and the channel region 9 are formed above the gate electrode 4, and the resist 24 is formed.
【００３５】次いで、図３に示すように、レジスト２４
を除去した後、基板１上に層間絶縁膜６を形成し、その
後不純物活性化の為の熱処理を施した。熱処理条件とし
ては、例えば温度を９５０°Ｃとした窒素雰囲気中で３
０分間行った。その後、層間絶縁膜６を貫通し、ソース
領域１０ａ及びドレイン領域１０ｂに達するように、２
箇所にコンタクトホール７ａ、７ｂを開口した後、Ａｌ
等からなる導電材料をコンタクトホール７ａ、７ｂに一
部充填して電極８ａ、８ｂを形成した。Next, as shown in FIG.
After removing, the interlayer insulating film 6 was formed on the substrate 1, and then a heat treatment for activating the impurities was performed. The heat treatment condition is, for example, 3 in a nitrogen atmosphere at a temperature of 950 ° C.
It went for 0 minutes. After that, the interlayer insulating film 6 is penetrated to reach the source region 10a and the drain region 10b.
After opening contact holes 7a and 7b at the locations, Al
Electrodes 8a and 8b were formed by partially filling the contact holes 7a and 7b with a conductive material such as.
【００３６】したがって、この薄膜トランジスタにおい
ても、前同様に、濃度制御性を損なうことがなく、また
オン・オフ電流比を高くすることができる。Therefore, also in this thin film transistor, the concentration controllability is not impaired and the on / off current ratio can be increased as before.
【００３７】[0037]
【発明の効果】以上詳述したように本発明によれば、オ
ン・オフ電流比を高くすることが可能となり、液晶表示
装置に組み込まれた場合には絵素電極へ電荷を短時間で
充電でき、また充電された電荷を１フレームの間十分に
保持することができる。更に、ＳＲＡＭに組み込まれた
場合には、消費電流を低減でき、また耐ノイズ性や耐放
射線性を良くしてメモリセルを安定化できる。また、不
純物の注入が行われるソース領域及びドレイン領域が厚
いので、濃度制御性を損なうことがない。As described above in detail, according to the present invention, the on / off current ratio can be increased, and when incorporated in a liquid crystal display device, the pixel electrodes are charged with electric charges in a short time. In addition, the charged electric charge can be sufficiently retained for one frame. Further, when incorporated in an SRAM, it is possible to reduce current consumption, improve noise resistance and radiation resistance, and stabilize the memory cell. Further, since the source region and the drain region where the impurities are implanted are thick, the concentration controllability is not impaired.
【図１】本実施例の薄膜トランジスタを示す断面図であ
る。FIG. 1 is a cross-sectional view showing a thin film transistor of this example.
【図２】その薄膜トランジスタの製造プロセスを示す工
程図（断面図）である。FIG. 2 is a process drawing (cross-sectional view) showing a manufacturing process of the thin film transistor.
【図３】本発明の他の実施例を示す断面図である。FIG. 3 is a sectional view showing another embodiment of the present invention.
【図４】他の実施例に係る薄膜トランジスタの製造プロ
セスを示す工程図（断面図）である。FIG. 4 is a process drawing (cross-sectional view) showing a manufacturing process of a thin film transistor according to another embodiment.
【図５】従来の薄膜トランジスタを示す断面図である。FIG. 5 is a cross-sectional view showing a conventional thin film transistor.
【図６】従来の他の薄膜トランジスタを示す断面図であ
る。FIG. 6 is a cross-sectional view showing another conventional thin film transistor.
１ 基板 ２ 半導体層 ３ ゲート絶縁膜 ４ ゲート電極 ６ 層間絶縁膜 ７ａ、７ｂ コンタクトホール ８ａ、８ｂ 電極 ９ チャネル領域 １０ａ ソース領域 １０ｂ ドレイン領域 １１ａ、１１ｂ 低濃度不純物領域 １２ａ、１２ｂ 高濃度不純物領域 ２１ シリコン酸化膜 ２２ シリコン窒化膜 ２３ ポリシリコン酸化膜 ２４ レジスト 1 substrate 2 semiconductor layer 3 gate insulating film 4 gate electrode 6 interlayer insulating film 7a, 7b contact hole 8a, 8b electrode 9 channel region 10a source region 10b drain region 11a, 11b low concentration impurity region 12a, 12b high concentration impurity region 21 silicon Oxide film 22 Silicon nitride film 23 Polysilicon oxide film 24 Resist
Claims (2)
及びゲート電極がこの順に、又は逆の順に積層形成さ
れ、該半導体層の３つに区分された帯状領域の中央部が
チャネル領域となっており、両側の一方がソース領域、
他方がドレイン領域となった薄膜トランジスタにおい
て、 該半導体層のソース領域及びドレイン領域の厚さがチャ
ネル領域の厚さよりも厚く、かつ、ソース領域及びドレ
イン領域のそれぞれがチャネル領域側を低濃度不純物領
域とし、反対側を高濃度不純物領域とした２つの領域を
有する薄膜トランジスタ。1. A semiconductor layer, a gate insulating film, and a gate electrode are laminated on an insulating substrate in this order or in the reverse order, and a central portion of a band-shaped region divided into three parts of the semiconductor layer serves as a channel region. And one of the two sides is the source region,
In a thin film transistor in which the other is a drain region, the thickness of the source region and the drain region of the semiconductor layer is thicker than the thickness of the channel region, and each of the source region and the drain region has a low concentration impurity region on the channel region side. , A thin film transistor having two regions with the opposite side having a high concentration impurity region.
及びゲート電極がこの順に、又は逆の順に積層形成さ
れ、該半導体層の３つに区分された帯状領域の中央部が
チャネル領域となっており、両側の一方がソース領域、
他方がドレイン領域となった薄膜トランジスタの製造方
法において、 半導体層を形成する工程と、 形成された半導体層のチャネル領域のみを選択酸化する
工程と、 該チャネル領域に形成された酸化膜をマスクとして不純
物を低濃度で注入し、チャネル領域の両側の半導体層部
分の一方にソース領域を、他方にドレイン領域を形成す
る工程と、 該ソース領域及び該ドレイン領域それぞれのチャネル領
域側を低濃度不純物領域として残した状態で、該低濃度
不純物領域の外側に不純物を高濃度で注入して高濃度不
純物領域を形成する工程と、 を含む薄膜トランジスタの製造方法。2. A semiconductor layer, a gate insulating film, and a gate electrode are laminated on the insulating substrate in this order or in the reverse order, and a central portion of the strip-shaped region divided into three of the semiconductor layer serves as a channel region. And one of the two sides is the source region,
In a method of manufacturing a thin film transistor in which the other is a drain region, a step of forming a semiconductor layer, a step of selectively oxidizing only a channel region of the formed semiconductor layer, and an impurity film using the oxide film formed in the channel region as a mask At a low concentration to form a source region in one of the semiconductor layer portions on both sides of the channel region and a drain region in the other, and a channel region side of each of the source region and the drain region is used as a low concentration impurity region. A method of manufacturing a thin film transistor, comprising: a step of implanting an impurity at a high concentration outside the low-concentration impurity region to form a high-concentration impurity region in the state of being left.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26226391A JP2731056B2 (en) | 1991-10-09 | 1991-10-09 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26226391A JP2731056B2 (en) | 1991-10-09 | 1991-10-09 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102483A true JPH05102483A (en) | 1993-04-23 |
| JP2731056B2 JP2731056B2 (en) | 1998-03-25 |
Family
ID=17373357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26226391A Expired - Fee Related JP2731056B2 (en) | 1991-10-09 | 1991-10-09 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2731056B2 (en) |
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