JPH04313272A - Manufacture of thin-film transistor - Google Patents

Manufacture of thin-film transistor

Info

Publication number
JPH04313272A
JPH04313272A JP7925691A JP7925691A JPH04313272A JP H04313272 A JPH04313272 A JP H04313272A JP 7925691 A JP7925691 A JP 7925691A JP 7925691 A JP7925691 A JP 7925691A JP H04313272 A JPH04313272 A JP H04313272A
Authority
JP
Japan
Prior art keywords
film
thin film
silicon
film transistor
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7925691A
Other languages
Japanese (ja)
Inventor
Masatoshi Yazaki
矢▲崎▼ 正俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP7925691A priority Critical patent/JPH04313272A/en
Publication of JPH04313272A publication Critical patent/JPH04313272A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a thin-film transistor with improved electrical characteristics, a wide operation temperature, and a high yield by performing selective oxidation of a semiconductor layer which becomes an activation layer for forming a specific film thickness. CONSTITUTION:A silicon film 2 is laminated on an insulation substrate 1 and an area other than a surface of a silicon oxide film 2 for performing selective oxidation is covered with a nitriding silicon film 4 and is oxidized locally, thus enabling a silicon dioxide film 5 to be formed. When performing this local and selective oxidation, a silicon atom within the silicon film 2 is realigned and the silicon film 2 changes into a polycrystalline film 3. After removing a silicon dioxide film 5 and a nitriding silicon film 4, the polycrystalline silicon film 3 is oxidized for constituting a gate insulation film 7 and then the polycrystalline film 3 is converted into a polycrystalline silicon film 6 at the time of this oxidation. A source region and a drain region of a thin-film transistor and a channel region which becomes an activation layer are formed at the polycrystalline silicon film 6 which is formed by this oxidation. Then, a film thickness of a region which becomes an activated layer is set to 200Angstrom to 700Angstrom .

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、多結晶シリコン薄膜ト
ランジスタの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing polycrystalline silicon thin film transistors.

【0002】0002

【従来の技術】従来の多結晶シリコン薄膜トランジスタ
の製造方法としては特開昭63−119269に記載さ
れた例が知られている。図7(a)〜図7(c)に従来
例の実施例を示す工程順断面図を示す。以下図面にもと
づき詳しく説明する。
2. Description of the Related Art As a conventional method for manufacturing polycrystalline silicon thin film transistors, an example described in Japanese Patent Application Laid-open No. 119269/1983 is known. FIGS. 7(a) to 7(c) are process-order sectional views showing a conventional example. A detailed explanation will be given below based on the drawings.

【0003】まず、図7(a)に示したように石英基板
21などの絶縁体基板上もしくは絶縁膜上に多結晶状の
シリコン薄膜を島状に構成した後、ゲート絶縁膜24お
よびゲート電極12を構成し不純物イオンをシリコン薄
膜22の一部に打ち込んで、ソース電極領域9とドレイ
ン電極領域10を形成する。その後、図7(b)に示し
たように層間絶縁膜23とアルミ配線11を形成した後
、水素イオン20を薄膜トランジスタの表面に照射する
。さらに図7(c)に示したように窒化シリコン膜など
の保護膜13を堆積して多結晶シリコン薄膜トランジス
タが完成する。なお特開昭63−119270に記載さ
れた例でも知られているように、水素イオンの照射は図
7(c)の保護膜13が形成された後でも良く、その場
合には、薄膜トランジスタやアルミ配線11への水素イ
オン照射によるダメージが防がれるという利点があった
First, as shown in FIG. 7A, a polycrystalline silicon thin film is formed into an island shape on an insulating substrate such as a quartz substrate 21 or an insulating film, and then a gate insulating film 24 and a gate electrode are formed. Impurity ions are implanted into a part of the silicon thin film 22 to form a source electrode region 9 and a drain electrode region 10. Thereafter, as shown in FIG. 7B, after forming an interlayer insulating film 23 and aluminum wiring 11, hydrogen ions 20 are irradiated onto the surface of the thin film transistor. Furthermore, as shown in FIG. 7C, a protective film 13 such as a silicon nitride film is deposited to complete a polycrystalline silicon thin film transistor. As is known from the example described in JP-A-63-119270, hydrogen ion irradiation may be performed after the protective film 13 shown in FIG. 7(c) is formed. This has the advantage that damage to the wiring 11 due to hydrogen ion irradiation can be prevented.

【0004】0004

【発明が解決しようとする課題】しかしながら、上記の
従来の技術では、薄膜トランジスタの活性層とソース電
極領域9およびドレイン電極領域10が同一のシリコン
薄膜22によって形成されているため、特性に大きな影
響を与えるシリコン薄膜の膜厚を最適化しにくいという
問題点を有している。実際、アルミ配線11とソース電
極領域9の接触面およびアルミ配線11とドレイン電極
領域10の接触面において形成されるコンタクト抵抗や
ソース・ドレイン両電極領域自体が有するシート抵抗は
、ソース電極領域9とドレイン電極領域10のシリコン
薄膜の膜厚が厚いほど小さく、それが薄いほど大きくな
ることがわかっている。一般に不純物濃度が一定ならば
ソース電極領域9とドレイン電極領域10のシート抵抗
は、その両電極領域を構成するシリコン膜厚に逆比例す
る関係にあることが知られている。このためソース電極
領域9とドレイン電極領域10を構成するシリコン薄膜
の膜厚が数百Å程度の場合には、これらコンタクト抵抗
とシート抵抗の合計が数キロオームから数十キロオーム
におよび、薄膜トランジスタの高電流領域の電気的特性
を悪化させる原因となっていた。ところが、飽和領域と
よばれる低電圧印加時の薄膜トランジスタの電気特性の
向上のためには、活性層となるシリコン薄膜の膜厚を2
00Åから700Åに設定することが望ましい。これは
、活性層が膜厚の場合に比べ薄膜化された場合、ゲート
絶縁膜と活性層の界面から基板側へ伸びる活性層内の最
大空乏層幅が小さく抑えられ、キャリヤの流れる反転層
が相対的に低電圧下で構成されやすくなるためであると
考えられる。これらのことから、飽和領域の電気特性を
向上させるためにはシリコン薄膜の膜厚を数百Å以下に
抑えるのが良く、他方において高電流状態の電気特性を
向上させるためには、膜厚をより厚くするほうが良いと
いうことがわかる。このため、ソース領域とドレイン領
域の両領域を構成するシリコン薄膜と活性層を構成する
シリコン薄膜のそれぞれの膜厚をかえるのが望ましいが
、仮にそれらを別々に構成するとした場合には、今度は
ソース・ドレイン両電極領域と活性層の接触界面におけ
る欠陥や汚染物質などによるコンタクト抵抗の増加や両
電極領域と活性層との位置合わせのための余分な領域の
確保が必要となるなどといった種々の新たな問題を生ず
ることになる。また、数十キロオーム以下にコンタクト
抵抗を低く制御するためには、シリコン薄膜の活性層の
厚さを数百Å以下にするのは困難なために、電気特性の
改善を目的とする水素イオンの照射も長時間行わなけれ
ば効果があがらないという問題点も有している。これは
水素イオンを照射することにより多結晶シリコン薄膜ト
ランジスタの電気特性が向上する主な原因が、照射され
た水素イオンが不対電子からなるダングリング・ボンド
を終端化し伝導キャリヤに対する障壁を小さくする効果
があることによっている。このため、活性層となるシリ
コン薄膜の厚さが数百Åと厚いと、シリコン薄膜中に含
まれる格子欠陥や結晶境界における不対電子の数が多く
なり、それらを終端化するのに多量の水素イオンを注入
しなければならないからである。しかも、数百Åほどの
膜厚を有するシリコン薄膜に注入された水素イオンの多
くは、シリコン薄膜のゲート絶縁膜側界面から数十Åか
ら数百Åぐらいの領域に集中的に存在し、シリコン薄膜
の基板側界面までは達しない。このため、シリコン薄膜
中に存在する他の不対電子が終端化されることなくトラ
ップ準位を形成したり、キャリヤの散乱をおこし、薄膜
トランジスタの電気特性を十分向上させることもできな
いという問題点も有している。
However, in the above conventional technique, the active layer, source electrode region 9, and drain electrode region 10 of the thin film transistor are formed of the same silicon thin film 22, which has a large effect on the characteristics. The problem is that it is difficult to optimize the thickness of the silicon thin film provided. In fact, the contact resistance formed at the contact surface between the aluminum wiring 11 and the source electrode region 9 and the contact surface between the aluminum wiring 11 and the drain electrode region 10 and the sheet resistance of both the source and drain electrode regions themselves are different from that of the source electrode region 9. It has been found that the thicker the silicon thin film of the drain electrode region 10 is, the smaller it is, and the thinner it is, the larger it is. Generally, it is known that if the impurity concentration is constant, the sheet resistance of the source electrode region 9 and the drain electrode region 10 is inversely proportional to the thickness of the silicon film forming both electrode regions. Therefore, when the thickness of the silicon thin film constituting the source electrode region 9 and the drain electrode region 10 is about several hundred Å, the total of these contact resistances and sheet resistances ranges from several kilohms to several tens of kilohms. This caused deterioration of electrical characteristics in the current region. However, in order to improve the electrical characteristics of thin film transistors when a low voltage is applied, which is called the saturation region, it is necessary to increase the thickness of the silicon thin film that will become the active layer by 2.
It is desirable to set the thickness between 00 Å and 700 Å. This is because when the active layer is made thinner than when it is thick, the maximum depletion layer width in the active layer extending from the interface between the gate insulating film and the active layer to the substrate side is suppressed, and the inversion layer where carriers flow is reduced. This is thought to be because it is easier to configure under relatively low voltage. For these reasons, in order to improve the electrical properties in the saturation region, it is best to keep the thickness of the silicon thin film to a few hundred Å or less, and on the other hand, in order to improve the electrical properties in the high current state, the film thickness should be increased. It turns out that the thicker it is, the better. For this reason, it is desirable to change the film thicknesses of the silicon thin films that make up both the source and drain regions and the silicon thin film that makes up the active layer, but if they were to be formed separately, There are various problems such as an increase in contact resistance due to defects and contaminants at the contact interface between the source and drain electrode regions and the active layer, and the need to secure extra area for alignment between the source and drain electrode regions and the active layer. This will create new problems. In addition, in order to control contact resistance to a low level of several tens of kilohms or less, it is difficult to reduce the thickness of the active layer of a silicon thin film to a few hundred Å or less, so hydrogen ions are used to improve electrical characteristics. Another problem is that the irradiation is not effective unless it is carried out for a long period of time. The main reason why the electrical characteristics of polycrystalline silicon thin film transistors improve by irradiation with hydrogen ions is that the irradiated hydrogen ions terminate dangling bonds made of unpaired electrons and reduce the barrier to conduction carriers. It depends on the fact that there is. For this reason, when the silicon thin film that serves as the active layer is as thick as several hundred angstroms, the number of lattice defects and unpaired electrons at crystal boundaries in the silicon thin film increases, and a large amount of unpaired electrons are required to terminate them. This is because hydrogen ions must be implanted. Moreover, most of the hydrogen ions implanted into a silicon thin film with a thickness of several hundred Å are concentrated in a region several tens of Å to several hundred Å from the gate insulating film side interface of the silicon thin film. It does not reach the interface of the thin film on the substrate side. For this reason, other unpaired electrons existing in the silicon thin film are not terminated and form trap levels, carrier scattering occurs, and the electrical characteristics of the thin film transistor cannot be sufficiently improved. have.

【0005】そこで、本発明はこのような問題点を解決
するもので、その目的とするところは良好なコンタクト
抵抗とシート抵抗を有する厚膜のソース電極領域および
ドレイン電極領域を備え、700Å以下の活性層を有し
、短時間の水素化によって容易に優れた電気的特性が得
られうる薄膜トランジスタの製造方法を提供することに
ある。
The present invention is intended to solve these problems, and its purpose is to provide thick film source and drain electrode regions with good contact resistance and sheet resistance. It is an object of the present invention to provide a method for manufacturing a thin film transistor that has an active layer and can easily obtain excellent electrical characteristics by hydrogenation for a short time.

【0006】[0006]

【課題を解決するための手段】本発明の薄膜トランジス
タの製造方法は、絶縁性基体上にMOS型電界効果トラ
ンジスタを形成する薄膜トランジスタの製造方法におい
て、活性層となる薄膜半導体層を選択酸化して700Å
以下の膜厚にする工程を含むことを特徴とする。本発明
の薄膜トランジスタの製造方法は、前記活性層となる薄
膜半導体層にレーザ照射し加熱する工程を含むことを特
徴とする。
Means for Solving the Problems The method for manufacturing a thin film transistor of the present invention is a method for manufacturing a thin film transistor in which a MOS field effect transistor is formed on an insulating substrate, in which a thin film semiconductor layer to be an active layer is selectively oxidized to a thickness of 70 Å.
It is characterized by including the step of making the film thickness as follows. The method for manufacturing a thin film transistor according to the present invention is characterized by including a step of irradiating and heating the thin film semiconductor layer serving as the active layer with a laser.

【0007】また、本発明の薄膜トランジスタの製造方
法において、前記活性層となる薄膜半導体層に水素イオ
ンを注入する工程を含むことを特徴とする。
[0007] Furthermore, the method for manufacturing a thin film transistor according to the present invention is characterized in that it includes a step of implanting hydrogen ions into the thin film semiconductor layer that will become the active layer.

【0008】[0008]

【実施例】以下本発明に係る薄膜トランジスタの製造方
法について、実施例にもとづき詳細に説明する。
EXAMPLES The method for manufacturing a thin film transistor according to the present invention will be described in detail below based on examples.

【0009】まず、本発明の請求項第1項にもとづいて
薄膜トランジスタを作製する例を示す。はじめに図1(
a)に示したように石英基板などの絶縁性基体1上にシ
リコン膜2を積層する。このシリコン膜2はプラズマC
VD(プラズマ励起による化学的気相成長)法により2
00℃から数百℃の加熱状態で成膜した非晶性のアモル
ファス・シリコン膜や減圧CVD法により数百℃以上の
加熱状態で成膜した多結晶性のシリコン膜でも良い。 ただし、水素の含有量が数%以上のシリコン膜にたいし
ては、堆積後300℃から500℃の加熱状態で水素抜
きをほどこし、シリコン膜の安定性を高める。ついで、
図1(b)に示したように選択酸化をおこなうシリコン
膜2の表面以外を窒化シリコン膜で覆い、酸素雰囲気下
で図のように局所的に酸化し、二酸化シリコン膜5を形
成する。この局所的な選択酸化をおこなう際に加えられ
た熱によって、シリコン膜2中のシリコン原子の再配列
が起きシリコン膜2は多結晶シリコン膜3に変化する。 また、同時に多結晶シリコン膜3の酸化された部分の膜
厚は薄くなる。さらに、選択酸化により形成された二酸
化シリコン膜5と窒化シリコン膜4を取り除いた後、多
結晶シリコン膜をフォトリソグラフィー法により島状に
加工し、多結晶シリコン膜を酸化して図1(c)に示す
ようにゲート絶縁膜7を構成する。この酸化の際に多結
晶シリコン膜3の膜厚が減少し多結晶シリコン薄膜6に
変換される。この酸化により形成された多結晶シリコン
薄膜6に薄膜トランジスタのソース領域とドレイン領域
および活性層となるチャネル領域が形成されることにな
る。活性層となる領域の膜厚は200Åから700Åで
、ソース電極領域9とドレイン電極領域10となる領域
の膜厚は1000Åから2000Åである。次に図1(
d)に示したように、ゲート電極12を構成した後、自
己整合法によりソース電極領域9およびドレイン電極領
域10を形成する。さらに同図に示すようにソース電極
領域9とドレイン電極領域10を覆うゲート絶縁膜の一
部をフォトリソグラフィー法により取り除き、アルミ配
線11材料とソース電極領域9およびドレイン電極領域
10が接触するように加工して保護膜13を成膜する。 このようにして形成された薄膜トランジスタは200Å
から700Åの薄いチャネル領域と1000Åから20
00Åの厚いソース電極とドレイン電極の領域を有する
ようになる。このため、チャネル領域における最大空乏
層の広がりは浅く抑えられ、トランジスタ動作時の伝導
層となる反転層の形成は、各電極へ印加する電圧が低電
圧の場合においても容易になされる。したがって、薄膜
トランジスタの電気特性は厚膜の活性層を有する場合に
比べ著しく改善される。図3に活性層の厚さを1000
Åとした場合と400Åとした場合の薄膜トランジスタ
のゲート印加電圧とドレイン電流の関係を表す電気特性
を示す。図3において、実線16で表した電気特性は従
来例にもとづき活性層とソース・ドレイン領域を同じ膜
厚にして構成したものを示している。シリコン薄膜の厚
さは1000Åである。この特性に対し、破線17は本
発明の実施例にもとづき活性層の厚さを500Åにした
場合の薄膜トランジスタの電気特性を示している。 この実施例が示すように活性層の厚さを薄膜化すること
は、薄膜トランジスタの電気特性を著しく改善する効果
がある。そのうえ、ソース電極領域9とドレイン電極領
域10の膜厚が厚いために、それら電極領域のシート抵
抗やアルミ配線11とのコンタクト抵抗も十分小さく抑
えられ、寄生抵抗として薄膜トランジスタの電気特性に
悪影響を与えることも無い。
First, an example of manufacturing a thin film transistor based on the first aspect of the present invention will be described. IntroductionFigure 1 (
As shown in a), a silicon film 2 is laminated on an insulating substrate 1 such as a quartz substrate. This silicon film 2 is exposed to plasma C.
2 by VD (chemical vapor deposition using plasma excitation) method.
It may be an amorphous silicon film formed in a heated state of 00° C. to several hundreds of degrees Celsius, or a polycrystalline silicon film formed in a heated state of several hundred degrees Celsius or higher by low pressure CVD. However, for silicon films with a hydrogen content of several percent or more, hydrogen is removed by heating at 300° C. to 500° C. after deposition to increase the stability of the silicon film. Then,
As shown in FIG. 1B, the surface of the silicon film 2 other than the surface to be selectively oxidized is covered with a silicon nitride film, and is locally oxidized as shown in the figure in an oxygen atmosphere to form a silicon dioxide film 5. The heat applied during this local selective oxidation causes the silicon atoms in the silicon film 2 to be rearranged, and the silicon film 2 changes into a polycrystalline silicon film 3. At the same time, the thickness of the oxidized portion of the polycrystalline silicon film 3 becomes thinner. Furthermore, after removing the silicon dioxide film 5 and silicon nitride film 4 formed by selective oxidation, the polycrystalline silicon film is processed into an island shape by photolithography, and the polycrystalline silicon film is oxidized, as shown in FIG. 1(c). The gate insulating film 7 is configured as shown in FIG. During this oxidation, the thickness of polycrystalline silicon film 3 is reduced and converted into polycrystalline silicon thin film 6. In the polycrystalline silicon thin film 6 formed by this oxidation, a source region, a drain region, and a channel region which becomes an active layer of a thin film transistor are formed. The film thickness of the region to be the active layer is 200 Å to 700 Å, and the film thickness of the regions to be the source electrode region 9 and the drain electrode region 10 is 1000 Å to 2000 Å. Next, Figure 1 (
As shown in d), after forming the gate electrode 12, a source electrode region 9 and a drain electrode region 10 are formed by a self-alignment method. Furthermore, as shown in the figure, a part of the gate insulating film covering the source electrode region 9 and drain electrode region 10 is removed by photolithography so that the material of the aluminum wiring 11 comes into contact with the source electrode region 9 and drain electrode region 10. A protective film 13 is formed by processing. The thin film transistor formed in this way has a thickness of 200 Å.
Thin channel region from 700 Å and from 1000 Å to 20
It has a thick source electrode and drain electrode region of 00 Å. Therefore, the maximum depletion layer in the channel region is suppressed to a shallow extent, and an inversion layer that becomes a conductive layer during transistor operation can be easily formed even when the voltage applied to each electrode is low. Therefore, the electrical characteristics of the thin film transistor are significantly improved compared to the case where the thin film transistor has a thick active layer. The thickness of the active layer is 1000 in Figure 3.
The electrical characteristics representing the relationship between the gate applied voltage and drain current of the thin film transistor are shown when the thickness is 400 Å and when the thickness is 400 Å. In FIG. 3, the electrical characteristics indicated by a solid line 16 are based on a conventional example in which the active layer and the source/drain regions are made to have the same thickness. The thickness of the silicon thin film is 1000 Å. In contrast to this characteristic, a broken line 17 shows the electrical characteristic of the thin film transistor when the thickness of the active layer is set to 500 Å based on the embodiment of the present invention. As shown in this example, reducing the thickness of the active layer has the effect of significantly improving the electrical characteristics of the thin film transistor. Moreover, since the film thicknesses of the source electrode region 9 and the drain electrode region 10 are thick, the sheet resistance of these electrode regions and the contact resistance with the aluminum wiring 11 are kept sufficiently low, which adversely affects the electrical characteristics of the thin film transistor as a parasitic resistance. No problem.

【0010】次に本発明の請求項第2項に関する実施例
を説明する。図2(a)〜図2(c)は、本発明の請求
項第2項の一実施例の薄膜トランジスタの製造方法を説
明するための工程順断面図である。まず、請求項第1項
の実施例と同様に図2(a)に示すように絶縁性基体上
1にシリコン膜2を成膜する。次に図2(b)に示すよ
うに、シリコン膜2の一部領域を窒化シリコン膜4をマ
スクにして選択酸化して二酸化シリコン膜5を形成し、
レーザビーム15を照射しシリコン膜2を結晶性シリコ
ン膜14へ変換する。このレーザビーム15の照射はシ
リコン膜2内のシリコンを瞬間的に融解し、照射後シリ
コンは急速に再び固化する。この固化の際に、シリコン
の結晶が成長し結晶性シリコン膜14が形成される。結
晶性シリコン膜14を活性層とソース・ドレイン領域と
する薄膜トランジスタは、たんに活性層のシリコン膜の
膜厚を薄膜化させたものに比べ、高易動度の優れた電気
特性を示すことがわかっている。図4の電気特性を示す
図には、チャネルの薄膜化とレーザビーム照射をおこな
った薄膜トランジスタの特性と1000Åの活性層をも
つ従来の薄膜トランジスタの特性を記した。破線18は
活性層の薄膜を500Åとしレーザビームを照射して構
成された結晶性シリコン膜14からなる薄膜トランジス
タの電気特性で、実線16は前記の活性層1000Åの
薄膜トランジスタの電気特性を示している。活性層の薄
膜化ばかりでなく、レーザビームの照射をおこない結晶
性を改善すると易動度が大きくなり、高電圧印加時の電
気特性が著しく向上することがわかる。また活性層であ
るシリコン層の結晶化は、伝導キャリヤの電気的易動度
を高めるばかりでなく、薄膜トランジスタの温度特性を
も改善する。これは、活性層のシリコン膜の結晶化が、
キャリヤの伝導障壁となる結晶欠陥をも減少させる効果
をもたらすためである。このため、電流の活性化エネル
ギーも減少しほとんどゼロになり、薄膜トランジスタの
高温においても安定した動作が可能となる。
Next, an embodiment related to claim 2 of the present invention will be described. 2(a) to 2(c) are step-by-step cross-sectional views for explaining a method for manufacturing a thin film transistor according to an embodiment of claim 2 of the present invention. First, a silicon film 2 is formed on an insulating substrate 1, as shown in FIG. 2(a), similarly to the embodiment of claim 1. Next, as shown in FIG. 2B, a partial region of the silicon film 2 is selectively oxidized using the silicon nitride film 4 as a mask to form a silicon dioxide film 5.
A laser beam 15 is irradiated to convert the silicon film 2 into a crystalline silicon film 14. The irradiation with this laser beam 15 instantaneously melts the silicon within the silicon film 2, and after the irradiation, the silicon rapidly solidifies again. During this solidification, silicon crystals grow and a crystalline silicon film 14 is formed. A thin film transistor in which the crystalline silicon film 14 is used as an active layer and source/drain region can exhibit superior electrical characteristics with high mobility compared to a transistor in which the silicon film in the active layer is simply made thinner. know. The electrical characteristics diagram in FIG. 4 shows the characteristics of a thin film transistor in which the channel was made thinner and irradiated with a laser beam, and the characteristics of a conventional thin film transistor with an active layer of 1000 Å. The broken line 18 shows the electrical characteristics of a thin film transistor made of a crystalline silicon film 14 formed by laser beam irradiation with a thin active layer of 500 Å, and the solid line 16 shows the electrical characteristics of the thin film transistor with an active layer of 1000 Å. It can be seen that not only making the active layer thinner but also improving the crystallinity by irradiating it with a laser beam increases the mobility and significantly improves the electrical properties when high voltage is applied. Furthermore, crystallization of the active silicon layer not only increases the electrical mobility of conduction carriers but also improves the temperature characteristics of the thin film transistor. This is because the crystallization of the silicon film in the active layer
This is because it has the effect of reducing crystal defects that act as carrier conduction barriers. Therefore, the activation energy of the current decreases to almost zero, allowing stable operation of the thin film transistor even at high temperatures.

【0011】さらに、本発明の請求項3に関する一実施
例を示す。図5の工程において薄膜トランジスタに水素
イオン20を照射する。従来例の薄膜トランジスタへの
水素イオン照射は、活性層とソース・ドレイン両電極領
域の膜厚が同じものか、あるいは、ソース・ドレイン両
電極領域が活性層とは別の工程によって積層されたもの
に適用されたものであった。後者の別々の工程によって
積層された薄膜トランジスタにおいてはソース・ドレイ
ン両電極領域と活性層との間に生ずる欠陥や抵抗が電気
特性に悪影響をおよぼし易く望ましくない。また、島状
の両電極領域を構成するためにおこなわれるフォトリソ
グラフィー法の工程の段階での汚染物質の混入を完全に
防ぐことは困難で、混入した汚染物質が薄膜トランジス
タの信頼性を下げる原因にもなっていた。さらに、前者
の活性層と両電極領域が同じ膜厚を有する薄膜トランジ
スタにおいては、前記したように薄膜トランジスタの電
気特性を向上させるための膜厚の最適化が困難で、十分
特性を向上させられないという問題点があった。これら
に対し、図5のように一度に成膜された両電極領域と薄
膜化された活性層を有する薄膜トランジスタにおける水
素照射は、その薄膜化のために極めて単時間でかつ低パ
ワーでおこなうことができるうえに、他の汚染物質の混
入もない。活性層が厚膜の場合、水素照射による不対電
子の終端化をおこなうには10KeV近くの高パワーで
1時間以上照射する必要があった。ところが、前記した
本実施例のように200Åから700Åの最適化した活
性層の膜厚を有する薄膜トランジスタにおいては、数K
eV以下の低パワーでかつ30分程度の短時間で、十分
効果的な水素照射ができる。低パワーで照射することが
可能な場合には、薄膜トランジスタに与える照射時のダ
メージも少なく、水素イオン照射による薄膜トランジス
タの破壊を防ぎ、高歩留まりな工程となり得る。図6に
示した薄膜トランジスタの電気特性は、5KeVで30
分間水素イオンを照射することによって得られたものの
特性と、前記実施例におけるレーザビーム照射を照射し
たものの特性を示している。実線18が図2bでレーザ
ビーム15を照射した薄膜トランジスタの特性を示し、
破線19は実線18の特性を示す薄膜トランジスタに図
5の水素イオン照射をおこなった薄膜トランジスタの特
性を示している。この図6の特性比較からも明らかなよ
うに、水素イオン照射は薄膜トランジスタの電気特性を
著しく改善する。薄膜トランジスタの動作電流の増加ば
かりでなく、特にリーク電流の減少において効果がみら
れる。これは、リーク電流の原因となるドレイン電極近
傍の不対電子から構成される欠陥準位の量が水素イオン
の照射により終端化され減少したためと考えられる。こ
のリーク電流の減少により動作電流量とリーク電流量の
比として定義されるオン・オフ比が増大し、薄膜トラン
ジスタの動作許容領域を広げ、種々の高性能な応用商品
への適用を可能とする。たとえば、ハイビジョン対応の
液晶テレビの駆動素子や高精細カラー・センサーへの適
用も可能である。
Furthermore, an embodiment related to claim 3 of the present invention will be described. In the process shown in FIG. 5, the thin film transistor is irradiated with hydrogen ions 20. In conventional hydrogen ion irradiation of thin film transistors, either the active layer and the source/drain electrode regions have the same film thickness, or the source/drain electrode regions are laminated in a separate process from the active layer. It was applied. In the latter thin film transistor laminated by separate steps, defects and resistance occurring between the source/drain electrode regions and the active layer tend to adversely affect electrical characteristics, which is undesirable. Additionally, it is difficult to completely prevent contaminants from entering during the photolithography process used to form the island-shaped electrode regions, and contaminants that do enter can reduce the reliability of thin film transistors. It was also becoming. Furthermore, in the case of the former thin film transistor in which the active layer and both electrode regions have the same film thickness, it is difficult to optimize the film thickness to improve the electrical characteristics of the thin film transistor, as described above, and it is said that the characteristics cannot be sufficiently improved. There was a problem. On the other hand, hydrogen irradiation in a thin film transistor having both electrode regions formed at once and an active layer thinned as shown in FIG. 5 can be performed in an extremely short period of time and at low power in order to thin the film. Not only that, but there are no other contaminants mixed in. When the active layer is a thick film, terminating unpaired electrons by hydrogen irradiation requires irradiation at a high power of nearly 10 KeV for more than one hour. However, in a thin film transistor having an optimized active layer thickness of 200 Å to 700 Å as in this embodiment described above, the thickness of several K
Sufficiently effective hydrogen irradiation can be performed with low power of eV or less and in a short time of about 30 minutes. If it is possible to irradiate with low power, there will be less damage to the thin film transistor during irradiation, and destruction of the thin film transistor due to hydrogen ion irradiation can be prevented, resulting in a high-yield process. The electrical characteristics of the thin film transistor shown in Figure 6 are 30 at 5KeV.
The characteristics obtained by irradiation with hydrogen ions for a minute and the characteristics obtained by irradiation with the laser beam in the above example are shown. A solid line 18 indicates the characteristics of the thin film transistor irradiated with the laser beam 15 in FIG. 2b,
A broken line 19 indicates the characteristics of a thin film transistor obtained by subjecting the thin film transistor exhibiting the characteristics shown in the solid line 18 to the hydrogen ion irradiation shown in FIG. As is clear from the characteristic comparison in FIG. 6, hydrogen ion irradiation significantly improves the electrical characteristics of the thin film transistor. The effect is seen not only in increasing the operating current of thin film transistors, but also in reducing leakage current in particular. This is considered to be because the amount of defect levels composed of unpaired electrons near the drain electrode, which causes leakage current, is terminated and reduced by the hydrogen ion irradiation. This reduction in leakage current increases the on-off ratio defined as the ratio of the amount of operating current to the amount of leakage current, broadening the allowable operating range of thin film transistors and making them applicable to a variety of high-performance application products. For example, it can be applied to drive elements for high-definition LCD televisions and high-definition color sensors.

【0012】0012

【発明の効果】以上説明したように本発明の薄膜トラン
ジスタの製造方法は、選択的酸化工程を利用することに
より活性層とソース・ドレイン両電極領域の膜厚の最適
化を容易にし、反転層の形成を速め両電極の抵抗を低下
させて電気的特性を飛躍的に向上させ得る効果を有する
。また、レーザビーム照射によりさらに特性を向上させ
るとともに動作可能な温度領域を広げられる。さらに、
活性層の薄膜化によって水素照射工程のパワーを下げ時
間を短縮することが可能で水素照射も効果的におこなわ
れ電気特性をさらに向上させ得るとともに、水素照射に
よるダメージを弱め薄膜トランジスタの製造歩留まりを
向上させ、リーク電流も減少させることにより、高性能
な薄膜トランジスタを必要とする種々の商品への適用も
可能となるという効果を有する。
Effects of the Invention As explained above, the method for manufacturing a thin film transistor of the present invention makes it easy to optimize the film thickness of the active layer and the source/drain electrode regions by using a selective oxidation process. It has the effect of speeding up the formation, lowering the resistance of both electrodes, and dramatically improving the electrical characteristics. Further, by laser beam irradiation, the characteristics can be further improved and the operable temperature range can be expanded. moreover,
By making the active layer thinner, it is possible to reduce the power and time of the hydrogen irradiation process, and hydrogen irradiation can be performed effectively, further improving electrical characteristics, as well as weakening the damage caused by hydrogen irradiation and improving the manufacturing yield of thin film transistors. By reducing the leakage current, it is possible to apply the thin film transistor to various products requiring high performance thin film transistors.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の薄膜トランジスタの製造方法の請求項
1に係る一実施例を示す工程順断面図。
FIG. 1 is a step-by-step sectional view showing an embodiment of the method for manufacturing a thin film transistor of the present invention.

【図2】本発明の薄膜トランジスタの製造方法の請求項
2に係る一実施例を示す工程順断面図。
FIG. 2 is a step-by-step cross-sectional view showing an embodiment of the thin film transistor manufacturing method of the present invention.

【図3】本発明の薄膜トランジスタの製造方法の請求項
1にもとづく工程により製作した薄膜トランジスタの電
気的特性図。
FIG. 3 is an electrical characteristic diagram of a thin film transistor manufactured by the process according to claim 1 of the method for manufacturing a thin film transistor of the present invention.

【図4】本発明の薄膜トランジスタの製造方法の請求項
2にもとづく工程により製作した薄膜トランジスタの電
気的特性図。
FIG. 4 is an electrical characteristic diagram of a thin film transistor manufactured by the process according to claim 2 of the method for manufacturing a thin film transistor of the present invention.

【図5】本発明の薄膜トランジスタの製造方法の請求項
3にかかる一実施例を示す工程断面図。
FIG. 5 is a process sectional view showing an embodiment of the method for manufacturing a thin film transistor of the present invention.

【図6】本発明の薄膜トランジスタの製造方法の請求項
3にもとづく工程により製作した薄膜トランジスタの電
気的特性図。
FIG. 6 is an electrical characteristic diagram of a thin film transistor manufactured by the process according to claim 3 of the method for manufacturing a thin film transistor of the present invention.

【図7】従来の薄膜トランジスタの製造方法の一実施例
を示す工程順断面図。
FIG. 7 is a step-by-step cross-sectional view showing an example of a conventional thin film transistor manufacturing method.

【符号の説明】[Explanation of symbols]

1  絶縁性基体 2  シリコン膜 3  多結晶シリコン膜 4  窒化シリコン膜 5  二酸化シリコン膜 6  多結晶シリコン薄膜 7  ゲート酸化膜 8  多結晶シリコン薄膜 9  ソース電極領域 10  ドレイン電極領域 11  アルミ配線 12  ゲート電極 13  保護膜 14  結晶性シリコン膜 15  レーザビーム 20  水素イオン 21  石英基板 22  シリコン薄膜 23  層間絶縁膜 24  ゲート絶縁膜 1 Insulating substrate 2 Silicon film 3 Polycrystalline silicon film 4 Silicon nitride film 5 Silicon dioxide film 6 Polycrystalline silicon thin film 7 Gate oxide film 8 Polycrystalline silicon thin film 9 Source electrode area 10 Drain electrode area 11 Aluminum wiring 12 Gate electrode 13 Protective film 14 Crystalline silicon film 15 Laser beam 20 Hydrogen ion 21 Quartz substrate 22 Silicon thin film 23 Interlayer insulation film 24 Gate insulating film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】絶縁性基体上にMOS型電界効果トランジ
スタを形成する薄膜トランジスタの製造方法において、
活性層となる薄膜半導体層を選択酸化して700Å以下
の膜厚にする工程とを含むことを特徴とする薄膜トラン
ジスタの製造方法。
1. A method for manufacturing a thin film transistor in which a MOS field effect transistor is formed on an insulating substrate, comprising:
1. A method for manufacturing a thin film transistor, comprising the step of selectively oxidizing a thin film semiconductor layer serving as an active layer to a thickness of 700 Å or less.
【請求項2】請求項1記載の薄膜トランジスタの製造方
法において、前記活性層となる薄膜半導体層にレーザ照
射し加熱する工程を含むことを特徴とする薄膜トランジ
スタの製造方法。
2. The method of manufacturing a thin film transistor according to claim 1, further comprising the step of irradiating the thin film semiconductor layer serving as the active layer with a laser and heating it.
【請求項3】請求項1記載の薄膜トランジスタの製造方
法において、前記活性層となる薄膜半導体層に水素イオ
ンを注入する工程を含むことを特徴とする薄膜トランジ
スタの製造方法。
3. The method of manufacturing a thin film transistor according to claim 1, further comprising the step of implanting hydrogen ions into the thin film semiconductor layer serving as the active layer.
JP7925691A 1991-04-11 1991-04-11 Manufacture of thin-film transistor Pending JPH04313272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7925691A JPH04313272A (en) 1991-04-11 1991-04-11 Manufacture of thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7925691A JPH04313272A (en) 1991-04-11 1991-04-11 Manufacture of thin-film transistor

Publications (1)

Publication Number Publication Date
JPH04313272A true JPH04313272A (en) 1992-11-05

Family

ID=13684775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7925691A Pending JPH04313272A (en) 1991-04-11 1991-04-11 Manufacture of thin-film transistor

Country Status (1)

Country Link
JP (1) JPH04313272A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656825A (en) * 1994-06-14 1997-08-12 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor having crystalline semiconductor layer obtained by irradiation
US6337232B1 (en) 1995-06-07 2002-01-08 Semiconductor Energy Laboratory Co., Ltd. Method of fabrication of a crystalline silicon thin film semiconductor with a thin channel region
US6797550B2 (en) 2001-12-21 2004-09-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method therefor
US6911358B2 (en) 2001-12-28 2005-06-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656825A (en) * 1994-06-14 1997-08-12 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor having crystalline semiconductor layer obtained by irradiation
US5940690A (en) * 1994-06-14 1999-08-17 Kusumoto; Naoto Production method for a thin film semiconductor device with an alignment marker made out of the same layer as the active region
US6541795B2 (en) 1994-06-14 2003-04-01 Semiconductor Energy Laboratory Co., Ltd. Thin film semiconductor device and production method for the same
US6337232B1 (en) 1995-06-07 2002-01-08 Semiconductor Energy Laboratory Co., Ltd. Method of fabrication of a crystalline silicon thin film semiconductor with a thin channel region
US6797550B2 (en) 2001-12-21 2004-09-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method therefor
US7319055B2 (en) 2001-12-21 2008-01-15 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device utilizing crystallization of semiconductor region with laser beam
US6911358B2 (en) 2001-12-28 2005-06-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7129121B2 (en) 2001-12-28 2006-10-31 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
JP2731056B2 (en) Method for manufacturing thin film transistor
JP3841598B2 (en) Manufacturing method of semiconductor device
JPS60137070A (en) Manufacture of semiconductor device
JPH0523055B2 (en)
US5015593A (en) Method of manufacturing semiconductor device
JPH08250713A (en) Insulated-gate field-effect transistor and manufacture thereof
JPH04313272A (en) Manufacture of thin-film transistor
JP2001185548A (en) Semiconductor device and manufacturing method thereof
JPH04276662A (en) Manufacture of semiconductor device
JP4541489B2 (en) Semiconductor device and manufacturing method thereof
JPH06349856A (en) Thin-film transistor and its manufacture
JP2002299590A (en) Method of manufacturing semiconductor substrate and semiconductor device
JPH04316333A (en) Manufacture of thin-film transistor
JP2001036078A (en) Mos-type transistor and manufacture thereof
US5391509A (en) Method of manufacturing a semiconductor device forming a high concentration impurity region through a CVD insulating film
JP3277910B2 (en) Field effect transistor and method of manufacturing the same
JPS6126264A (en) Manufacture of semiconductor device
JP4321828B2 (en) Method for manufacturing semiconductor device
JP4387477B2 (en) Manufacturing method of semiconductor device
JP2007048882A (en) Semiconductor device and its manufacturing method
JPH01112755A (en) Manufacture of semiconductor device
JPS6346776A (en) Manufacture of thin film transistor
JPH0684944A (en) Thin film transistor
JPS63261879A (en) Manufacture of semiconductor device
JPH0555232A (en) Manufacture of semiconductor device