CN113161423A - Thin film transistor, manufacturing method of thin film transistor and display panel - Google Patents
Thin film transistor, manufacturing method of thin film transistor and display panel Download PDFInfo
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- CN113161423A CN113161423A CN202110452733.9A CN202110452733A CN113161423A CN 113161423 A CN113161423 A CN 113161423A CN 202110452733 A CN202110452733 A CN 202110452733A CN 113161423 A CN113161423 A CN 113161423A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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Abstract
The embodiment of the invention discloses a thin film transistor, a manufacturing method of the thin film transistor and a display panel. The thin film transistor includes a substrate; an active layer, an insulating layer, and a gate electrode layer which are stacked in this order on one side of a substrate; the active layer comprises a channel region, a source region and a drain region which are arranged on two sides of the channel region; the thickness of a first region of the source region, which is adjacent to the channel region, is smaller than that of the channel region; and/or the thickness of the second region of the drain region adjacent to the channel region is less than the thickness of the channel region. According to the technical scheme provided by the embodiment of the invention, the area of the cross section of the first region adjacent to the channel region and the area of the cross section of the second region adjacent to the channel region are smaller, so that the area of a path for ions to diffuse to the channel region is reduced, the effective length of the channel region arranged between the source region and the drain region is longer, the reliability and the stability of the thin film transistor are improved, and the problem that the length of the channel of the thin film transistor is reduced after the ions are injected into the thin film transistor in the prior art is solved.
Description
Technical Field
The embodiment of the invention relates to the technical field of thin film transistors, in particular to a thin film transistor, a manufacturing method of the thin film transistor and a display panel.
Background
With the development of display technology and the improvement of living standard of people, display devices are widely used. In the conventional display device, the thin film transistor is generally used as a switching element or a driving element to control a pixel, and the reliability and stability of the conventional thin film transistor are low.
Disclosure of Invention
The embodiment of the invention provides a thin film transistor, a manufacturing method of the thin film transistor and a display panel, and aims to solve the problem that the existing thin film transistor is low in reliability and stability.
In order to realize the technical problem, the invention adopts the following technical scheme:
in a first aspect, an embodiment of the present invention provides a thin film transistor, including:
a substrate;
an active layer, an insulating layer, and a gate electrode layer which are stacked in this order on one side of a substrate;
the active layer comprises a channel region, a source region and a drain region which are arranged on two sides of the channel region;
the thickness of a first region of the source region, which is adjacent to the channel region, is smaller than that of the channel region; and/or the thickness of the second region of the drain region adjacent to the channel region is less than the thickness of the channel region.
Further, the first region includes a first boundary adjacent to the channel region and a second boundary remote from the channel region;
the thickness of the first area gradually increases along the direction from the first boundary to the second boundary;
the second region comprises a third boundary adjacent to the channel region and a fourth boundary far away from the channel region;
the thickness of the second region gradually increases in a direction in which the third boundary points to the fourth boundary.
Further, the first region comprises at least two sub-source regions, and the thickness of the sub-source regions is gradually increased along the direction far away from the channel region;
the second region includes at least two sub-drain regions, and the thickness of the sub-drain regions gradually increases along a direction away from the channel region.
Further, the insulating layer covers only the channel region or covers the entire active layer.
Furthermore, the thickness of the first region is 40% -80% of the thickness of the channel region;
the thickness of the second region is 40% -80% of the thickness of the channel region.
Further, the first region is a source region;
the second region is a drain region.
Further, the material of the active layer is a metal oxide.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a thin film transistor, including:
providing a substrate;
forming a semiconductor layer on a substrate; wherein the semiconductor layer comprises a source region, a channel region and a drain region; the thickness of a first region of the source region, which is adjacent to the channel region, is smaller than that of the channel region; and/or the thickness of a second region of the drain region, which is adjacent to the channel region, is less than that of the channel region;
forming an insulating layer on one side of the semiconductor layer far away from the substrate;
forming a gate electrode layer on one side of the insulating layer away from the substrate;
and implanting ions into the semiconductor layer by using the gate electrode layer as a mask to form an active layer having a channel region and source and drain regions disposed on both sides of the channel region.
Further, forming a semiconductor layer on the substrate includes:
forming a semiconductor material layer on a substrate;
forming a photoresist layer on one side of the semiconductor material layer far away from the substrate;
patterning the photoresist layer;
and etching the semiconductor material layer to form a semiconductor layer.
In a third aspect, an embodiment of the present invention provides a display panel, including any of the thin film transistors in the first aspect.
According to the thin film transistor provided by the embodiment of the invention, the thickness of the first region adjacent to the channel region and the source region is smaller than that of the channel region; and/or the thickness of the second region adjacent to the channel region of the drain region is smaller than that of the channel region, so that the area of the cross section of the first region adjacent to the channel region and the area of the cross section of the second region adjacent to the channel region are smaller, the area of a path for ions to diffuse to the channel region is reduced, the effective length of the channel region arranged between the source region and the drain region is longer, and the reliability and the stability of the thin film transistor are improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
fig. 6 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;
fig. 7 is a flowchart of another method for fabricating a thin film transistor according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background art, the existing thin film transistor has the problem of low reliability and stability, and the inventor researches and discovers that the active layer of the existing thin film transistor is generally manufactured by forming a semiconductor layer and then implanting ions into the semiconductor layer to form a source region or a drain region, wherein the region between the source region and the drain region of the active layer is a channel region, and due to the ion diffusion effect, the ions of the source region or the drain region can diffuse into the channel region after being implanted, so that the length of the channel of the thin film transistor is reduced, and the reliability and stability of the thin film transistor are low.
Based on the above technical problem, the present embodiment proposes the following solutions:
fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention. Referring to fig. 1, a thin film transistor provided by an embodiment of the present invention includes a substrate 100; an active layer 200, an insulating layer 300, and a gate electrode layer 400 which are stacked in this order on one side of a substrate 100; active layer200 comprises a channel region 201, and a source region 202 and a drain region 203 which are arranged at two sides of the channel region 201; thickness d of first region 1 of source region 202 adjacent to channel region1Less than the thickness D of the channel region 201; and/or the thickness d of the second region 2 of the drain region 203 adjacent to the channel region 2012Less than the thickness D of the channel region 201.
Specifically, the substrate 100 may be transparent glass, the material may be silicon dioxide, the substrate 100 may also be an opaque material or a component of plastic, and the material of the substrate 100 may be selected according to the requirement of the display device. The material of the insulating layer 300 is an insulating material, the insulating layer 300 insulates the active layer 200 and the gate electrode layer 400, the gate electrode layer 400 is a metal layer, and the material of the gate electrode layer 400 may be one or more conductive materials of Ag, Mg, Al, Pt, Au, Ni, Li, Ca, Mo, Ti, Cu, and the like. The active layer 200 may be formed by patterning a semiconductor material layer into a semiconductor layer, the material of the semiconductor layer may include polysilicon or zinc oxide material, and may also include metal, and implanting ions into the semiconductor layer to form a source region 202 and a drain region 203 having ions and a channel region 201 between the source region 202 and the drain region 203, and the semiconductor layer may form a doped source region 202 or drain region 203 by low dose implantation, so as to improve mobility of electrons or holes. Alternatively, the semiconductor layer may be formed into the N-type doped active layer 200 by implanting an element such as phosphorus, arsenic, or antimony, so as to further improve the mobility of electrons.
The source region 202 includes a first region 1 adjacent to the channel region 201, and a thickness d of the first region 1 may be set1Is smaller than the thickness D of the channel region 201 due to the thickness D of the first region 11The first region 1 is thinner, on one hand, the area of the cross section of the first region 1 perpendicular to the substrate direction is smaller, when the source region 202 is formed by ion implantation, the area of a path for ions to diffuse to the channel region 201 close to one end of the first region 1 is reduced, and the diffusion of the ions to the channel region 201 is reduced, on the other hand, when the source region 202 is formed by ion implantation, the ions implanted into the thinner first region 1 partially diffuse to the substrate 100, so that the ions of the first region 1 adjacent to the channel region 201 are fewer, the diffusion of the ions to the channel region 201 is reduced, and the situation that the ions diffuse to the channel region 201 is ensuredThe effective length of the channel region 201 is longer, and the reliability and stability of the thin film transistor are improved.
The drain region 203 includes a second region 2 adjacent to the channel region 201, and a thickness d of the second region 2 may be set2Is smaller than the thickness D of the channel region 201 due to the thickness D of the second region 22The second region 2 is thin, on one hand, the area of the cross section of the second region 2 perpendicular to the substrate direction is small, when the drain region 203 is formed by ion implantation, the area of a path for ions to diffuse to the channel region 201 close to one end of the second region 2 is reduced, and the diffusion of the ions to the channel region 201 is reduced, on the other hand, when the drain region 203 is formed by ion implantation, the ions implanted to the thin second region 2 partially diffuse to the substrate 100, so that the ions of the second region 2 adjacent to the channel region 201 are few, the effective length of the channel region 201 is long, and the reliability and stability of the thin film transistor are improved.
Furthermore, the thickness d of the first region 1 can also be set1Is smaller than the thickness D of the channel region 201, and the thickness D of the second region 22Smaller than the thickness D of the channel region 201, so that the area of a cross section perpendicular to the substrate direction of the first region 1 adjacent to the channel region 201 and the area of a cross section perpendicular to the substrate direction of the second region 2 adjacent to the channel region 201 are both small, thereby reducing the area of the path of ions diffusing into the channel region 201 near the end of the first region 1 and the channel region 201 near the end of the second region 2, and reducing the diffusion of ions into the channel region 201, and, on the other hand, when ion implantation is performed to form the source region 202 and the drain region 203, ions implanted into the thinner first region 1 and the thinner second region 2 may partially diffuse onto the substrate 100, the first region 1 and the second region 2 adjacent to the channel region 201 are made less ionic, diffusion of ions to the channel region 201 is reduced, the effective length of the channel region 201 arranged between the source region 202 and the drain region 203 is made longer, and the reliability and stability of the thin film transistor are further improved.
In the thin film transistor provided by the embodiment, the thickness of the first region, adjacent to the channel region, of the source region is smaller than that of the channel region; and/or the thickness of the second region adjacent to the channel region of the drain region is smaller than that of the channel region, so that the area of the cross section of the first region adjacent to the channel region and the area of the cross section of the second region adjacent to the channel region are smaller, the area of a path for ions to diffuse to the channel region is reduced, the effective length of the channel region arranged between the source region and the drain region is longer, and the reliability and the stability of the thin film transistor are improved.
Optionally, fig. 2 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 2, a first region 1 of the thin film transistor provided by the embodiment of the invention includes a first boundary 3 adjacent to the channel region 201 and a second boundary 4 far away from the channel region 201, and a thickness d of the first region 1 is along a direction from the first boundary 3 to the second boundary 41Gradually increasing; the second region 2 comprises a third boundary 5 adjacent to the channel region 201 and a fourth boundary 6 remote from the channel region 201, the thickness d of the second region 2 being in a direction from the third boundary 5 to the fourth boundary 62Gradually increasing.
In particular, the thickness d of the first region 1 in the direction of the first boundary 3 towards the second boundary 4 may be provided1Gradually increasing, on one hand, the area of the contact cross section between the first region 1 and the channel region 201 at the first boundary 3 is small, the diffusion of ions to the channel region 201 is reduced, and the effective length of the channel region 201 is ensured to be long, and on the other hand, the thickness d of the source region 202 in the first region 1 is small1The gradient distribution is adopted, and the transition is uniform, so that the gradient angle at the second boundary 4 of the source region 202 is small, and the subsequent deposition of the insulating layer 300 is facilitated.
Furthermore, it is possible to provide the thickness d of the second region 2 in a direction pointing along the third boundary 5 towards the fourth boundary 62Gradually increasing, on one hand, the area of the contact section of the second region 2 at the third boundary 5 and the channel region 201 is smaller, the diffusion of ions to the channel region 201 is reduced, the effective length of the channel region 201 is ensured to be longer, on the other hand, the transition of the source region 202 in the second region 2 is more uniform, the slope angle at the fourth boundary 6 of the source region 202 is smaller, the subsequent deposition of the insulating layer 300 is facilitated, the formed insulating layer 300 is flatter, the formation of gaps or the warping of the insulating layer 300 at the second boundary 4 or the fourth boundary 6 is avoided, and the insulating layer is ensured to be smooth300 has better insulation effect.
Optionally, fig. 3 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 3, the first region 1 of the thin film transistor provided by the embodiment of the invention includes at least two sub-source regions 11, and the thickness d of the sub-source regions 11 along the direction away from the channel region 2011Gradually increasing; the second region 2 comprises at least two sub-drain regions 22, the sub-drain regions 22 having a thickness d in a direction away from the channel region 2012Gradually increasing.
In particular, the thickness d of sub-source region 11 in a direction away from channel region 2011The thickness d of the sub-source region 11 increases in a gradient manner along the direction from the source region 202 to the channel region 2011The channel area of the ions diffusing into the channel region 201 can be gradually reduced, and the diffusion of the ions into the channel region 201 can be better prevented. Thickness d of sub-drain region 222The thickness d of the sub-drain region 22 increases in a gradient manner along the direction from the drain region 203 to the channel region 2012The channel area of the ions diffusing to the channel region 201 can be reduced in a gradient manner, so that the ions are prevented from diffusing to the channel region 201 better, and the effective length of the channel region 201 arranged between the source region 202 and the drain region 203 is longer. The active layer 200 may be formed by a Half tone mask (Half tone mask) such that the thickness d of the sub-source region 11 of the first region 1 of the active layer 2001There are a plurality of thicknesses d of the sub-drain regions 22 of the second region 22Has multiple types, simple process and easy manufacture.
Optionally, fig. 4 is a schematic structural diagram of another thin film transistor provided in the embodiment of the present invention. On the basis of the above embodiments, with reference to fig. 3 and 4, the insulating layer 300 of the thin film transistor provided by the embodiment of the present invention covers only the channel region 201 or the entire active layer 200.
Specifically, with continued reference to fig. 3, the insulating layer 300 of the thin film transistor covers the active layer 200, and ions may be implanted into the semiconductor layer through the insulating layer 300 with the gate electrode layer 400 as a mask to form the active layer 200. Referring to fig. 4, the insulating layer 300 of the thin film transistor only covers the channel region 201, and before ion implantation, the gate electrode layer 400 is used as a mask, and the insulating layer 300 is etched through an etching process, for example, a dry etching process, so that the insulating layer 300 only covers the channel layer, and then, the gate electrode layer 400 is used as a mask to directly implant ions into the semiconductor layer to form the active layer 200, which can improve ion implantation efficiency.
Optionally, with continued reference to fig. 4, the thickness d of the first region 11May be 40% to 80% of the thickness D of the channel region 201; thickness d of the second region 22May be 40% to 80% of the thickness D of the channel region 201.
Specifically, the thicknesses of the first region 1 and the second region 2 are too thin, which affects the continuity of the active layer 200 and further affects the conduction stability of the thin film transistor, and the thicknesses of the first region 1 and the second region 2 are too thick, so that the areas of the cross sections of the first region 1 and the second region 2 in contact with the channel layer are large, which weakens the effect of preventing ions from diffusing into the channel region 201, and the length of the channel region 201 is insufficient, which affects the effect of improving the reliability and stability of the thin film transistor. The thickness d of the first region 1 is set140% -80% of the thickness D of the channel region 201, and the thickness D of the second region 22The thickness of the channel region 201 is 40% -80%, the diffusion path area of the first region 1 and the second region 2 to the channel region 201 can be reduced to a large extent, the effective length of the channel layer 201 is well ensured, the continuity of the active layer 200 is not affected, and the reliability and the stability of the thin film transistor are improved. Alternatively, the thicknesses of the first region 1 and the second region 2 may be set to be the same as needed.
Optionally, fig. 5 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention. On the basis of the above embodiments, referring to fig. 5, the first region 1 of the thin film transistor provided in the embodiment of the present invention may be a source region 202, and the second region 2 may be a drain region 203.
Specifically, by setting the thickness D of the channel region 201 to be larger than the thickness D of the drain region 2032The thickness D of the channel layer is greater than the thickness D of the source region 2021The cross-sectional area of the contact between the source region 202 or the drain region 203 and the channel region 201 is made smaller, thereby reducing the ion diffusionThe effective length of the channel region 201 caused by scattering is shortened, and in addition, the concentration of carriers such as doping ions of the source region 202 or the drain region 203 is uniform, so that the process is simple and easy to realize.
Alternatively, the material of the active layer may be a metal oxide.
Specifically, the active layer may be, for example, Indium Gallium Zinc Oxide (IGZO), IGZO is an amorphous oxide containing indium, gallium, and zinc, and the carrier mobility is 20 to 30 times that of amorphous silicon, so that the charge and discharge rates of the thin film transistor to the pixel electrode can be greatly increased, the response speed of the pixel can be increased, a faster refresh rate can be realized, the line scanning rate of the pixel can be greatly increased due to faster response, and the efficiency is higher.
Optionally, fig. 6 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention. On the basis of the foregoing embodiment, referring to fig. 6, a method for manufacturing a thin film transistor according to an embodiment of the present invention includes:
s101, providing a substrate.
S102, forming a semiconductor layer on a substrate; wherein the semiconductor layer comprises a source region, a channel region and a drain region; the thickness of a first region of the source region, which is adjacent to the channel region, is smaller than that of the channel region; and/or the thickness of the second region of the drain region adjacent to the channel region is less than the thickness of the channel region.
And S103, forming an insulating layer on one side of the semiconductor layer far away from the substrate.
And S104, forming a gate electrode layer on the side, away from the substrate, of the insulating layer.
And S105, implanting ions into the semiconductor layer by taking the gate electrode layer as a mask to form an active layer which is provided with a channel region, and a source region and a drain region which are arranged at two sides of the channel region.
Specifically, the thickness of the first region of the thin film transistor, which is adjacent to the source region and the channel region, manufactured by using the manufacturing method of the thin film transistor provided by the embodiment is smaller than the thickness of the channel region; and/or the thickness of the second region adjacent to the channel region of the drain region is smaller than that of the channel region, so that the area of the cross section of the boundary of the first region adjacent to the channel region and the area of the cross section of the boundary of the second region adjacent to the channel region are smaller, the diffusion strength of ions to the channel region is reduced, the effective length of the channel region arranged between the source region and the drain region is longer, and the reliability and the stability of the thin film transistor can be improved.
Optionally, fig. 7 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention. On the basis of the foregoing embodiment, referring to fig. 7, a method for manufacturing a thin film transistor according to an embodiment of the present invention includes:
s101, providing a substrate.
S201, forming a semiconductor material layer on the substrate.
Specifically, the semiconductor material layer may include a ZnO material such as ZnO, In-ZnO, Ga-In-ZnO, or the like. The semiconductor material layer may be an In-Ga-ZnO (igzo) semiconductor including a metal (e.g., ZnO to which In and Ga are added).
And S202, forming a photoresist layer on one side of the semiconductor material layer away from the substrate.
And S203, patterning the photoresist layer.
In particular, the patterning of the photoresist layer may be achieved by photolithography.
And S204, etching the semiconductor material layer to form a semiconductor layer.
And S103, forming an insulating layer on one side of the semiconductor layer far away from the substrate.
And S104, forming a gate electrode layer on the side, away from the substrate, of the insulating layer.
And S105, implanting ions into the semiconductor layer by taking the gate electrode layer as a mask to form an active layer which is provided with a channel region, and a source region and a drain region which are arranged at two sides of the channel region.
Specifically, the source region and the drain region may be formed by a conductive process, for example, by adjusting an ion concentration of an oxide semiconductor. For example, the source region and the drain region may be formed by increasing the ion concentration of the oxide semiconductor by plasma treatment using, for example, a hydrogen-based gas, a fluorine-based gas, or a combination thereof. The active layer can be formed through a Half tone mask (Half tone mask), so that the thicknesses of the sub-source regions of the first region and the thicknesses of the sub-drain regions of the second region of the active layer are various, the process is simple, and the manufacturing is easy. The first region of the active layer may be made to include at least two sub-source regions, the sub-source regions having thicknesses that gradually increase in a direction away from the channel region; the second region includes at least two sub-drain regions, and the thickness of the sub-drain regions gradually increases along a direction away from the channel region.
Optionally, fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention. On the basis of the above embodiments, referring to fig. 8, a display panel 100 provided by an embodiment of the present invention includes the thin film transistor 200 according to any of the above embodiments. The beneficial effects of the thin film transistor provided by the above embodiments are not described herein. The display panel can be used for mobile terminals such as mobile phones, tablet computers and wearable devices.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A thin film transistor, comprising:
a substrate;
an active layer, an insulating layer, and a gate electrode layer which are sequentially stacked on one side of the substrate;
the active layer comprises a channel region, and a source region and a drain region which are arranged on two sides of the channel region;
the thickness of a first region of the source region adjacent to the channel region is smaller than that of the channel region; and/or the thickness of a second region of the drain region, which is adjacent to the channel region, is smaller than that of the channel region.
2. The thin film transistor according to claim 1,
the first region comprises a first boundary adjacent to the channel region and a second boundary remote from the channel region;
the thickness of the first area gradually increases along the direction in which the first boundary points to the second boundary;
the second region comprises a third boundary adjacent to the channel region and a fourth boundary distal from the channel region;
the thickness of the second region gradually increases in a direction in which the third boundary points to the fourth boundary.
3. The thin film transistor according to claim 1,
the first region comprises at least two sub-source regions, and the thickness of each sub-source region is gradually increased along the direction far away from the channel region;
the second region comprises at least two sub-drain regions, and the thickness of the sub-drain regions is gradually increased along the direction far away from the channel region.
4. The thin film transistor according to claim 1,
the insulating layer covers only the channel region or the entire active layer.
5. The thin film transistor according to claim 1,
the thickness of the first region is 40% -80% of the thickness of the channel region;
the thickness of the second region is 40% -80% of the thickness of the channel region.
6. The thin film transistor according to claim 1,
the first region is the source region;
the second region is the drain region.
7. The thin film transistor according to claim 1,
the material of the active layer is metal oxide.
8. A method for manufacturing a thin film transistor includes:
providing a substrate;
forming a semiconductor layer on the substrate; wherein the semiconductor layer includes a source region, a channel region, and a drain region; the thickness of a first region of the source region adjacent to the channel region is smaller than that of the channel region; and/or the thickness of a second region of the drain region, which is adjacent to the channel region, is smaller than that of the channel region;
forming an insulating layer on one side of the semiconductor layer far away from the substrate;
forming a gate electrode layer on one side of the insulating layer away from the substrate;
and implanting ions into the semiconductor layer by taking the gate electrode layer as a mask to form an active layer which is provided with a channel region and a source region and a drain region which are arranged at two sides of the channel region.
9. The method of manufacturing a thin film transistor according to claim 8, wherein the forming a semiconductor layer over the substrate includes:
forming a semiconductor material layer on the substrate;
forming a photoresist layer on one side of the semiconductor material layer far away from the substrate;
patterning the photoresist layer;
and etching the semiconductor material layer to form a semiconductor layer.
10. A display panel comprising the thin film transistor according to any one of claims 1 to 7.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102483A (en) * | 1991-10-09 | 1993-04-23 | Sharp Corp | Film transistor and its manufacturing method |
| US6013929A (en) * | 1997-07-08 | 2000-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor, having a nitride film on the gate insulation layer and an organic resin interlayer film on the transistor |
| WO2016038823A1 (en) * | 2014-09-10 | 2016-03-17 | 株式会社Ｊｏｌｅｄ | Thin film transistor and thin film transistor manufacturing method |
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2021
- 2021-04-26 CN CN202110452733.9A patent/CN113161423B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102483A (en) * | 1991-10-09 | 1993-04-23 | Sharp Corp | Film transistor and its manufacturing method |
| US6013929A (en) * | 1997-07-08 | 2000-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor, having a nitride film on the gate insulation layer and an organic resin interlayer film on the transistor |
| WO2016038823A1 (en) * | 2014-09-10 | 2016-03-17 | 株式会社Ｊｏｌｅｄ | Thin film transistor and thin film transistor manufacturing method |
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