WO2016038823A1

WO2016038823A1 - Thin film transistor and thin film transistor manufacturing method

Info

Publication number: WO2016038823A1
Application number: PCT/JP2015/004291
Authority: WO
Inventors: 光正松本
Original assignee: 株式会社Ｊｏｌｅｄ
Priority date: 2014-09-10
Filing date: 2015-08-26
Publication date: 2016-03-17

Abstract

A thin film transistor (1) has: a substrate (10); an oxide semiconductor layer (30), which is positioned above the substrate (10), and which has a channel region, a source region, and a drain region; a gate insulating layer (40) positioned above the oxide semiconductor layer (30); a gate electrode (50) positioned above the gate insulating layer (40); a source electrode (70S) electrically connected to the source region; and a drain electrode (70D) electrically connected to the drain region. The channel region is a region facing the gate electrode (50) by having the gate insulating layer (40) therebetween, the drain region is a region, which is positioned on the one end side of the channel region, and which has a resistance value that is lower than that of the channel region, and the source region is a region, which is positioned on the other end side of the channel region, and which has a resistance value that is lower than that of the channel region. In the oxide semiconductor layer (30), the thickness of at least a boundary portion between the drain region and the channel region is less than the thickness of the channel region.

Description

THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR

The present invention relates to a thin film transistor (TFT: Thin Film Transistor) and a method for manufacturing the thin film transistor, and more particularly to an oxide semiconductor thin film transistor having an oxide semiconductor layer as a channel layer and a method for manufacturing the same.

TFTs are used as switching elements or drive elements in active matrix display devices such as liquid crystal display devices or organic EL (Electro Luminescence) display devices.

In recent years, oxide semiconductor TFTs using an oxide semiconductor such as InGaZnO _x (IGZO) as a channel layer have been actively developed as next-generation TFTs. For example, Patent Document 1 discloses an oxide semiconductor TFT whose channel layer is an oxide semiconductor layer. Oxide semiconductor TFTs have already been put into practical use and are used in mobile small display devices and large display devices.

JP 2010-161227 A

The oxide semiconductor TFT has a problem that the threshold voltage (Vth) shifts as the channel length becomes shorter.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a thin film transistor capable of suppressing fluctuations in threshold voltage and a method for manufacturing the same.

In order to achieve the above object, a thin film transistor according to one embodiment of the present invention includes a substrate, an oxide semiconductor layer that is located above the substrate and includes a channel region, a source region, and a drain region, and the oxide semiconductor layer A gate insulating layer located above the gate insulating layer; a gate electrode located above the gate insulating layer; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region; The channel region is a region facing the gate electrode across the gate insulating layer, the drain region is located on the other end side of the channel region, and the resistance value is the channel The source region is located on one end side of the channel region, and the resistance value is lower than the resistance value of the channel region. A region in the oxide semiconductor layer, the thickness of the boundary portion between at least said drain region and said channel region is equal to or smaller than the thickness of the channel region.

A thin film transistor that can suppress fluctuations in threshold voltage can be realized.

FIG. 1 is a cross-sectional view illustrating a configuration of a thin film transistor according to an embodiment. FIG. 2 is a diagram for explaining the short channel effect in the oxide semiconductor TFT. FIG. 3 is a diagram illustrating a relationship between a step in the oxide semiconductor layer of the thin film transistor according to the embodiment and Vth variation. FIG. 4A is a cross-sectional view of a substrate preparation step in the method of manufacturing a thin film transistor according to the embodiment. FIG. 4B is a cross-sectional view of the undercoat layer forming step in the method for manufacturing the thin film transistor according to the embodiment. FIG. 4C is a cross-sectional view of the oxide semiconductor layer forming step in the method for manufacturing the thin film transistor according to the embodiment. FIG. 4D is a cross-sectional view of the step of forming the gate insulating layer and the gate electrode in the method for manufacturing the thin film transistor according to the embodiment. FIG. 4E is a cross-sectional view of the oxide semiconductor layer etching step in the method for manufacturing the thin film transistor according to the embodiment. FIG. 4F is a cross-sectional view of an acceptor element adsorption step in the method of manufacturing a thin film transistor according to the embodiment. FIG. 4G is a cross-sectional view of an acceptor element diffusion step in the method for manufacturing a thin film transistor according to the embodiment. FIG. 4H is a cross-sectional view of the step of forming the source region and the drain region of the oxide semiconductor layer in the method for manufacturing the thin film transistor according to the embodiment. FIG. 4I is a cross-sectional view of the insulating layer forming step in the method for manufacturing the thin film transistor according to the embodiment. FIG. 4J is a cross-sectional view of the source electrode and drain electrode formation step in the method of manufacturing a thin film transistor according to the embodiment. FIG. 5 is a partially cutaway perspective view of the organic EL display device according to the embodiment. FIG. 6 is an electric circuit diagram of a pixel circuit in the organic EL display device shown in FIG. FIG. 7 is a cross-sectional view illustrating a configuration of a thin film transistor according to the first modification. FIG. 8 is a cross-sectional view illustrating a configuration of a thin film transistor according to the second modification. FIG. 9 is a cross-sectional view illustrating a configuration of a thin film transistor according to Modification 3. FIG. 10A is a cross-sectional view illustrating a configuration of a thin film transistor according to Modification 4. FIG. 10B is a cross-sectional view illustrating another configuration of the thin film transistor according to Modification 4.

A thin film transistor according to one embodiment of the present invention includes a substrate, an oxide semiconductor layer located above the substrate and having a channel region, a source region, and a drain region, and a gate insulating layer located above the oxide semiconductor layer A gate electrode located above the gate insulating layer, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region, and the channel region Is a region facing the gate electrode across the gate insulating layer, the drain region is located on the other end side of the channel region, and the resistance value is lower than the resistance value of the channel region The source region is located on one end side of the channel region and has a resistance value lower than the resistance value of the channel region; In the body layer, the thickness of the boundary portion between at least said drain region and said channel region is thinner than the thickness of the channel region.

According to this aspect, in the oxide semiconductor layer, the thickness of the boundary portion between the drain region (low resistance region) and the channel region is thinner than the thickness of the channel region. Thereby, since the physical distance between the drain region and the channel region can be increased, the drain electric field can be blunted. Therefore, it is possible to suppress fluctuations in the threshold voltage caused by shortening the channel.

In the thin film transistor according to one embodiment of the present invention, in the oxide semiconductor layer, a thickness of a boundary portion between the source region and the channel region may be smaller than a thickness of the channel region.

According to this aspect, the thickness of the boundary portion between the drain region and the channel region and the thickness of the boundary portion between the source region and the channel region can be simultaneously reduced.

In the thin film transistor according to one embodiment of the present invention, the oxide semiconductor layer has a convex cross-sectional shape, and an upper surface of the portion having the channel region includes the portion having the drain region and the source region. It is good to be located above the upper surface of the part.

According to this embodiment, the thickness of the portion having the drain region and the portion having the source region in the oxide semiconductor layer is set to a constant thickness, and the thickness of the portion having the channel region in the oxide semiconductor layer is Can also be thinned. Accordingly, for example, by etching the oxide semiconductor layer using the gate electrode as a mask, the film thickness of the portion corresponding to the drain region and the portion corresponding to the source region can be simultaneously processed and reduced.

In the thin film transistor according to one embodiment of the present invention, the oxide semiconductor layer includes, in the channel region, a first region that is a region on the source region side and the drain region side, and the channel more than the first region. And a second region which is a region closer to the center of the region, and the carrier density of the first region is preferably lower than the carrier density of the second region.

According to this aspect, the carrier density in the drain end direction in the channel region of the oxide semiconductor layer can be reduced. As a result, the drain voltage can be made insensitive, so that fluctuations in the threshold voltage due to the shortening of the channel can be further suppressed.

In the thin film transistor according to one embodiment of the present invention, the first region may include an element that functions as an acceptor.

According to this aspect, the carrier density in the oxide semiconductor layer can be stably reduced.

In the thin film transistor according to one embodiment of the present invention, the first region preferably includes at least one of copper, silicon, and fluorine as the acceptor.

According to this aspect, the consistency with the large-scale mass production equipment becomes high, so that the manufacturing cost can be suppressed.

In the thin film transistor according to one embodiment of the present invention, the contact point between the upper end portion of the source region or the drain region and the lower end portion of the side surface of the channel region is more than a position that is 1/2 the thickness of the channel region. It may be located on the lower side.

According to this aspect, since a sufficient distance can be taken between the electric field distribution formed in the drain region and the carrier path generated in the channel region (front channel region), the threshold voltage fluctuation due to the shortening of the channel can be reduced. It can suppress more effectively.

In the thin film transistor according to one embodiment of the present invention, the difference between the contact between the upper end of the source region or the drain region and the lower end of the side surface of the channel region and the upper surface of the channel region is at least 15 nm or more. It is good to be.

According to this aspect, it is possible to effectively suppress the fluctuation of the threshold voltage due to the shortening of the channel.

In the thin film transistor according to one embodiment of the present invention, the metal element included in the oxide semiconductor layer may include at least one of indium, gallium, and zinc.

According to this aspect, since the target consistency with the large-scale mass production facility is increased, the manufacturing cost can be suppressed.

In addition, a method for manufacturing a thin film transistor according to one embodiment of the present invention includes a step of preparing a substrate, a step of forming an oxide semiconductor layer having a channel region above the substrate, and a region above the oxide semiconductor layer. A step of forming a gate insulating layer; a step of forming a gate electrode above the gate insulating layer; a step of forming a source region and a drain region in the oxide semiconductor layer; and electrically connected to the source region. Forming a source electrode and a drain electrode electrically connected to the drain region, wherein the channel region is a region facing the gate electrode with the gate insulating layer interposed therebetween, and the source region is The drain region is located on one end side of the channel region and has a resistance value lower than the resistance value of the channel region. The region is located on the other end side of the region and has a resistance value lower than the resistance value of the channel region, and at least the boundary portion between the drain region and the channel region has a thickness greater than the thickness of the channel region. A step of processing the oxide semiconductor layer so as to be thin.

According to this aspect, it is possible to form an oxide semiconductor layer in which the thickness of the boundary portion between the drain region and the channel region, which is a low resistance region, is thinner than the thickness of the channel region. Accordingly, since a physical distance between the drain region and the channel region can be increased, a thin film transistor that can suppress a variation in threshold voltage due to a short channel can be manufactured.

In addition, a method for manufacturing a thin film transistor according to another embodiment of the present invention includes a step of preparing a substrate, a step of forming an oxide semiconductor layer over the substrate, and a gate insulating film over the oxide semiconductor layer. Forming a gate electrode having a predetermined shape above the gate insulating film, and forming a gate insulating layer having a predetermined shape by etching the gate insulating film using the gate electrode as a mask, Etching the part of the oxide semiconductor layer using the gate electrode as a mask to thin the part of the oxide semiconductor layer; and the source region and the drain region in the part of the oxide semiconductor layer And forming a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region.

According to this aspect, since the gate electrode can be used as a mask and the oxide semiconductor layer can be thinned by etching the source region and the drain region, the thin film transistor can be manufactured without increasing the number of manufacturing steps.

In the method for manufacturing a thin film transistor according to another aspect of the present invention, the carrier density of the first region, which is the region on the source region side and the drain region side, in the channel region is higher than that in the first region. It is preferable to include a step of diffusing an element acting as an acceptor into the channel region so as to be lower than the carrier density of the second region which is a region closer to the center of the channel region.

According to this embodiment, by diffusing an element that acts as an acceptor into the channel region of the oxide semiconductor layer, the carrier density in the channel path direction is reduced with respect to the oxide semiconductor layer so that the carrier density in the drain end direction is low. Distribution can be given.

In the thin film transistor according to another embodiment of the present invention, in the channel region, a carrier density of a first region that is a region on the source region side and the drain region side is higher than that in the first region. It is preferable to include a step of diffusing an element acting as an acceptor into the channel region so as to be lower than the carrier density of the second region, which is a region closer to the center of the channel region.

According to this aspect, since the acceptor element can be easily introduced into the oxide semiconductor layer from the side surface portion of the channel region, the carrier density at the drain end in the channel region can be easily reduced.

(Embodiment)
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present invention. Therefore, numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps (steps), order of steps, and the like shown in the following embodiments are merely examples and are intended to limit the present invention. is not. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements.

Each figure is a schematic diagram and is not necessarily shown strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.

[Configuration of thin film transistor]
First, a thin film transistor 1 according to an embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view illustrating a configuration of a thin film transistor according to an embodiment.

As shown in FIG. 1, a thin film transistor 1 according to this embodiment is a top-gate oxide semiconductor TFT having an oxide semiconductor layer as a channel layer.

The thin film transistor 1 includes a substrate 10, an undercoat layer 20, an oxide semiconductor layer 30 serving as a channel layer, a gate insulating layer 40, a gate electrode 50, an interlayer insulating layer 60, a source electrode 70S, and a drain electrode 70D. Is provided.

Hereinafter, each component of the thin film transistor 1 according to the present embodiment will be described in detail.

The substrate 10 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, or high heat resistant glass. The substrate 10 is not limited to a glass substrate but may be a resin substrate or the like. Moreover, the board | substrate 10 may be a flexible substrate comprised not with a rigid board | substrate but with the single layer or lamination | stacking of film materials, such as a polyimide, a polyethylene terephthalate, and a polyethylene naphthalate.

The undercoat layer 20 is an example of an inorganic layer disposed on the substrate 10. The undercoat layer 20 is formed on the upper surface of the substrate 10. In the present embodiment, the undercoat layer 20 is formed on the surface of the substrate 10 (the side on which the oxide semiconductor layer is formed). By forming the undercoat layer 20, impurities such as sodium and phosphorus contained in the substrate 10 (glass substrate) or moisture transmitted from the atmosphere can be prevented from entering the oxide semiconductor layer 30.

The undercoat layer 20 is a single-layer insulating layer or a laminated insulating layer using an oxide insulating layer or a nitride insulating layer. As an example, the undercoat layer 20 includes a single layer film such as silicon nitride (SiNx), silicon oxide (SiO _y ), silicon oxynitride (SiO _y N _x ), or aluminum oxide (AlO _x ), or a laminate thereof. A membrane can be used. In the present embodiment, the undercoat layer 20 is a laminated film configured by laminating a plurality of insulating films. The film thickness of the undercoat layer 20 is preferably set to 100 nm to 500 nm.

The oxide semiconductor layer 30 is used as a channel layer. That is, the oxide semiconductor layer 30 is a semiconductor layer including a channel region which is a region facing the gate electrode 50 with the gate insulating layer 40 interposed therebetween. In addition to the channel region, the oxide semiconductor layer 30 further includes a source region and a drain region.

Specifically, the oxide semiconductor layer 30 includes a first oxide semiconductor layer 31 including a channel region, a second oxide semiconductor layer 32 including a drain region, and a third oxide semiconductor layer 33 including a source region. It is configured.

The channel region (front channel region) is formed at least in the upper layer portion of the first oxide semiconductor layer 31 on the gate electrode 50 side, but is also formed in the lower layer portion of the first oxide semiconductor layer 31 on the substrate 10 side. In some cases.

The drain region in the second oxide semiconductor layer 32 and the source region in the third oxide semiconductor layer 33 are low resistance regions (offset regions) having a lower resistance value than the first oxide semiconductor layer 31 (channel region). . The drain region and the source region can be formed by reducing the resistance of the oxide semiconductor film by performing plasma irradiation with argon (Ar), hydrogen (H), or the like, or causing oxygen vacancies by heating.

The second oxide semiconductor layer 32 is a portion located on one side of the first oxide semiconductor layer 31 in the oxide semiconductor layer 30. Therefore, the drain region in the second oxide semiconductor layer 32 is located on one end side of the first oxide semiconductor layer 31 (channel region).

On the other hand, the third oxide semiconductor layer 33 is a portion located on the other side of the first oxide semiconductor layer 31 in the oxide semiconductor layer 30. Therefore, the source region in the third oxide semiconductor layer 33 is located on the other end side of the first oxide semiconductor layer 31 (channel region).

As a material of the oxide semiconductor layer 30, for example, a transparent amorphous oxide semiconductor (TAOS: Transparent Amorphous Oxide Semiconductor) is used. The metal element included in the oxide semiconductor layer 30 contains at least indium (In), and preferably contains at least one or both of gallium (Ga) and zinc (Zn).

The oxide semiconductor layer 30 in this embodiment includes InGaZnOx (IGZO) which is an oxide containing indium (In), gallium (Ga), and zinc (Zn). That is, the first oxide semiconductor layer 31, the second oxide semiconductor layer 32, and the third oxide semiconductor layer 33 are made of the same material, and are made of IGZO in this embodiment.

Further, the first oxide semiconductor layer 31 in this embodiment includes a channel region (front channel region) in the second oxide semiconductor layer 32 side (drain region side) and the third oxide semiconductor layer 33 side (source region). Side region) and a second region 31b that is closer to the center of the channel region than the first region 31a. That is, the central region of the channel region is the second region 31b, and the regions on both sides of the second region 31b (central portion) in the channel region are the first region 31a.

The first region 31a contains an element that has an effect of reducing the carrier density, that is, an element that acts as an acceptor in the channel region. Thereby, the carrier density of the first region 31a is lower than the carrier density of the second region 31b. That is, in the channel region of the first oxide semiconductor layer 31, the carrier density is lower at both sides (drain end and source end) than at the center, and the carrier density at the drain end and source end is lower. It has a carrier density distribution in the channel path direction.

Examples of the element that acts as an acceptor include copper, silicon (silicon), and fluorine. That is, the first region 31a contains at least one of copper, silicon (silicon), and fluorine.

For example, the first region 31a having a carrier density lower than that of the second region 31b can be lowered by diffusing and introducing fluorine, silicon, or copper into the portion of the oxide semiconductor layer 30 that becomes the first region 31a. In the present embodiment, fluorine is introduced into the first region 31a.

The oxide semiconductor layer 30 is formed so as to be located above the substrate 10. The oxide semiconductor layer 30 in the present embodiment is formed in a predetermined shape on the undercoat layer 20.

In the oxide semiconductor layer 30, at least the thickness of the boundary between the drain region and the channel region is smaller than the thickness of the channel region. In the present embodiment, the thickness of the boundary portion between the source region and the channel region is further thinner than the thickness of the channel region.

Specifically, the oxide semiconductor layer 30 is formed so that the cross-sectional shape is convex and the upper surface of the channel region is located above the upper surfaces of the drain region and the source region. More specifically, the thickness of each of the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 is smaller than the thickness of the first oxide semiconductor layer 31, and the first oxide semiconductor layer The upper surface of 31 is located above the upper surfaces of the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33. That is, a step is formed between the first oxide semiconductor layer 31, the second oxide semiconductor layer 32, and the third oxide semiconductor layer 33.

Therefore, the side surface of the upper layer portion of the first oxide semiconductor layer 31 is exposed and is in contact with the interlayer insulating layer 60. Specifically, the first region 31 a of the first oxide semiconductor layer 31 is in contact with the interlayer insulating layer 60.

The gate insulating layer 40 (insulating layer) is formed at a position facing the undercoat layer 20 with the oxide semiconductor layer 30 interposed therebetween. Specifically, the gate insulating layer 40 is located above the oxide semiconductor layer 30, and is formed on the oxide semiconductor layer 30, for example.

In the present embodiment, the gate insulating layer 40 is formed on the first oxide semiconductor layer 31 in the oxide semiconductor layer 30. Specifically, the side surface of the gate insulating layer 40 is flush with the side surface of the first oxide semiconductor layer 31, and when viewed from above, the contour line of the gate insulating layer 40 and the contour line of the first oxide semiconductor layer 31 are Are consistent. Note that although the gate insulating layer 40 is formed only over the oxide semiconductor layer 30 in this embodiment, the present invention is not limited thereto.

The gate insulating layer 40 is a single-layer insulating layer or a stacked insulating layer using an oxide insulating layer or a nitride insulating layer. As the gate insulating layer 40, a single layer film such as silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide, or aluminum oxide, or a laminated film of these can be used. In the present embodiment, the gate insulating layer 40 is, for example, a stacked film of a silicon oxide film and a silicon nitride film. The film thickness of the gate insulating layer 40 can be designed in consideration of the breakdown voltage of the TFT, and is preferably 50 nm to 500 nm, for example.

The gate electrode 50 is formed at a position facing the oxide semiconductor layer 30 with the gate insulating layer 40 interposed therebetween. Specifically, the gate electrode 50 is located above the gate insulating layer 40, and is patterned in a predetermined shape on the gate insulating layer 40, for example. In the present embodiment, the length of the gate electrode 50 in the channel direction (gate length) and the length of the gate insulating layer 40 in the channel direction are the same. Specifically, the side surface of the gate electrode 50 is flush with the side surface of the gate insulating layer 40, and the outline of the gate electrode 50 and the outline of the gate insulating layer 40 coincide with each other when viewed from above.

The gate electrode 50 is an electrode having a single layer structure or a multilayer structure such as a conductive material such as a metal or an alloy thereof. For example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), chromium (Cr), molybdenum tungsten (MoW), or the like. The film thickness of the gate electrode 50 is preferably set to 50 nm to 300 nm.

The interlayer insulating layer 60 is formed so as to cover the gate electrode 50 and the oxide semiconductor layer 30. Specifically, the interlayer insulating layer 60 is formed so as to cover the gate electrode 50 and the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 that are exposed from the gate electrode 50 in the oxide semiconductor layer 30. The

The interlayer insulating layer 60 may be formed of a material mainly composed of an organic substance, or may be formed of an inorganic substance such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The interlayer insulating layer 60 may be a single layer film or a laminated film.

Further, a plurality of openings (contact holes) are formed in the interlayer insulating layer 60 so as to penetrate a part of the interlayer insulating layer 60. Through the opening of the interlayer insulating layer 60, the second oxide semiconductor layer 32 and the drain electrode 70D are connected, and the third oxide semiconductor layer 33 and the source electrode 70S are connected.

The source electrode 70S and the drain electrode 70D are formed on the interlayer insulating layer 60 in a predetermined shape. Each of the source electrode 70 S and the drain electrode 70 D is electrically connected to the oxide semiconductor layer 30.

In the present embodiment, the drain electrode 70D is electrically and physically connected to the drain region of the second oxide semiconductor layer 32 through an opening formed in the interlayer insulating layer 60. On the other hand, the source electrode 70 S is electrically and physically connected to the source region of the third oxide semiconductor layer 33 through an opening formed in the interlayer insulating layer 60.

The source electrode 70S and the drain electrode 70D are electrodes having a single layer structure or a multilayer structure such as a conductive material or an alloy thereof. Examples of the material of the source electrode 70S and the drain electrode 70D include molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), chromium (Cr), and molybdenum tungsten alloy (MoW). Alternatively, a copper manganese alloy (CuMn) or the like can be used. The film thickness of the source electrode 70S and the drain electrode 70D is preferably set to, for example, 50 nm to 300 nm.

[Operational effect of thin film transistor]
Next, functions and effects of the thin film transistor 1 according to this embodiment will be described including the background to the arrival of one embodiment of the present invention.

Conventionally, a silicon semiconductor TFT using a silicon semiconductor as a channel layer is mainly used in a display device. In recent years, a display device using an oxide semiconductor TFT using an oxide semiconductor such as IGZO as a channel layer has been put into practical use.

With the recent high definition of display devices, it is required to shorten the channel length (short channel) in oxide semiconductor TFTs as well as silicon semiconductor TFTs. For example, the channel length is required to be 10 μm or less.

However, when the channel length is shortened in the oxide semiconductor TFT, electrical characteristics are deteriorated (short channel effect). When an oxide semiconductor TFT having a channel length of the order of several μm was actually manufactured, it was found that the threshold voltage (Vth) fluctuated. Specifically, it has been found that in the oxide semiconductor TFT, the threshold voltage (Vth) shifts negatively as the channel length becomes shorter.

This phenomenon is considered to be because the effect of the depletion layer in the source / drain region cannot be ignored by shortening the channel as in the case of the silicon field effect transistor (MOSFET) formed on the silicon substrate. This phenomenon will be described with reference to FIG. FIG. 2 is a diagram for explaining the short channel effect in the oxide semiconductor TFT.

As shown in FIG. 2, acceptor ions that reduce the surface potential exist in the depletion layer of the oxide semiconductor layer 300. For example, acceptor ions are present evenly near the source region, near the channel region, and near the drain region when the drain voltage (Vd) is about 0 V, but as the drain voltage (Vd) increases, As shown in the enclosed region A, there are many in the vicinity of the drain region.

The acceptor ion has a function of lowering the threshold voltage (Vth). Moreover, when the channel length is shortened, the drain voltage (Vd) substantially increases. As a result, it is considered that the threshold voltage (Vth) shifts negatively as the channel length becomes shorter.

For the short channel effect, in the case of MOSFET, the short channel effect is suppressed by thinning the gate insulating layer. Similarly, in the case of an oxide semiconductor TFT, it is considered that the short channel effect can be suppressed by reducing the thickness of the gate insulating layer. When an oxide semiconductor TFT in which the gate insulating layer was actually thinned was prototyped, it was found that the short channel effect could be suppressed.

However, when the gate insulating layer is thinned in the oxide semiconductor TFT, generation of a tunnel current passing through the gate insulating layer becomes a problem. In addition, when an oxide semiconductor is applied with a high-temperature process (for example, 500 ° C. or higher) due to its characteristics, oxygen deficiency is caused and the oxide semiconductor does not function as a semiconductor. As a result, when the gate insulating layer is thinned, there arises a problem that sufficiently good insulation resistance cannot be obtained.

Therefore, the inventor of the present application diligently studied a method capable of suppressing the short channel effect in the oxide semiconductor TFT by a method different from the method of thinning the gate insulating layer. As a result, the inventor of the present application has found that by changing the carrier density in the channel direction and canceling the depletion layer, the threshold voltage fluctuation (short channel effect) caused by the shortening of the channel can be suppressed.

Specifically, it has been found that the short channel effect can be suppressed by making the thickness of at least the boundary between the drain region and the channel region thinner than the thickness of the channel region in the oxide semiconductor layer that becomes the channel layer of the oxide semiconductor TFT. It was.

In this embodiment, as illustrated in FIG. 1, in the oxide semiconductor layer 30, the thickness of the second oxide semiconductor layer 32 having the drain region is set to the thickness of the first oxide semiconductor layer 31 having the channel region. It is thinner.

Thereby, since the distance between the drain region and the channel region can be increased, the drain region can be separated from the channel region. In this embodiment, since the cross-sectional shape of the oxide semiconductor layer 30 is convex, the drain region can be separated from the channel region by the length of the side wall of the first oxide semiconductor layer 31.

Thus, by separating the drain region from the channel region, the strength of the drain electric field due to the application of the drain voltage (Vd) can be reduced. Thereby, the short channel effect can be suppressed without reducing the ON current. That is, a negative shift of the threshold voltage (Vth) due to the shortening of the channel can be suppressed while maintaining a high ON current.

Further, in the thin film transistor 1 in this embodiment, the channel region in the first oxide semiconductor layer 31 of the oxide semiconductor layer 30 includes the first region 31a having a low carrier density.

Thereby, in the carrier region of the oxide semiconductor layer 30 (first oxide semiconductor layer 31), the carrier density distribution can be provided in the channel path direction so that the carrier density in the drain end direction is lowered. Therefore, since it can be insensitive to the drain voltage, the short channel effect can be further suppressed.

Here, a step in the oxide semiconductor layer 30 (a portion where the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 are lower than the first oxide semiconductor layer 31) and Vth variation (threshold voltage fluctuation). ) Will be described with reference to FIG. FIG. 3 is a diagram illustrating a relationship between a step in the oxide semiconductor layer of the thin film transistor according to the embodiment and Vth variation. Note that FIG. 3 shows Vth variation of the thin film transistor when the thickness of the first oxide semiconductor layer 31 is 30 nm, 60 nm, and 80 nm.

As shown in FIG. 3, the step of the oxide semiconductor layer 30, that is, the step between the first oxide semiconductor layer 31, the second oxide semiconductor layer 32, and the third oxide semiconductor layer 33 is increased. , Vth variation can be reduced. That is, the difference between the upper surface of the first oxide semiconductor layer 31 and the upper surface of the second oxide semiconductor layer 32 or the third oxide semiconductor layer 33 (the second oxide semiconductor layer 32 or the third oxide in the oxide semiconductor layer 30). By increasing the digging amount of the physical semiconductor layer 33, the Vth variation can be reduced.

In particular, it can be seen that Vth variation can be greatly reduced by setting this step to 15 nm or more. That is, the top end of each of the second oxide semiconductor layer 32 (drain region) and the third oxide semiconductor layer 33 (source region) and the bottom end of the side surface of the first oxide semiconductor layer 31 (channel region). When the difference (step) between the contact and the upper surface of the first oxide semiconductor layer 31 (channel region) is at least 15 nm or more, Vth variation can be greatly reduced. As a result, it is possible to effectively suppress the fluctuation of the threshold voltage due to the shortening of the channel.

Further, as shown by the data of the three broken circles in FIG. 3, the thickness of each of the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 is ½ of the thickness of the first oxide semiconductor layer 31. By doing so, it can be seen that the effect of reducing Vth variation is saturated. That is, the upper end of each of the second oxide semiconductor layer 32 (drain region) and the third oxide semiconductor layer 33 (source region) and the lower end of the side surface of the first oxide semiconductor layer 31 (channel region). By configuring the contact so that it is located below the half of the thickness of the first oxide semiconductor layer 31 (channel region), the effect of reducing Vth variation is saturated. Therefore, the thickness of each of the second oxide semiconductor layer 32 (drain region) and the third oxide semiconductor layer 33 (source region) is set to be 1/2 or more of the thickness of the first oxide semiconductor layer 31, thereby reducing the thickness. Variation in threshold voltage due to channelization can be effectively suppressed.

Note that the level difference between the first oxide semiconductor layer 31, the second oxide semiconductor layer 32, and the third oxide semiconductor layer 33, that is, the digging amount of the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 is increased. If it is too much, the process time for forming this step becomes long, or the conductive oxide residue generated when the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 are shaved causes an interlayer at the wiring intersection. A short circuit may occur. Accordingly, it is preferable that the step between the first oxide semiconductor layer 31, the second oxide semiconductor layer 32, and the third oxide semiconductor layer 33 is not too large.

[Thin Film Transistor Manufacturing Method]
Next, a method for manufacturing the thin film transistor 1 according to the present embodiment will be described with reference to FIGS. 4A to 4J. 4A to 4J are cross-sectional views of each step in the method of manufacturing the thin film transistor according to the embodiment.

First, as shown in FIG. 4A, a substrate 10 is prepared. For example, a glass substrate is prepared as the substrate 10.

Next, as shown in FIG. 4B, an undercoat layer 20 is formed on the substrate 10. For example, the undercoat layer 20 composed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like is formed on the substrate 10 by plasma CVD (Chemical Vapor Deposition) or the like.

Next, as illustrated in FIG. 4C, the oxide semiconductor layer 30 X is formed over the substrate 10. In this embodiment, the oxide semiconductor layer 30X having a predetermined shape is formed over the undercoat layer 20. As a material of the oxide semiconductor layer 30X, a transparent amorphous oxide semiconductor of InGaZnO _x can be used.

In this case, first, an oxide semiconductor film (InGaZnO _x film) made of InGaZnO _x by vapor deposition such as sputtering and laser deposition. Specifically, using a target material containing In, Ga and Zn (for example, a polycrystalline sintered body having a composition of InGaO ₃ (ZnO) ₄ ), argon (Ar) gas flows as an inert gas into the vacuum chamber. At the same time, a gas containing oxygen (O ₂ ) is introduced as a reactive gas, and a voltage having a predetermined power density is applied to the target material.

Then, by patterning the oxide semiconductor film using a photolithography method and a wet etching method, the oxide semiconductor layer 30X processed into a predetermined shape can be formed as illustrated in FIG. 4C. Note that as the etching solution, for example, a chemical solution in which phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed can be used.

Next, as illustrated in FIG. 4D, the gate insulating layer 40 is formed above the oxide semiconductor layer 30X, and the gate electrode 50 is formed above the gate insulating layer 40. Specifically, the gate insulating layer 40 and the gate electrode 50 are formed over a predetermined region of the oxide semiconductor layer 30X.

In this case, first, a gate insulating film is formed so as to cover the oxide semiconductor layer 30X. The gate insulating film is, for example, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, a tantalum oxide film, a single layer film of an aluminum oxide film, or a laminated film in which these films are stacked. In this embodiment, a silicon oxide film is formed by plasma CVD as the gate insulating film.

Thereafter, a gate metal film is formed on the gate insulating film. In this embodiment, a metal film made of molybdenum tungsten (MoW) is formed by sputtering as the gate metal film.

Next, by patterning the gate metal film using a photolithography method and a wet etching method, a gate electrode 50 having a predetermined shape is formed on the gate insulating film above the oxide semiconductor layer 30X. The wet etching of the gate metal film made of MoW can be performed using, for example, a chemical solution in which phosphoric acid (HPO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed in a predetermined composition.

Thereafter, the gate insulating layer 40 having a predetermined shape is formed by patterning the gate insulating film. For example, the gate insulating layer 40 having the same shape as the gate electrode 50 can be formed between the oxide semiconductor layer 30X and the gate electrode 50 by patterning the gate insulating film using the gate electrode 50 as a mask.

In this embodiment, the gate insulating film and the gate metal film are formed over the entire surface, the gate metal film is patterned, and then the gate insulating film is patterned, whereby the gate insulating layer 40 and the gate electrode having a predetermined shape are formed. Although the laminated structure with 50 was formed, it is not restricted to this. For example, after forming a gate insulating film, the gate insulating film is once patterned to form a gate insulating layer 40 having a predetermined shape, and then a gate metal film is formed and the gate metal film is patterned to form a predetermined shape. The gate electrode 50 may be formed.

Next, the oxide semiconductor layer 30X is processed so that at least the boundary portion between the drain region and the channel region is thinner than the thickness of the channel region. In this embodiment, as illustrated in FIG. 4E, part of the oxide semiconductor layer 30X is thinned by etching part of the oxide semiconductor layer 30X using the gate electrode 50 as a mask. That is, by etching a portion of the oxide semiconductor layer 30X that is exposed from the gate electrode 50, the thickness of the exposed portion is reduced.

Specifically, the oxide semiconductor layer 30X is processed into a convex shape by etching portions other than the portions covered with the gate electrode 50 and the gate insulating layer 40 of the oxide semiconductor layer 30X.

In this case, the etching may be either a wet process (wet etching) or a dry process (dry etching). In the case of a wet process, for example, a chemical solution in which phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed can be used as the etching solution. In the case of a dry process, for example, boron tetrachloride (BCl ₃ ) can be used as an etching gas.

Note that the etching process of the oxide semiconductor layer 30X and the etching process of the gate insulating film may be performed in the same process.

Next, in the channel region of the oxide semiconductor layer 30X, the carrier density in the first region adjacent to the source region and the drain region is lower than the carrier density in the second region closer to the center of the channel region than the first region. Thus, an element acting as an acceptor (acceptor element) is diffused into the channel region.

In this embodiment, the step of diffusing the acceptor element includes a step of attaching the acceptor element to at least a side surface portion of the channel region in the oxide semiconductor layer, and a step of heating thereafter.

Specifically, first, an acceptor element is attached to at least a side surface portion of the oxide semiconductor layer 30X which becomes a channel region. For example, as shown in FIG. 4F, the acceptor element is attached to the entire surface of the substrate 10 so that the acceptor element is adsorbed to the exposed portion of the oxide semiconductor layer 30X, and the acceptor element-containing layer (acceptor element-containing layer) 80 is formed. Form.

As the acceptor element, for example, fluorine (F), silicon (Si), copper (Cu), or the like can be used. As a process for attaching the acceptor element, for example, a process for forming a thin film such as CVD or sputtering, a thermal process using an interfacial reaction obtained by raising the substrate temperature, or the like can be used. In this embodiment, fluorine is used as an acceptor element, and the fluorine is attached to the oxide semiconductor layer 30X by heat.

Subsequently, as shown in FIG. 4G, thermal acceptor is applied to diffuse the acceptor element into the portion that becomes the channel region of the oxide semiconductor layer 30X. Specifically, the acceptor element contained in the acceptor element-containing layer 80 is diffused and introduced into the oxide semiconductor layer 30X by thermal annealing. The annealing temperature is preferably 300 ° C. or higher, for example.

The first oxide semiconductor layer 31 having the first region 31a having a carrier density lower than that of the second region 31b on both sides of the second region 31b can be formed by performing the thermal annealing in this way. In other words, the carrier density distribution can be provided in the channel path direction in the convex portion of the oxide semiconductor layer 30 (the first oxide semiconductor layer 31).

In this embodiment, the annealing temperature is set to 350 ° C. In addition, it was confirmed that the acceptor element (fluorine) was diffused from the exposed surface of the oxide semiconductor layer 30X to a depth of several tens of nm by thermal annealing at 350 ° C.

In addition, when the acceptor element-containing layer 80 remains on the surface of the oxide semiconductor layer 30X, the gate electrode 50, the undercoat layer 20, or the like, a step for removing the acceptor element-containing layer 80 is added as necessary. May be.

Next, a source region and a drain region are formed in the oxide semiconductor layer 30X. In this embodiment, as illustrated in FIG. 4H, a process of selectively reducing the resistance value of a predetermined region of the oxide semiconductor layer 30X that is not covered with the gate electrode 50 and the gate insulating layer 40 (resistance reduction process). By performing the steps, the convex oxide semiconductor layer 30X is formed into a first oxide semiconductor layer 31 including a channel region, a second oxide semiconductor layer 32 including a source region, and a third oxide semiconductor layer 33 including a drain region. Separate functions. Accordingly, the oxide semiconductor layer 30 including the first oxide semiconductor layer 31, the second oxide semiconductor layer 32, and the third oxide semiconductor layer 33 can be formed.

Specifically, plasma irradiation is performed on the oxide semiconductor layer 30X in which the gate electrode 50 is partially formed. In other words, the oxide semiconductor layer 30X is irradiated with plasma using the gate electrode 50 as a mask. Accordingly, plasma is irradiated to a portion of the oxide semiconductor layer 30X exposed from the gate electrode 50, and a portion of the oxide semiconductor layer 30X that is not exposed from the gate electrode 50 is not irradiated with plasma. Only the portion of 30X irradiated with plasma (the portion exposed from the gate electrode 50) is selectively reduced in resistance.

More specifically, the portion of the oxide semiconductor layer 30X that is covered with the gate electrode 50 and is not irradiated with plasma (center portion) becomes the first oxide semiconductor layer 31 without being reduced in resistance. The first oxide semiconductor layer 31 thus formed has a channel region including the first region 31a and the second region 31b having different carrier densities, and has a shape having a carrier density distribution in the carrier path direction. .

On the other hand, portions of the oxide semiconductor layer 30X that are not covered with the gate electrode 50 and are irradiated with plasma (both side portions) are reduced in resistance to become a drain region and a source region. Thus, the second oxide semiconductor layer 32 having a drain region and the third oxide semiconductor layer 33 having a source region can be formed.

In addition, as plasma irradiation, Ar plasma irradiation or hydrogen plasma irradiation can be used, for example. By using these plasma irradiations, the resistance value of the oxide semiconductor stacked film can be sufficiently reduced.

Further, instead of reducing the resistance of the oxide semiconductor layer 30X by plasma irradiation, the resistance of the oxide semiconductor layer 30X may be decreased by causing oxygen deficiency by heating.

Next, as illustrated in FIG. 4I, an interlayer insulating layer 60 is formed so as to cover the exposed portion of the oxide semiconductor layer 30 (the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33) and the gate electrode 50. To do. The interlayer insulating layer 60 may be an organic material as a main component or an inorganic material such as a silicon oxide film. For example, a silicon oxide film can be formed as the interlayer insulating layer 60 by plasma CVD.

Thereafter, an opening (contact hole) is formed in the interlayer insulating layer 60 so that a part of each of the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 is exposed. Specifically, a part of the interlayer insulating layer 60 is removed by etching using a photolithography method and an etching method, so that the third oxide is formed on the drain region (connection portion with the drain electrode 70D) of the second oxide semiconductor layer 32. An opening is formed on the source region (connection portion with the source electrode 70S) of the physical semiconductor layer 33.

For example, when the interlayer insulating layer 60 is a silicon oxide film, the opening can be formed in the silicon oxide film by a dry etching method using a reactive ion etching (RIE) method. In this case, for example, carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ) can be used as the etching gas.

Next, as shown in FIG. 4J, the drain electrode 70D is electrically and physically connected to the second oxide semiconductor layer 32 (drain region) through the opening formed in the interlayer insulating layer 60, and the first The source electrode 70S is electrically and physically connected to the three oxide semiconductor layer 33 (source region).

In this embodiment, after a metal film (source / drain metal film) is formed on the interlayer insulating layer 60 by sputtering so as to fill the opening formed in the interlayer insulating layer 60, a photolithography method and a wet etching method are performed. By using the metal film and patterning, a source electrode 70S and a drain electrode 70D having a predetermined shape are formed.

In addition, although not illustrated, for example, heat treatment (annealing) at 300 ° C. is performed. By this heat treatment, oxygen vacancies in the oxide semiconductor layer 30 can be repaired, and the characteristics of the oxide semiconductor layer 30 can be stabilized.

[Display device]
Next, an example in which the thin film transistor 1 according to the above embodiment is applied to a display device will be described with reference to FIGS. In this embodiment, an application example to an organic EL display device will be described.

FIG. 5 is a partially cutaway perspective view of the organic EL display device according to the embodiment. FIG. 6 is an electric circuit diagram of a pixel circuit in the organic EL display device shown in FIG. Note that the pixel circuit is not limited to the configuration shown in FIG.

The above-described thin film transistor 1 can be used as a switching transistor SwTr and a drive transistor DrTr of an active matrix substrate in an organic EL display device.

As shown in FIG. 5, the organic EL display device 100 includes a TFT substrate (TFT array substrate) 110 on which a plurality of thin film transistors are arranged, an anode 131 as a lower electrode (reflection electrode), and an EL layer (light emitting layer) 132. And a laminated structure with an organic EL element (light emitting part) 130 composed of a cathode 133 which is an upper electrode (transparent electrode).

The thin film transistor 1 described above is used for the TFT substrate 110 in the present embodiment. A plurality of pixels 120 are arranged in a matrix on the TFT substrate 110, and each pixel 120 is provided with a pixel circuit.

The organic EL element 130 is formed corresponding to each of the plurality of pixels 120, and the light emission of each organic EL element 130 is controlled by a pixel circuit provided in each pixel 120. The organic EL element 130 is formed on an interlayer insulating layer (planarization film) formed so as to cover a plurality of thin film transistors.

The organic EL element 130 has a configuration in which an EL layer 132 is disposed between the anode 131 and the cathode 133. A hole transport layer is further laminated between the anode 131 and the EL layer 132, and an electron transport layer is further laminated between the EL layer 132 and the cathode 133. Note that another functional layer may be provided between the anode 131 and the cathode 133. The functional layer formed between the anode 131 and the cathode 133 including the EL layer 132 is an organic layer made of an organic material.

Each pixel 120 is driven and controlled by each pixel circuit. The TFT substrate 110 includes a plurality of gate wirings (scanning lines) 140 arranged along the row direction of the pixels 120 and a plurality of gate wirings 140 arranged along the column direction of the pixels 120 so as to intersect the gate wiring 140. Source wiring (signal wiring) 150 and a plurality of power supply wirings (not shown in FIG. 5) arranged in parallel with the source wiring 150 are formed. Each pixel 120 is partitioned by, for example, an orthogonal gate wiring 140 and a source wiring 150.

The gate wiring 140 is connected to the gate electrode of the switching transistor included in each pixel circuit for each row. The source wiring 150 is connected to the source electrode of the switching transistor for each column. The power supply wiring is connected to the drain electrode of the drive transistor included in each pixel circuit for each column.

As shown in FIG. 6, the pixel circuit includes a switching transistor SwTr, a drive transistor DrTr, and a capacitor C that stores data to be displayed on the corresponding pixel 120. In the present embodiment, the switching transistor SwTr is a TFT for selecting the pixel 120, and the drive transistor DrTr is a TFT for driving the organic EL element 130.

The switching transistor SwTr includes a gate electrode G1 connected to the gate wiring 140, a source electrode S1 connected to the source wiring 150, a drain electrode D1 connected to the capacitor C and the gate electrode G2 of the second thin film transistor DrTr, and an oxidation A physical semiconductor layer (not shown). In the switching transistor SwTr, when a predetermined voltage is applied to the connected gate wiring 140 and source wiring 150, the voltage applied to the source wiring 150 is stored in the capacitor C as a data voltage.

The drive transistor DrTr is connected to the drain electrode D1 of the switching transistor SwTr and the gate electrode G2 connected to the capacitor C, the drain electrode D2 connected to the power supply wiring 160 and the capacitor C, and the anode 131 of the organic EL element 130. A source electrode S2 and an oxide semiconductor layer (not shown) are provided. The drive transistor DrTr supplies a current corresponding to the data voltage held by the capacitor C from the power supply wiring 160 to the anode 131 of the organic EL element 130 through the source electrode S2. Thereby, in the organic EL element 130, a drive current flows from the anode 131 to the cathode 133, and the EL layer 132 emits light.

Note that the organic EL display device 100 having the above configuration employs an active matrix system in which display control is performed for each pixel 120 located at the intersection of the gate wiring 140 and the source wiring 150. Thereby, the corresponding organic EL element 130 selectively emits light by the switching transistor SwTr and the drive transistor DrTr in each pixel 120, and a desired image is displayed.

As described above, in the organic EL display device 100 according to the present embodiment, the thin film transistor 1 in which the short channel effect is suppressed is used as the switching transistor SwTr and the drive transistor DrTr. Therefore, an organic EL display device with excellent reliability can be realized. In particular, since the thin film transistor 1 is used as the drive transistor DrTr for driving the organic EL element 130, a high-definition organic EL display device with excellent display performance can be realized.

(Modification 1)
Next, a thin film transistor 1A according to Modification 1 will be described with reference to FIG. FIG. 7 is a cross-sectional view illustrating a configuration of a thin film transistor according to the first modification.

In the thin film transistor 1 shown in FIG. 1, the entire second oxide semiconductor layer 32 is a drain region and the entire third oxide semiconductor layer 33 is a source region. However, as shown in FIG. In the thin film transistor 1A, only the upper layer portion of the second oxide semiconductor layer 32 is a drain region and only the upper layer portion of the third oxide semiconductor layer 33 is a source region.

Even in the configuration of the thin film transistor 1A in this modification, the distance between the drain region and the channel region can be increased, so that the strength of the drain electric field can be reduced. Thereby, like the thin film transistor 1 in the above embodiment, the short channel effect can be suppressed without reducing the ON current.

(Modification 2)
Next, a thin film transistor 1B according to Modification 2 will be described with reference to FIG. FIG. 8 is a cross-sectional view illustrating a configuration of a thin film transistor according to the second modification.

In the thin film transistor 1 illustrated in FIG. 1, the acceptor element is introduced from the side wall portion of the first oxide semiconductor layer 31 to form the first region 31 a having a low carrier density in the first oxide semiconductor layer 31. Like the thin film transistor 1 B, the first region 31 a is not necessarily formed in the first oxide semiconductor layer 31. That is, the channel density region of the first oxide semiconductor layer 31 may not have a carrier density distribution.

Even in the configuration of the thin film transistor 1B in the present modification, the distance between the drain region and the channel region can be increased, so that the strength of the drain electric field can be reduced. Thereby, like the thin film transistor 1 in the above embodiment, the short channel effect can be suppressed without reducing the ON current.

However, the short channel effect can be effectively suppressed by providing the carrier density distribution in the channel region of the first oxide semiconductor layer 31 as in the thin film transistor 1 shown in FIG.

(Modification 3)
Next, a thin film transistor 1C according to Modification 3 will be described with reference to FIG. FIG. 9 is a cross-sectional view illustrating a configuration of a thin film transistor according to Modification 3.

In the thin film transistor 1 shown in FIG. 1, the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 are formed by thinning both sides of the oxide semiconductor layer 30X using the gate electrode 50 as a mask. Therefore, the entire second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 are thinner than the first oxide semiconductor layer 31. That is, the film thickness of each of the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 is constant and thinner than the film thickness of the first oxide semiconductor layer 31.

On the other hand, in the thin film transistor 1C in the present modification, only a part of the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 is thinned. However, the thickness of the boundary portion between the second oxide semiconductor layer 32 (drain region) and the third oxide semiconductor layer 33 (source region) and the first oxide semiconductor layer 31 (channel region) is the first oxide semiconductor layer. Part of the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 is thinned so as to be thinner than the thickness of 31 (channel region).

Even in the configuration of the thin film transistor 1C in the present modification, the distance between the drain region and the channel region can be increased, so that the strength of the drain electric field can be reduced. Thereby, like the thin film transistor 1 in the above embodiment, the short channel effect can be suppressed without reducing the ON current.

In this modification, the first region 31a (low carrier density region) is not formed in the first oxide semiconductor layer 31, but the first oxide semiconductor layer 31 is the same as the thin film transistor 1 in the above embodiment. Alternatively, the first region 31a may be formed.

(Modification 4)
Next, a thin film transistor 1D according to Modification 4 will be described with reference to FIG. 10A. FIG. 10A is a cross-sectional view illustrating a configuration of a thin film transistor according to Modification 4.

In the thin film transistor 1 shown in FIG. 1, the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 are formed by thinning both sides of the oxide semiconductor layer 30X using the gate electrode 50 as a mask. Therefore, both the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 are made thinner than the first oxide semiconductor layer 31.

On the other hand, in the thin film transistor 1D in the present modification, the second oxide semiconductor layer 32 having the drain region is thinned, but the third oxide semiconductor layer 33 having the source region is not thinned.

Even in the configuration of the thin film transistor 1D in the present modification, the distance between the drain region and the channel region can be increased, so that the strength of the drain electric field can be reduced. Thereby, like the thin film transistor 1 in the above embodiment, the short channel effect can be suppressed without reducing the ON current.

In the thin film transistor 1D illustrated in FIG. 10A, the first region 31a (low carrier density region) is formed in the first oxide semiconductor layer 31, but the first oxide semiconductor layer 31 includes the first region as illustrated in FIG. 10B. The region 31a may not be formed.

(Other variations)
As described above, the thin film transistor and the manufacturing method thereof have been described based on the embodiment and the modification. However, the present invention is not limited to the above embodiment and the modification.

For example, in the above-described embodiment and modification, a transparent amorphous oxide semiconductor of InGaZnO _x (IGZO) is used as the oxide semiconductor used for the oxide semiconductor layer, but the present invention is not limited thereto, and a polycrystalline oxide such as InGaO is used. An oxide semiconductor containing In such as a semiconductor can be used. Further, a transparent amorphous oxide semiconductor such as InWO or InWZnO may be used.

In the above-described embodiment and modification, the undercoat layer 20 is formed on the surface of the substrate 10, but the undercoat layer 20 may not be formed.

In the embodiment and the modification, the organic EL display device has been described as a display device using a thin film transistor, but the present invention is not limited to this. For example, the thin film transistor in the above embodiment and modifications can also be applied to other display devices such as a liquid crystal display device.

In this case, the organic EL display device (organic EL panel) can be used as a flat panel display. For example, the organic EL display device can be used as a display panel of any electronic device such as a television set, a personal computer, or a mobile phone.

In addition, the form obtained by making various modifications conceived by those skilled in the art with respect to each embodiment and modification, and the components and functions in each embodiment and modification are arbitrarily set within the scope of the present invention. Forms realized by combining them are also included in the present invention.

The thin film transistor according to the present invention can be widely used in various electric devices having a thin film transistor such as a display device (display panel) such as an organic EL display device, a television set, a personal computer, and a mobile phone using the display device. it can.

1, 1A, 1B, 1C, 1D Thin film transistor 10 Substrate 20

Undercoat layer

30, 30X, 300 Oxide semiconductor layer 31 First oxide semiconductor layer 31a First region 31b Second region 32 Second oxide semiconductor layer 33 Third Oxide semiconductor layer 40 Gate insulating layer 50, G1, G2 Gate electrode 60 Interlayer insulating layer 70S, S1, S2 Source electrode 70D, D1, D2 Drain electrode 80 Acceptor element-containing layer 100 Organic EL display device 110 TFT substrate 120 Pixel 130 Organic EL element 131 Anode 132 EL layer 133 Cathode 140 Gate wiring 150 Source wiring 160 Power supply wiring SwTr Switching transistor DrTr Drive transistor C Capacitor

Claims

A substrate,
An oxide semiconductor layer located above the substrate and having a channel region, a source region and a drain region;
A gate insulating layer located above the oxide semiconductor layer;
A gate electrode located above the gate insulating layer;
A source electrode electrically connected to the source region;
A drain electrode electrically connected to the drain region,
The channel region is a region facing the gate electrode with the gate insulating layer interposed therebetween,
The drain region is a region located on the other end side of the channel region, and a resistance value is lower than a resistance value of the channel region,
The source region is located on one end side of the channel region and has a resistance value lower than the resistance value of the channel region,
In the oxide semiconductor layer, at least a thickness of a boundary portion between the drain region and the channel region is thinner than a thickness of the channel region.
Thin film transistor.
In the oxide semiconductor layer, the thickness of the boundary portion between the source region and the channel region is thinner than the thickness of the channel region.
The thin film transistor according to claim 1.
The oxide semiconductor layer has a convex cross-sectional shape, and the upper surface of the portion having the channel region is located above the upper surface of the portion having the drain region and the portion having the source region,
The thin film transistor according to claim 2.
The oxide semiconductor layer includes a first region that is a region on the source region side and the drain region side in the channel region, and a region that is closer to the center of the channel region than the first region. Two regions,
The carrier density of the first region is lower than the carrier density of the second region,
The thin film transistor according to claim 2 or 3.
The first region contains an element that acts as an acceptor,
The thin film transistor according to claim 4.
The first region contains at least one of copper, silicon, and fluorine as the acceptor,
The thin film transistor according to claim 5.
The contact point between the end of the upper surface of the source region or the drain region and the lower end of the side surface of the channel region is located below the position of ½ of the thickness of the channel region.
The thin film transistor according to any one of claims 2 to 6.
The difference between the contact between the end of the upper surface of the source region or the drain region and the lower end of the side surface of the channel region, and the upper surface of the channel region is at least 15 nm,
The thin film transistor according to any one of claims 2 to 7.
The metal element constituting the oxide semiconductor layer includes at least one of indium, gallium, and zinc.
The thin film transistor according to any one of claims 1 to 8.
Preparing a substrate;
Forming an oxide semiconductor layer having a channel region above the substrate;
Forming a gate insulating layer above the oxide semiconductor layer;
Forming a gate electrode above the gate insulating layer;
Forming a source region and a drain region in the oxide semiconductor layer;
Forming a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region,
The channel region is a region facing the gate electrode with the gate insulating layer interposed therebetween,
The source region is located on one end side of the channel region and has a resistance value lower than the resistance value of the channel region,
The drain region is a region located on the other end side of the channel region, and a resistance value is lower than a resistance value of the channel region,
Furthermore, it includes a step of processing the oxide semiconductor layer so that at least a thickness of a boundary portion between the drain region and the channel region is thinner than a thickness of the channel region.
A method for manufacturing a thin film transistor.
Preparing a substrate;
Forming an oxide semiconductor layer above the substrate;
Forming a gate insulating film above the oxide semiconductor layer;
Forming a gate electrode having a predetermined shape above the gate insulating film;
Etching the gate insulating film using the gate electrode as a mask to form a gate insulating layer having a predetermined shape;
Etching the part of the oxide semiconductor layer using the gate electrode as a mask to thin the part of the oxide semiconductor layer;
Forming a source region and a drain region in the part of the oxide semiconductor layer;
Forming a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region.
A method for manufacturing a thin film transistor.
Further, in the channel region, the carrier density of the first region which is the region on the source region side and the drain region side is a region closer to the center of the channel region than the first region. A step of diffusing an element acting as an acceptor into the channel region so as to be lower than the carrier density,
The manufacturing method of the thin-film transistor of Claim 11.
The step of diffusing the element acting as the acceptor
Including a step of attaching the element to at least a side surface of the channel region, and a step of heating thereafter.
The manufacturing method of the thin-film transistor of Claim 12.