JP2017191838A - Thin film transistor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor substrate which can suppress the reduction of a TFT threshold voltage.SOLUTION: A TFT substrate 20 comprises: a base 110; an undercoat layer 120; an oxide semiconductor layer 130 having a channel region 131, a source region 132 and a drain region 133; a gate insulator layer 140; a gate electrode layer 150 provided on the gate insulator layer 140 at a position opposed to the channel region 131; an aluminum oxide layer 160 capable of suppressing hydrogen transmission through itself, which is provided so as to cover surfaces of the gate electrode layer 150, the source region 132 and the drain region 133, and the undercoat layer 120; and a hydrogen-suppressing layer 190 capable of suppressing hydrogen transmission through itself, which is provided on the undercoat layer 120. The hydrogen-suppressing layer 190 is provided in a region which is not coincident with the oxide semiconductor layer 130, which is one of regions extending along end faces of the gate electrode layer 150 in plan view.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a thin film transistor substrate.

  Conventionally, a thin film semiconductor device such as a thin film transistor (TFT) is used in an active matrix display device such as a liquid crystal display device or a solid-state imaging device such as a digital camera. In the display device, the TFT is used as a switching element for selecting a pixel, a driving transistor for driving the pixel, a driver outside the display region, or the like.

  For example, an organic EL display having an organic EL (Electro Luminescence) element using an organic light-emitting material is a current-driven display device, unlike a voltage-driven liquid crystal display. For this reason, development of TFTs having better performance is urgently required. In recent years, TFTs using an oxide semiconductor typified by InGaZnO as a channel layer have been actively developed (for example, see Patent Document 1).

JP 2014-183238 A

  In the TFT described in Patent Document 1, generation of defects in the semiconductor layer is suppressed by supplying hydrogen to the semiconductor layer. However, when the amount of hydrogen supplied to the semiconductor layer is too large, the channel region of the semiconductor layer occludes hydrogen to lower the resistance, and the threshold voltage of the TFT decreases.

  Accordingly, an object of the present invention is to provide a thin film transistor substrate in which a decrease in threshold voltage of a TFT is suppressed.

  In order to achieve the above object, a thin film transistor substrate according to one embodiment of the present invention includes a substrate, an undercoat layer provided above the substrate, a channel region provided above the undercoat layer, and the channel An oxide semiconductor layer having a source region and a drain region whose resistivity is lower than that of the region; a gate insulating layer provided on the channel region; and a gate provided on the gate insulating layer at a position facing the channel region An electrode layer; a first hydrogen suppression layer configured to cover the surface of the gate electrode layer, the source region and the drain region, and the undercoat layer; And a second hydrogen suppression layer, which is provided between the first hydrogen suppression layer and suppresses hydrogen permeation. In view it is provided in a region which does not overlap with the oxide semiconductor layer in the region along the end surface of the gate electrode layer.

  ADVANTAGE OF THE INVENTION According to this invention, the thin-film transistor substrate by which the fall of the threshold voltage of TFT was suppressed can be provided.

1 is a diagram showing a thin film semiconductor array substrate according to a first embodiment. 1 is a partially cutaway perspective view of an organic EL display device according to Embodiment 1. FIG. 2 is a perspective view illustrating an example of a pixel bank of the organic EL display device according to Embodiment 1. FIG. FIG. 3 is an electric circuit diagram illustrating a configuration of a pixel circuit in the organic EL display device according to the first embodiment. 3 is a top view of the thin film transistor substrate according to Embodiment 1. FIG. FIG. 6 is a cross-sectional view of the thin film transistor substrate according to the first embodiment taken along line VI-VI in FIG. 5. FIG. 6 is a cross-sectional view of the thin film transistor substrate according to the first embodiment taken along line VII-VII in FIG. 5. 4 is a plan view for explaining the positional relationship between a gate electrode layer and a region where a hydrogen suppression layer is provided according to Embodiment 1. FIG. 4 is a plan view for explaining the positional relationship between a gate electrode layer and a region where a hydrogen suppression layer is provided according to Embodiment 1. FIG. FIG. 5 is a cross-sectional view showing from the undercoat layer forming step to the gate electrode layer and gate insulating layer forming step in the method of manufacturing a thin film transistor substrate according to the first embodiment. 5 is a cross-sectional view showing an aluminum oxide layer forming step and an interlayer insulating layer forming step in the method of manufacturing a thin film transistor substrate according to Embodiment 1. FIG. It is a top view of the conventional thin-film transistor substrate. It is sectional drawing of the conventional thin-film transistor substrate in the XB-XB line | wire of FIG. 10A. It is sectional drawing of the conventional thin-film transistor substrate in the XC-XC line | wire of FIG. 10A. 6 is a top view of a thin film transistor substrate according to a first modification of the first embodiment. FIG. It is sectional drawing of the thin-film transistor substrate which concerns on the modification 1 of Embodiment 1 in the XIB-XIB line | wire of FIG. 11A. 6 is a top view of a thin film transistor substrate according to a second modification of the first embodiment. FIG. FIG. 6 is a cross-sectional view of a thin film transistor substrate according to a second embodiment. 6 is a cross-sectional view of a thin film transistor substrate according to a modification of the second embodiment. FIG. FIG. 6 is a top view of a thin film transistor substrate according to a third embodiment. It is sectional drawing of the thin-film transistor substrate which concerns on Embodiment 3 in the XIVB-XIVB line | wire of FIG. 14A. FIG. 10 is a top view of a thin film transistor substrate according to a modification of the third embodiment. It is sectional drawing of the thin-film transistor substrate which concerns on the modification of Embodiment 3 in the XVB-XVB line | wire of FIG. 15A. FIG. 6 is a cross-sectional view of a thin film transistor substrate according to a fourth embodiment.

  Hereinafter, a thin film transistor substrate according to an embodiment of the present invention will be described in detail with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present invention. Therefore, numerical values, shapes, materials, components, arrangement and connection forms of components, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements.

  Each figure is a mimetic diagram and is not necessarily illustrated strictly. Therefore, for example, the scales and the like do not necessarily match in each drawing. Moreover, in each figure, the same code | symbol is attached | subjected about the substantially same structure, The overlapping description is abbreviate | omitted or simplified.

  Further, in this specification, the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute space recognition, but are based on the stacking order in the stacking configuration. Is used as a term defined by the relative positional relationship. In addition, the terms “upper” and “lower” are used not only when two components are spaced apart from each other and there is another component between the two components. The present invention is also applied when two components are in close contact with each other and are in contact with each other.

(Embodiment 1)
[1. Organic EL display device]
First, an outline of the organic EL display device according to the present embodiment will be described with reference to FIGS. FIG. 1 is a diagram showing a configuration of a thin film semiconductor array substrate 1 according to the present embodiment. FIG. 2 is a partially cutaway perspective view of the organic EL display device 10 according to the present embodiment. FIG. 3 is a diagram illustrating an example of a pixel bank of the organic EL display device 10 according to the present embodiment. FIG. 4 is a diagram showing a circuit configuration of the pixel circuit 31 in the organic EL display device 10 according to the present embodiment.

  First, as shown in FIG. 1, the thin film semiconductor array substrate 1 includes a plurality (two in FIG. 1) of organic EL display devices 10. As shown in FIG. 2, each of the plurality of organic EL display devices 10 includes a TFT substrate (TFT array substrate) 20 on which a plurality of thin film transistors are arranged, an anode 41 which is a lower electrode, and a light emission made of an organic material. It is configured by a laminated structure of an organic EL element (light emitting part) 40 including an EL layer 42 as a layer and a cathode 43 as a transparent upper electrode.

  A plurality of pixels 30 are arranged in a matrix on the TFT substrate 20, and each pixel 30 is provided with a pixel circuit 31.

  The organic EL element 40 is formed corresponding to each of the plurality of pixels 30, and the light emission of each organic EL element 40 is controlled by the pixel circuit 31 provided in each pixel 30. The organic EL element 40 is formed on an interlayer insulating film (planarization layer) formed so as to cover a plurality of thin film transistors.

  The organic EL element 40 has a configuration in which an EL layer 42 is disposed between an anode 41 and a cathode 43. A hole transport layer is further laminated between the anode 41 and the EL layer 42, and an electron transport layer is further laminated between the EL layer 42 and the cathode 43. Note that another organic functional layer (for example, a hole injection layer, an electron injection layer, or the like) may be provided between the anode 41 and the cathode 43.

  As the material of the anode 41, for example, a conductive metal such as molybdenum, aluminum, gold, silver, or copper or an alloy thereof, an organic conductive material such as PEDOT: PSS, zinc oxide, or zinc-doped indium oxide is used. be able to. The anode 41 is formed by, for example, a vacuum evaporation method, an electron beam evaporation method, an RF sputtering method, or a printing method.

  The EL layer 42 is formed on the anode 41 in the opening of the bank 21 for each pixel 30 or for each line. As a material of the EL layer 42, for example, Alq3 (tris (8-hydroxyquinoline) aluminum) can be used. Further, for example, copper phthalocyanine as a hole injection layer, α-NPD (Bis [N- (1-Naphthyl) -N-phenyl] benzidine) as a hole transport layer, oxazole derivative as an electron transport layer, electron injection Alq3 can be used as the layer. Note that these materials are merely examples, and other materials may be used.

As a material of the cathode 43, for example, ITO, SnO ₂ , In ₂ O ₃ , ZnO, or a combination thereof can be used.

  Each pixel 30 is driven and controlled by a respective pixel circuit 31. The TFT substrate 20 includes a plurality of gate wirings (scanning lines) 50 arranged along the row direction of the pixels 30 and a plurality of gate wirings 50 arranged along the column direction of the pixels 30 so as to intersect the gate wiring 50. Source wiring (signal wiring) 60 and a plurality of power supply wirings (not shown) arranged in parallel with the source wiring 60 are formed. Each pixel 30 is partitioned by, for example, an orthogonal gate line 50 and a source line 60.

  The gate wiring 50 is connected to the gate electrode of the thin film transistor operating as a switching element included in each pixel circuit 31 for each row. The source wiring 60 is connected to the source electrode of the thin film transistor operating as a switching element included in each pixel circuit 31 for each column. The power supply wiring is connected to the drain electrode of the thin film transistor operating as a drive element included in each pixel circuit 31 for each column.

  As shown in FIG. 3, each pixel 30 of the organic EL display device 10 is composed of sub-pixels 30R, 30G, and 30B of three colors (red, green, and blue), and these sub-pixels 30R, 30G, and 30B. Each is formed so that a plurality are arranged in a matrix on the display surface. The sub-pixels 30R, 30G, and 30B are separated from each other by the bank 21.

  The banks 21 are formed in a lattice shape so that the ridges extending in parallel to the gate wiring 50 and the ridges extending in parallel to the source wiring 60 intersect each other. Each of the portions surrounded by the protrusions (that is, the opening of the bank 21) and the sub-pixels 30R, 30G, and 30B have a one-to-one correspondence. In the present embodiment, the bank 21 is a pixel bank, but may be a line bank.

  The anode 41 is formed for each of the sub-pixels 30R, 30G, and 30B on the interlayer insulating film (flattening layer) on the TFT substrate 20 and in the opening of the bank 21. Similarly, the EL layer 42 is formed for each of the sub-pixels 30R, 30G, and 30B on the anode 41 and in the opening of the bank 21. The transparent cathode 43 is continuously formed on the plurality of banks 21 so as to cover all the EL layers 42 (all the sub-pixels 30R, 30G, and 30B).

  Further, the pixel circuit 31 is provided for each of the sub-pixels 30R, 30G, and 30B, and each of the sub-pixels 30R, 30G, and 30B and the corresponding pixel circuit 31 are electrically connected by a contact hole and a relay electrode. ing. The sub-pixels 30R, 30G, and 30B have the same configuration except that the emission color of the EL layer 42 is different.

  Here, the circuit configuration of the pixel circuit 31 in the pixel 30 will be described with reference to FIG. FIG. 4 is an electric circuit diagram showing the configuration of the pixel circuit 31 in the organic EL display device 10 according to the present embodiment.

  As shown in FIG. 4, the pixel circuit 31 includes a thin film transistor 32 that operates as a driving element, a thin film transistor 33 that operates as a switching element, and a capacitor 34 that stores data to be displayed on the corresponding pixel 30. . In the present embodiment, the thin film transistor 32 is a drive transistor for driving the organic EL element 40, and the thin film transistor 33 is a switching transistor for selecting the pixel 30.

  The thin film transistor 32 includes a drain electrode 33d of the thin film transistor 33 and a gate electrode 32g connected to one end of the capacitor 34, a drain electrode 32d connected to the power supply wiring 70, the other end of the capacitor 34, and an anode 41 of the organic EL element 40. And a semiconductor film (not shown). The thin film transistor 32 supplies a current corresponding to the data voltage held by the capacitor 34 from the power supply wiring 70 to the anode 41 of the organic EL element 40 through the source electrode 32 s. Thereby, in the organic EL element 40, a drive current flows from the anode 41 to the cathode 43, and the EL layer 42 emits light.

  The thin film transistor 33 includes a gate electrode 33g connected to the gate wiring 50, a source electrode 33s connected to the source wiring 60, a drain electrode 33d connected to one end of the capacitor 34 and the gate electrode 32g of the thin film transistor 32, and a semiconductor film. (Not shown). In the thin film transistor 33, when a predetermined voltage is applied to the connected gate wiring 50 and source wiring 60, the source and the drain become conductive. As a result, the voltage applied to the source line 60 is stored in the capacitor 34 as the data voltage.

  Note that the organic EL display device 10 having the above configuration employs an active matrix system in which display control is performed for each pixel 30 located at the intersection of the gate line 50 and the source line 60. Thereby, the corresponding organic EL element 40 selectively emits light by the thin film transistors 32 and 33 of each pixel 30 (each subpixel), and a desired image is displayed.

  In FIG. 4, a pixel circuit having a so-called 2Tr1C configuration including two thin film transistors 32 and 33 and one capacitor 34 is illustrated as the pixel circuit 31, but the pixel circuit 31 is not limited thereto. For example, the pixel circuit 31 may further include a transistor for correcting the threshold voltage of the driving transistor.

[2. Thin Film Transistor (TFT)]
Hereinafter, the thin film transistor 100 formed on the TFT substrate 20 according to the present embodiment will be described with reference to FIGS.

  FIG. 5 is a top view of the TFT substrate 20 according to the present embodiment. FIG. 6 is a cross-sectional view of the TFT substrate 20 according to the present embodiment taken along line VI-VI in FIG. FIG. 7 is a cross-sectional view of the TFT substrate 20 according to the present embodiment taken along the line VII-VII in FIG.

  As shown in FIGS. 5 to 7, the TFT substrate 20 includes a substrate 110, an undercoat layer 120, an oxide semiconductor layer 130, a gate insulating layer 140, a gate electrode layer 150, an aluminum oxide layer 160, An interlayer insulating layer 170, a drain electrode 180d and a source electrode 180s, and a hydrogen suppression layer 190 are provided.

  As shown in FIGS. 5 and 6, a thin film transistor 100 is formed on the TFT substrate 20. Specifically, the thin film transistor 100 is a top-gate TFT, and as illustrated in FIG. 6, the oxide semiconductor layer 130, the gate insulating layer 140, the electrode portion 151 of the gate electrode layer 150, and the source electrode 180s. And a drain electrode 180d.

  The thin film transistor 100 is, for example, the thin film transistor 32 illustrated in FIG. 4 and can be used as a drive transistor. Specifically, the electrode portion 151 of the gate electrode layer 150 corresponds to the gate electrode 32g, the source electrode 180s corresponds to the source electrode 32s, and the drain electrode 180d corresponds to the drain electrode 32d. Note that the thin film transistor 100 may be, for example, the thin film transistor 33 illustrated in FIG. 4 or may be used as a switching transistor.

  In the following description, “upward” means the undercoat layer 120 side with respect to the substrate 110, and specifically means the stacking direction of each layer. On the other hand, “downward” means a side opposite to the undercoat layer 120 with respect to the substrate 110, and specifically means a direction opposite to the stacking direction of the layers.

[2-1. substrate]
The board | substrate 110 is a board | substrate comprised from the material which has electrical insulation, for example. For example, the substrate 110 is a substrate made of a glass material such as alkali-free glass, quartz glass, or high heat resistance glass, or a resin material such as polyethylene, polypropylene, or polyimide.

  The substrate 110 may be a flexible substrate having sheet-like or film-like flexibility, for example. The board | substrate 110 is a flexible resin board comprised by the single layer or lamination | stacking of film materials, such as a polyimide, a polyethylene terephthalate, a polyethylene naphthalate, for example.

  When the substrate 110 is a flexible substrate, a support substrate such as a glass substrate is provided on the back surface of the substrate 110 in the manufacturing process of the TFT substrate 20. For example, after forming the thin film transistor 100 and the organic EL element 40, the support substrate is peeled from the substrate 110, whereby the TFT substrate 20 can be used for a flexible display.

[2-2. Undercoat layer]
The undercoat layer 120 is an example of an inorganic layer provided on the substrate 110. The undercoat layer 120 is formed on the surface of the substrate 110 (the surface on the side where the oxide semiconductor layer 130 is formed). By providing the undercoat layer 120, impurities (eg, sodium and phosphorus) included in the substrate 110, moisture in the air, or the like can be prevented from entering the oxide semiconductor layer 130. Thereby, the film quality of the oxide semiconductor layer 130 can be stabilized, and the TFT characteristics can be stabilized.

  As shown in FIGS. 6 and 7, the undercoat layer 120 includes a first layer 121 and a second layer 122. That is, in this embodiment, the undercoat layer 120 has a stacked structure of the first layer 121 and the second layer 122.

The first layer 121 is a layer containing silicon nitride (SiN _x ) as a main component provided above the substrate 110. Specifically, the first layer 121 is a silicon nitride film, but may be a silicon oxynitride film (SiON _x ) or the like. The film thickness of the first layer 121 is, for example, 200 nm, but is not limited thereto. The first layer 121 contains hydrogen resulting from a gas (ammonia gas or the like) introduced during film formation.

The second layer 122 is a layer containing silicon oxide (SiO _x ) provided on the first layer 121 as a main component. Specifically, the second layer 122 is a silicon oxide film. The film thickness of the second layer 122 is, for example, 200 nm, but is not limited thereto.

[2-3. Oxide semiconductor layer]
The oxide semiconductor layer 130 is used as a channel layer. Specifically, as illustrated in FIG. 6, the oxide semiconductor layer 130 includes a channel region 131, a source region 132, and a drain region 133. The channel region 131 is a region facing the gate electrode layer 150 with the gate insulating layer 140 interposed therebetween. The source region 132 and the drain region 133 are low resistance regions whose resistivity is lower than that of the channel region 131. The source region 132 and the drain region 133 are formed by causing oxygen vacancies in a predetermined region of the formed oxide semiconductor, for example.

  The planar view shape of the oxide semiconductor layer 130 is substantially rectangular as shown in FIG. The planar view shape of the channel region 131 is a substantially rectangular shape that is long in the channel width direction. That is, the channel width W is longer than the channel length L. The source region 132 and the drain region 133 are in contact with the channel region 131 and are located with the channel region 131 interposed therebetween. The plan view shape of the source region 132 and the drain region 133 is substantially rectangular as shown in FIG.

As shown in FIG. 6, the oxide semiconductor layer 130 is provided in a predetermined shape above the substrate 110, specifically, on the undercoat layer 120. The oxide semiconductor layer 130 contains a transparent amorphous oxide semiconductor (TAOS) as a main component. Specifically, the oxide semiconductor layer 130 contains a metal oxide as a main component. The metal is, for example, indium (In), gallium (Ga), or zinc (Zn). As the oxide semiconductor layer 130, for example, InGaZnO, InTiZnO, ZnO, InGaO, InZaO, or the like can be used. Taking the case of InGaZnO as an example, an example of the composition ratio of each element is In _x Ga _y Zn _z O _{1.5x + 1.5y + z} (x, y, and z are integers). The film thickness of the oxide semiconductor layer 130 is, for example, 10 nm to 300 nm.

[2-4. Gate insulation layer]
The gate insulating layer 140 is provided over the channel region 131 of the oxide semiconductor layer 130. Although details will be described later, the gate insulating layer 140 is formed in a self-aligned manner using the gate electrode layer 150 as a mask. For this reason, the planar view shapes of the gate insulating layer 140 and the gate electrode layer 150 are substantially the same.

  In this embodiment, the end surface of the gate insulating layer 140 is flush with the end surface of the channel region 131, and the contour line of the gate insulating layer 140 and the contour line of the channel region 131 substantially coincide with each other when viewed from above. .

The gate insulating layer 140 is a single-layer insulating layer or a stacked insulating layer using an oxide insulating layer or a nitride insulating layer. As the gate insulating layer 140, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), a silicon oxynitride film (SiON _x ), an aluminum oxide film (AlO _x ), a tantalum oxide film (TaO _x ), or the like is used. A layer film or a laminated film thereof can be used. The thickness of the gate insulating layer 140 can be designed in consideration of the breakdown voltage of the thin film transistor 100, and is, for example, 50 nm to 400 nm.

[2-5. Gate electrode layer]
The gate electrode layer 150 is provided on the gate insulating layer 140. In this embodiment, the end surface of the gate electrode layer 150 is flush with the end surface of the gate insulating layer 140, and the outline of the gate electrode layer 150 and the outline of the gate insulating layer 140 substantially coincide with each other when viewed from above. ing.

  The gate electrode layer 150 is an electrode having a single layer structure or a stacked structure such as a conductive material such as metal or an alloy thereof. As a material of the gate electrode layer 150, aluminum (Al), molybdenum (Mo), tungsten (W), molybdenum tungsten (MoW), copper (Cu), titanium (Ti), chromium (Cr), or the like can be used. . The film thickness of the gate electrode layer 150 is, for example, 50 nm to 300 nm.

  In the present embodiment, as illustrated in FIG. 5, the gate electrode layer 150 includes an electrode portion 151 and an extending portion 152.

  The electrode portion 151 is a portion that functions as a gate electrode of the thin film transistor 100 and has substantially the same shape as the channel region 131 in plan view. That is, the electrode portion 151 is a portion located in the direction directly above the channel region 131.

  The extending portion 152 is a portion extending from the electrode portion 151 in the channel width direction. In the present embodiment, as shown in FIG. 5, the extending portions 152 are provided on both sides of the electrode portion 151. For example, the extending portion 152 functions as part of a wiring for applying a predetermined potential (voltage) to the electrode portion 151.

[2-6. Aluminum oxide layer (first hydrogen suppression layer)]
The aluminum oxide layer 160 is an example of a first hydrogen suppression layer that suppresses permeation of hydrogen. The aluminum oxide layer 160 suppresses supply of hydrogen contained in the interlayer insulating layer 170 to the channel region 131. Further, the aluminum oxide layer 160 suppresses supply of hydrogen contained in the undercoat layer 120 to the interlayer insulating layer 170. The aluminum oxide layer 160 is an example of a so-called hydrogen block layer.

  The aluminum oxide layer 160 is provided so as to cover the surface of the gate electrode layer 150, the source region 132 and the drain region 133, and the undercoat layer 120. Specifically, the aluminum oxide layer 160 is provided over the oxide semiconductor layer 130 and is in contact with the source region 132 and the drain region 133. In this embodiment, the aluminum oxide layer 160 is provided in a portion of the top surface of the oxide semiconductor layer 130 that is not covered with the gate insulating layer 140. Specifically, the aluminum oxide layer 160 is provided on the source region 132 and the drain region 133.

  More specifically, the aluminum oxide layer 160 covers the upper surface and the end surface of the gate electrode layer 150, the end surface of the gate insulating layer 140, the upper surfaces of the source region 132 and the drain region 133, and the upper surface of the undercoat layer 120. ing. Note that the aluminum oxide layer 160 is not necessarily provided over the gate electrode layer 150.

  A plurality of openings (contact holes) are formed in the aluminum oxide layer 160 and the interlayer insulating layer 170 so as to penetrate a predetermined region. Through the contact hole, the source region 132 and the source electrode 180s are electrically and physically connected, and the drain region 133 and the drain electrode 180d are electrically and physically connected.

  The aluminum oxide layer 160 also has a function of promoting reduction in resistance of the oxide semiconductor layer 130. In this embodiment, the aluminum oxide layer 160 promotes a reduction in resistance of the source region 132 and the drain region 133 of the oxide semiconductor layer 130. Specifically, the aluminum oxide layer 160 generates oxygen vacancies by extracting oxygen from the source region 132 and the drain region 133. Thereby, the resistance of the source region 132 and the drain region 133 is reduced.

  The source region 132 and the drain region 133 are regions that are electrically connected to the source electrode 180s and the drain electrode 180d, respectively. For this reason, the source region 132 and the drain region 133 preferably have a low contact resistance. Since the aluminum oxide layer 160 reduces the resistance of the source region 132 and the drain region 133, the contact resistance is lowered, and the TFT characteristics can be improved.

The film thickness of the aluminum oxide layer 160 may be sufficient to extract oxygen from the oxide semiconductor layer 130, and is, for example, 10 nm or more, and preferably 20 nm or more. The film density of the aluminum oxide layer 160 is, for example, 2.7 g / cm ³ or less.

[2-7. Interlayer insulation layer]
The interlayer insulating layer 170 is provided so as to cover the aluminum oxide layer 160. Specifically, the interlayer insulating layer 170 is formed so as to cover the entire element region where the thin film transistor 100 is formed.

The interlayer insulating layer 170 is formed of a material mainly containing an organic material or an inorganic material. For example, the interlayer insulating layer 170 is a single layer film such as a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), a silicon oxynitride film (SiON _x ), or an aluminum oxide film (AlO _x ), or a stacked film. It is. At this time, the interlayer insulating layer 170 may be formed in a thick film using a material having a small relative dielectric constant. Accordingly, parasitic capacitance between the gate electrode layer 150 and the source electrode 180s or the drain electrode 180d can be reduced.

[2-8. Source electrode and drain electrode]
The source electrode 180s and the drain electrode 180d are formed in a predetermined shape on the interlayer insulating layer 170. Each of the source electrode 180 s and the drain electrode 180 d is electrically connected to the oxide semiconductor layer 130.

  In this embodiment, the source electrode 180 s is electrically and physically connected to the source region 132 through a contact hole formed in the interlayer insulating layer 170 and the aluminum oxide layer 160. The drain electrode 180d is electrically and physically connected to the drain region 133 through a contact hole formed in the interlayer insulating layer 170 and the aluminum oxide layer 160.

  The source electrode 180s and the drain electrode 180d are electrodes having a single layer structure or a stacked structure such as a conductive material or an alloy thereof. Examples of the material of the source electrode 180s and the drain electrode 180d include aluminum (Al), molybdenum (Mo), tungsten (W), molybdenum tungsten (MoW), copper (Cu), titanium (Ti), and chromium (Cr). Can be used. The film thickness of the source electrode 180s and the drain electrode 180d is, for example, 50 nm to 300 nm.

[2-9. Hydrogen suppression layer (second hydrogen suppression layer)]
The hydrogen suppression layer 190 is an example of a second hydrogen suppression layer (hydrogen block layer) that suppresses hydrogen permeation. The hydrogen suppression layer 190 suppresses hydrogen contained in the undercoat layer 120 from being supplied to the interlayer insulating layer 170.

  In this embodiment, the hydrogen suppression layer 190 contains the same material as the oxide semiconductor layer 130 as a main component. Specifically, the hydrogen suppression layer 190 contains a transparent oxide semiconductor such as InGaZnO as a main component. In addition to low hydrogen sensitivity on the back gate side, the transparent oxide semiconductor itself has a function of suppressing hydrogen permeation.

  Although details will be described later, the hydrogen suppression layer 190 is formed in the same step as the oxide semiconductor layer 130. Therefore, similarly to the oxide semiconductor layer 130, the hydrogen suppression layer 190 includes a high resistance region 191 corresponding to the channel region 131 and a low resistance region 192 corresponding to the source region 132 and the drain region 133. .

  The high resistance region 191 is a portion provided in the non-overlapping region 212 of the electrode region 210 (see FIG. 8B), and the low resistance region 192 is a gate electrode in the non-overlapping region 202 of the end surface region 200 (see FIG. 8A). This is a portion provided in a region not overlapping with the layer 150. The plan view shape of the high resistance region 191 is substantially rectangular. The low-resistance region 192 has a substantially U-shape in plan view and is provided so as to surround the high-resistance region 191.

  Note that the high-resistance region 191 or the low-resistance region 192 may not be provided in the hydrogen suppression layer 190.

  The hydrogen suppression layer 190 is provided on the undercoat layer 120. In the present embodiment, as shown in FIG. 7, the hydrogen suppression layer 190 is provided between the undercoat layer 120, the gate insulating layer 140, and the aluminum oxide layer 160. Specifically, the hydrogen suppression layer 190 is provided in the direction immediately below the extending portion 152 of the gate electrode layer 150 and in the vicinity thereof.

  More specifically, the hydrogen suppression layer 190 is provided in a region that does not overlap with the oxide semiconductor layer 130 in a region along the end surface of the gate electrode layer 150 in plan view. In this embodiment, the hydrogen suppression layer 190 is further provided in a region not overlapping with the oxide semiconductor layer 130 in a region overlapping with the gate electrode layer 150 in a plan view. In FIG. 5, the hydrogen suppression layer 190 is hatched to clarify the shape of the hydrogen suppression layer 190 in plan view.

  Here, the positional relationship between the region where the hydrogen suppression layer 190 is provided and the gate electrode layer 150 will be described with reference to FIGS. 8A and 8B. 8A and 8B are plan views for explaining the positional relationship between the gate electrode layer 150 and the region where the hydrogen suppression layer 190 is provided according to the present embodiment. 8A and 8B, a plurality of areas are shaded with dots having different densities.

  As shown in FIGS. 8A and 8B, the contour line in the plan view of the gate electrode layer 150 is a portion corresponding to the end face of the gate electrode layer 150. In this embodiment, the end surface region 200 illustrated in FIG. 8A is a region along the end surface of the gate electrode layer 150. Specifically, the end surface region 200 is a region having a predetermined width along the end surface of the gate electrode layer 150. Since the gate electrode layer 150 has a substantially rectangular shape in plan view, the end surface region 200 has a substantially rectangular ring shape with a predetermined width.

  In the example shown in FIG. 8A, the end face of the gate electrode layer 150 is positioned at the approximate center in the width direction, but the present invention is not limited to this. The end surface region 200 may be an outer region adjacent along the end surface of the gate electrode layer 150. That is, the end surface region 200 may not overlap with the gate electrode layer 150 in plan view.

  As illustrated in FIG. 8A, the end surface region 200 is provided with an overlapping region 201 that overlaps with the oxide semiconductor layer 130 and a non-overlapping region 202 that does not overlap with the oxide semiconductor layer 130. The overlapping region 201 is a region along the end surface of the electrode portion 151 of the gate electrode layer 150 and is located in a direction directly below the end surface of the electrode portion 151. The non-overlapping region 202 is a region along the end surface of the extending portion 152 of the gate electrode layer 150 and is located in a direction directly below the end surface of the extending portion 152.

  An electrode region 210 illustrated in FIG. 8B is a region overlapping with the gate electrode layer 150. That is, the electrode region 210 is a region directly below the gate electrode layer 150, and the shape in plan view matches the gate electrode layer 150.

  As illustrated in FIG. 8B, the electrode region 210 is provided with an overlapping region 211 that overlaps with the oxide semiconductor layer 130 and a non-overlapping region 212 that does not overlap with the oxide semiconductor layer 130. The overlapping region 211 is a region directly below the electrode portion 151 of the gate electrode layer 150 and substantially coincides with the channel region 131. The non-overlapping region 212 is a region directly below the extending portion 152 of the gate electrode layer 150.

  As can be seen by comparing FIG. 5 with FIG. 8A and FIG. 8B, the hydrogen suppression layer 190 is provided in the non-overlapping region 202 and the non-overlapping region 212. In this embodiment, the hydrogen suppression layer 190 is separated from the oxide semiconductor layer 130. Specifically, as illustrated in FIG. 5, a gap is provided between the hydrogen suppression layer 190 and the oxide semiconductor layer 130. The width of the gap is not particularly limited, but is, for example, sufficiently shorter than the channel width W and shorter than the width of the non-overlapping region 202. Thereby, the hydrogen suppression layer 190 and the oxide semiconductor layer 130 are electrically insulated.

[3. Manufacturing method of TFT substrate]
Next, a manufacturing method of the TFT substrate 20 according to the present embodiment will be described with reference to FIGS. 9A and 9B.

  9A and 9B are cross-sectional views illustrating a method for manufacturing the TFT substrate 20 according to the present embodiment. Specifically, FIG. 9A shows a process from the formation process of the undercoat layer 120 to the formation process of the gate electrode layer 150 and the gate insulating layer 140. FIG. 9B shows a process for forming the aluminum oxide layer 160 and a process for forming the interlayer insulating layer 170. 9A and 9B, the left side shows a cross section of the thin film transistor 100 (cross section corresponding to FIG. 6), and the right side shows the cross section of the extended portion 152 of the gate electrode layer 150 (cross section corresponding to FIG. 7). Show.

  First, as shown in FIG. 9A (a), an undercoat layer 120 is formed on a substrate 110. Specifically, first, the substrate 110 is prepared. For example, a glass substrate such as non-alkali glass is used as the substrate 110, but a resin substrate, a synthetic quartz substrate, a silicon substrate with a thermal oxide film, or the like may be used.

  Next, a silicon nitride film is formed as the first layer 121 by, for example, a plasma CVD (Chemical Vapor Deposition) method, a sputtering method, an atomic layer deposition (ALD) method, or the like. Further, a silicon oxide film is formed as the second layer 122 on the first layer 121. Thereby, the undercoat layer 120 is formed on the substrate 110.

Here, the silicon nitride film is formed by, for example, a plasma CVD method. Specifically, a silicon nitride film is formed by introducing silane gas (SiH ₄ ), ammonia gas (NH ₃ ), and nitrogen gas (N ₂ ) into the vacuum chamber to generate plasma.

The silicon oxide film is formed by, for example, a plasma CVD method. Specifically, a silicon oxide film is formed by introducing silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) into a vacuum chamber and generating plasma.

  Next, as illustrated in FIG. 9A (b), the oxide semiconductor layer 135 and the hydrogen suppression layer 195 are formed over the substrate 110. Specifically, an oxide semiconductor layer 135 having a predetermined shape and a hydrogen suppression layer 195 having a predetermined shape are formed on the undercoat layer 120. As a material of the oxide semiconductor layer 135 and the hydrogen suppression layer 195, a transparent amorphous oxide semiconductor (TAOS) such as InGaZnO can be used. For example, a 60 nm InGaZnO film is formed as the oxide semiconductor layer 135 and the hydrogen suppression layer 195.

In this case, first, an oxide semiconductor film made of InGaZnO is formed by a sputtering method, a laser ablation method, a plasma CVD method, or the like. Specifically, using a target material containing In, Ga and Zn (for example, a polycrystalline sintered body having a composition of InGaO ₃ (ZnO) ₄ ), argon gas is introduced as an inert gas into the vacuum chamber. Then, a gas containing oxygen (O ₂ ) is introduced as a reactive gas, and electric power with a predetermined power density is applied to the target material.

After that, by patterning the formed oxide semiconductor film using a photolithography method and a wet etching method, as shown in FIG. 9A (b), the oxide semiconductor layer 135 processed into a predetermined shape and hydrogen suppression Layer 195 can be formed. Each of the oxide semiconductor layer 135 and the hydrogen suppression layer 195 is islanded in a predetermined shape. Note that for wet etching of InGaZnO, for example, a chemical solution in which phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water (H ₂ O) are mixed can be used.

  Next, as illustrated in FIG. 9C, the gate insulating film 145 is formed over the oxide semiconductor layer 135 and the hydrogen suppression layer 195. In this embodiment, a silicon oxide film is formed as a gate insulating film 145 over the entire surface so as to cover the oxide semiconductor layer 135 and the hydrogen suppression layer 195.

  Further, a gate metal film 155 is formed over the gate insulating film 145. For example, a Ti / Al / Ti stacked film is formed as the gate metal film 155 on the gate insulating film 145 by sputtering or the like.

  Next, as illustrated in FIG. 9D, the gate metal film 155 and the gate insulating film 145 are processed to form the gate electrode layer 150 and the gate insulating layer 140. Accordingly, a part of the oxide semiconductor layer 135 (specifically, a part to be the source region 132 and the drain region 133) and a part of the hydrogen suppression layer 195 (specifically, the low resistance region 192) are exposed. .

Specifically, first, a gate electrode layer 150 having a predetermined shape is formed on the gate insulating film 145 by patterning the gate metal film 155 by photolithography and etching. Etching of the gate metal film 155 which is a laminated film of Ti / Al / Ti is, for example, reactive using a gas such as sulfur hexafluoride (SF ₆ ), oxygen (O ₂ ), boron trichloride (BCl ₃ ). It can be performed by dry etching such as ion etching (RIE: Reactive Ion Etching).

Subsequently, by using the gate electrode layer 150 as a mask, the gate insulating film 145 is patterned to form the gate insulating layer 140 having substantially the same shape as the gate electrode layer 150 in a self-aligned manner. For example, the gate insulating film 145 that is a silicon oxide film can be etched by dry etching using a gas such as carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ). In this embodiment, for example, the gate metal film 155 and the gate insulating film 145 can be successively processed in this order by dry etching. Note that the gate insulating film 145 (silicon oxide film) may be processed by wet etching using a hydrofluoric acid (HF) solution.

  Next, as illustrated in FIG. 9B (e), an aluminum oxide layer 160 is formed over the oxide semiconductor layer 135 and the hydrogen suppression layer 195. By forming the aluminum oxide layer 160 over the oxide semiconductor layer 135 and the hydrogen suppression layer 195, the regions of the oxide semiconductor layer 135 and the hydrogen suppression layer 195 that are in contact with the aluminum oxide layer 160 are reduced in resistance. Thus, the oxide semiconductor layer 130 in which the source region 132 and the drain region 133 with reduced resistance are formed is formed. Further, the hydrogen suppression layer 190 in which the low resistance region 192 is formed is formed.

  In this embodiment, an aluminum oxide layer 160 is formed over the entire surface. Specifically, the top surface and side surfaces of the gate electrode layer 150, the side surface of the gate insulating layer 140, the top surface and side surfaces of the source region 132 and the drain region 133, and the top surface and side surfaces of the low resistance region 192 are covered. Layer 160 is formed. For example, a 30 nm aluminum oxide layer 160 is formed by reactive sputtering. When the aluminum oxide layer 160 extracts oxygen contained in the source region 132, the drain region 133, and the low-resistance region 192, the resistivity of these regions can be lowered.

  Note that heat (annealing) treatment may be performed before the aluminum oxide layer 160 is formed. Thus, damage to the oxide semiconductor layer 135 that has been damaged by the processes so far can be recovered.

  Next, as shown in FIG. 9B (f), an interlayer insulating layer 170 is formed so as to cover the aluminum oxide layer 160. For example, a 200 nm silicon oxide film is formed as the interlayer insulating layer 170 by plasma CVD.

  Further, openings (contact holes 170 s and 170 d) are formed in the interlayer insulating layer 170 and the aluminum oxide layer 160 so that a part of each of the source region 132 and the drain region 133 is exposed. Specifically, contact holes 170s and 170d are formed over the source region 132 and the drain region 133 by etching and removing part of the interlayer insulating layer 170 and the aluminum oxide layer 160 by a photolithography method and an etching method.

For example, a part of the interlayer insulating layer 170 which is a silicon oxide film can be removed by dry etching using carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ). Part of the aluminum oxide layer 160 can be removed by dry etching using a gas such as boron trichloride (BCl ₃ ). The aluminum oxide layer 160 may be partially removed by wet etching using, for example, an aqueous tetramethylammonium hydroxide (TMAH) solution.

  Finally, the source electrode 180s electrically and physically connected to the source region 132 and the drain electrode 180d electrically and physically connected to the drain region 133 are formed through the contact holes 170s and 170d. . Specifically, first, a metal film (source / drain metal film) is formed on the interlayer insulating layer 170 by a sputtering method or the like so as to fill the contact holes 170s and 170d. By patterning the formed metal film using a photolithography method and a wet etching method, a source electrode 180s and a drain electrode 180d having a predetermined shape are formed. For example, a MoW / Al / MoW three-layer metal film having a total film thickness of 500 nm was formed as the source electrode 180s and the drain electrode 180d.

  As described above, the TFT substrate 20 shown in FIGS. 5 to 7 can be manufactured.

[4. Effect etc.]
Here, the effect of the TFT substrate 20 according to the present embodiment will be described including the background to the present invention. First, problems in the conventional TFT substrate 20x that does not include the hydrogen suppression layer 190 will be described with reference to FIGS. 10A to 10C.

  FIG. 10A is a top view of a conventional TFT substrate 20x. FIG. 10B is a cross-sectional view of the conventional TFT substrate 20x taken along line XB-XB in FIG. 10A. FIG. 10C is a cross-sectional view of the conventional TFT substrate 20x taken along line XC-XC in FIG. 10A.

  Since the aluminum oxide layer 160 is formed of a thin film such as 10 nm to 20 nm, coverage may be insufficient at the stepped portion. That is, the aluminum oxide layer 160 may be thinner at the step portion than the other portions, or a through hole (step break) may be formed at the step portion. For example, in the region along the end face of the gate electrode layer 150, the coverage of the aluminum oxide layer 160 tends to be insufficient, and the hydrogen blocking effect is weakened.

  In the conventional TFT substrate 20x, as shown in FIG. 10B, the hydrogen suppression layer 190 is not provided. For this reason, the hydrogen contained in the first layer 121 of the undercoat layer 120 is a portion with insufficient coverage of the second layer 122 and the aluminum oxide layer 160 (that is, a region along the end face of the gate electrode layer 150). Is supplied to the interlayer insulating layer 170 (bold arrow shown in FIG. 10B).

  The hydrogen supplied to the interlayer insulating layer 170 permeates through the interlayer insulating layer 170 and is supplied to the channel region 131 through the insufficient coverage of the aluminum oxide layer 160 as shown in FIG. 10C ( A thick arrow shown in FIG. 10C). For this reason, the conventional TFT substrate 20 has a problem that the channel region 131 is lowered in resistance and the threshold voltage is lowered.

  In contrast, the TFT substrate 20 according to the present embodiment includes a substrate 110, an undercoat layer 120 provided above the substrate 110, a channel region 131 and a channel provided above the undercoat layer 120. The oxide semiconductor layer 130 having the source region 132 and the drain region 133 whose resistivity is lower than that of the region 131, the gate insulating layer 140 provided over the channel region 131, and the position facing the channel region 131 on the gate insulating layer 140 A gate electrode layer 150 provided on the gate electrode layer 150, an aluminum oxide layer 160 that suppresses hydrogen permeation and is provided so as to cover the surface of the gate electrode layer 150, the source region 132 and the drain region 133, and the undercoat layer 120. Hydrogen suppression layer provided on undercoat layer 120 to suppress hydrogen permeation And a 90, hydrogen suppression layer 190, in a plan view, is provided in the non-overlapping region 202 which does not overlap with the oxide semiconductor layer 130 of the end face region 200 along the end face of the gate electrode layer 150.

  Thereby, since the hydrogen suppression layer 190 is provided in the region along the end surface of the gate electrode layer 150 where the coverage of the aluminum oxide layer 160 is likely to be insufficient, the hydrogen contained in the undercoat layer 120 is transferred to the interlayer insulating layer 170. It can suppress that it is supplied to. Therefore, hydrogen can be prevented from being transmitted to the channel region 131 from the region along the end surface of the gate electrode layer 150 through the interlayer insulating layer 170. Therefore, a reduction in resistance of the channel region 131 can be suppressed, and a decrease in threshold voltage of the thin film transistor 100 can be suppressed.

  For example, the hydrogen suppression layer 190 contains the same material as the oxide semiconductor layer 130 as a main component.

  Accordingly, the hydrogen suppression layer 190 and the oxide semiconductor layer 130 can be formed in the same process. Therefore, the number of steps can be reduced, and for example, the manufacturing cost can be reduced.

  For example, the hydrogen suppression layer 190 is separated from the oxide semiconductor layer 130.

  Thereby, it is possible to suppress conduction between the source region 132 and the drain region 133 through the hydrogen suppression layer 190.

  For example, the hydrogen suppression layer 190 is further provided in a non-overlapping region 212 that does not overlap with the oxide semiconductor layer 130 in the electrode region 210 that overlaps with the gate electrode layer 150 in plan view.

  Thereby, since the unevenness | corrugation of the hydrogen suppression layer 190 can be decreased, the unevenness | corrugation of the aluminum oxide layer 160 provided above can also be decreased, and the coverage of the aluminum oxide layer 160 can be made favorable.

  Further, for example, the undercoat layer 120 contains a first layer 121 containing silicon nitride as a main component provided above the substrate 110 and a silicon oxide provided as a main component on the first layer 121. And a second layer 122.

  Thereby, the reliability of the thin film transistor 100 can be increased. Specifically, the first layer 121 can improve the PBTS (Positive Bias Temperature Stress) characteristics of the thin film transistor 100. In addition, the second layer 122 can suppress a decrease in threshold voltage of the thin film transistor 100.

  In addition, for example, the gate electrode layer 150 includes an electrode portion 151 that has substantially the same shape as the channel region 131 in plan view, and an extending portion 152 that extends from the electrode portion 151 in the channel width direction.

(Modification 1 of Embodiment 1)
Below, the modification 1 of Embodiment 1 is demonstrated using FIG. 11A and FIG. 11B.

  FIG. 11A is a top view of a TFT substrate 20a according to this modification. FIG. 11B is a cross-sectional view of the TFT substrate 20a according to this variation along the line XIB-XIB in FIG. 11A.

  The TFT substrate 20a according to this modification is different from the TFT substrate 20 according to the first embodiment in that a hydrogen suppression layer 190a is provided instead of the hydrogen suppression layer 190. Below, it demonstrates centering on difference with Embodiment 1, and abbreviate | omits or simplifies description about the same point.

  The shape of the hydrogen suppression layer 190a is different from that of the hydrogen suppression layer 190. Specifically, as shown in FIG. 11A, the hydrogen suppression layer 190a is provided only in the non-overlapping region 202 in the end surface region 200 (see FIG. 8A) along the end surface of the gate electrode layer 150. It is not provided in the area 210 (excluding the overlapping part with the non-overlapping area 202). More specifically, the planar view shape of the hydrogen suppression layer 190a is substantially U-shaped (substantially U-shaped). In FIG. 11A, the hydrogen suppression layer 190a is hatched in order to clarify the planar view shape of the hydrogen suppression layer 190a.

  As shown in FIG. 11B, the hydrogen suppression layer 190a has a high resistance region 191a and a low resistance region 192, as in the first embodiment. The high resistance region 191 a is a portion located in a direction directly below the gate electrode layer 150, and is a portion provided in a region overlapping the electrode region 210 in the non-overlapping region 202.

  As described above, in the TFT substrate 20a according to this modification, the hydrogen suppression layer 190a is provided only in the non-overlapping region 202.

  Accordingly, as in the first embodiment, the resistance of the channel region 131 can be reduced, and the threshold voltage of the thin film transistor 100 can be prevented from decreasing.

  Note that the hydrogen suppression layer 190a according to this modification is separated from the oxide semiconductor layer 130 as in the first embodiment. Thereby, it is possible to suppress conduction between the source region 132 and the drain region 133 through the hydrogen suppression layer 190a.

(Modification 2 of Embodiment 1)
Subsequently, Modification 2 of Embodiment 1 will be described with reference to FIG.

  FIG. 12 is a top view of a TFT substrate 20b according to this modification. The TFT substrate 20b according to the present modification is different from the TFT substrate 20 according to the first embodiment in that a hydrogen suppression layer 190b is provided instead of the hydrogen suppression layer 190. Below, it demonstrates centering on difference with Embodiment 1, and abbreviate | omits or simplifies description about the same point.

  The shape of the hydrogen suppression layer 190b is different from that of the hydrogen suppression layer 190. Specifically, the hydrogen suppression layer 190 b is in contact with the oxide semiconductor layer 130.

  As illustrated in FIG. 12, the hydrogen suppression layer 190 b includes a first suppression unit 190 b 1 in contact with the source region 132 and a second suppression unit 190 b 2 in contact with the drain region 133. The first suppression unit 190b1 and the second suppression unit 190b2 are separated from each other. That is, the first suppression unit 190b1 and the second suppression unit 190b2 are electrically insulated.

  The first suppression unit 190b1 is a portion provided in a straight line (band shape) within the non-overlapping region 202. Specifically, the first suppressing portion 190b1 extends from the end surface of the oxide semiconductor layer 130 including the boundary between the source region 132 and the channel region 131 along the channel width direction.

  The second suppression unit 190b2 is a portion provided in a straight line (band shape) in a region different from the first suppression unit 190b1 in the non-overlapping region 202. Specifically, the second suppression unit 190b2 extends from the end surface of the oxide semiconductor layer 130 including the boundary between the drain region 133 and the channel region 131 along the channel width direction.

  As described above, in the TFT substrate 20 according to this modification, the hydrogen suppression layer 190b includes the first suppression unit 190b1 in contact with the source region 132 and the second suppression unit 190b2 in contact with the drain region 133. The 1 suppression part 190b1 and the 2nd suppression part 190b2 are spaced apart.

  Thereby, it is possible to suppress conduction between the source region 132 and the drain region 133 through the hydrogen suppression layer 190b. Note that hydrogen from the undercoat layer 120 may permeate the interlayer insulating layer 170 in the space between the first suppression unit 190b1 and the second suppression unit 190b2. In this modification, since the separated portion is separated from the channel region 131, even if hydrogen permeates from the undercoat layer 120 to the interlayer insulating layer 170, the supply of the hydrogen to the channel region 131 is suppressed. be able to.

(Embodiment 2)
Hereinafter, the TFT substrate according to the second embodiment will be described.

  FIG. 13A is a cross-sectional view of the TFT substrate 320 according to this embodiment. A top view of the TFT substrate 320 is the same as FIG. 5, and FIG. 13A shows a cross section corresponding to the VII-VII line of FIG.

  As shown in FIG. 13A, the TFT substrate 320 according to the present embodiment is different from the TFT substrate 20 according to the first embodiment in that a hydrogen suppression layer 390 is provided instead of the hydrogen suppression layer 190. Below, it demonstrates centering on difference with Embodiment 1, and abbreviate | omits or simplifies description about the same point.

  The hydrogen suppression layer 390 is different from the hydrogen suppression layer 190 according to Embodiment 1 in the material included as the main component, and is otherwise the same as the hydrogen suppression layer 190. For example, the plan view shape of the hydrogen suppression layer 390 is the same as that of the hydrogen suppression layer 190, and is substantially rectangular as shown in FIG. Specifically, the hydrogen suppression layer 190 is provided in the non-overlapping region 202 (see FIG. 8A) and the non-overlapping region 212 (see FIG. 8B).

  The hydrogen suppression layer 390 contains a metal material as a main component. Examples of the metal material include, but are not limited to, copper and aluminum. In the first embodiment, the resistance of a part of the hydrogen suppression layer 190 is reduced. However, the high resistance region 191 and the low resistance region 192 are not provided in the hydrogen suppression layer 390 according to this embodiment. The hydrogen suppression layer 390 is a substantially uniform metal film. Note that a part of the film quality of the hydrogen suppression layer 390 may be changed (for example, oxidized).

  For example, the hydrogen suppression layer 390 is formed after the undercoat layer 120 is formed and before the oxide semiconductor layer 135 is formed. For example, the hydrogen suppression layer 390 having a predetermined shape can be formed by forming a metal thin film by a sputtering method or the like and then patterning the metal thin film by a photolithography method or an etching method. Note that the hydrogen suppression layer 390 may be formed after the oxide semiconductor layer 135 is formed and before the gate insulating film 145 is formed.

  As described above, in the TFT substrate 320 according to this embodiment, the hydrogen suppression layer 390 contains a metal material as a main component.

  Accordingly, since the metal material can suppress hydrogen permeation, the resistance of the channel region 131 can be reduced as in the first embodiment, and the threshold voltage of the thin film transistor 100 can be prevented from lowering. Can do.

  Note that the shape of the hydrogen suppression layer 390 containing a metal material as a main component is not limited to the example shown in FIG. For example, the hydrogen suppression layer 390a shown in FIG. 13B has a substantially U-shape (substantially U-shaped) in plan view as in the first modification of the first embodiment.

  FIG. 13B is a cross-sectional view of a TFT substrate 320a according to a modification of the present embodiment. A top view of the TFT substrate 320a is the same as FIG. 11A, and FIG. 13B shows a cross section corresponding to the XIB-XIB line of FIG. 11A.

  The hydrogen suppression layer 390a is different in shape from the hydrogen suppression layer 390 according to Embodiment 2, and is otherwise the same as the hydrogen suppression layer 390. For example, like the hydrogen suppression layer 390, the hydrogen suppression layer 390a contains a metal material such as aluminum as a main component.

  As shown in FIG. 13B, the hydrogen suppression layer 390a is not provided with the high resistance region 191a and the low resistance region 192. The hydrogen suppression layer 390a is a substantially uniform metal film.

  In addition, the planar view shape of the hydrogen suppression layer 390a may be a plurality of linear shapes. The cross-sectional shape of the hydrogen suppression layer 390a in this case is the same as the shape shown in FIG. 13B.

(Embodiment 3)
Hereinafter, the TFT substrate according to the third embodiment will be described.

  FIG. 14A is a top view of the TFT substrate 420 according to this embodiment. FIG. 14B is a cross-sectional view of the TFT substrate 420 according to the present embodiment taken along the line XIVB-XIVB in FIG. 14A.

  As shown in FIGS. 14A and 14B, the TFT substrate 420 according to the present embodiment includes a hydrogen suppression layer 490 instead of the hydrogen suppression layer 190 as compared with the TFT substrate 20 according to Embodiment 1. Is different. Below, it demonstrates centering on difference with Embodiment 1, and abbreviate | omits or simplifies description about the same point.

  The hydrogen suppression layer 490 contains aluminum oxide as a main component. Note that the hydrogen suppression layer 490 is not limited to aluminum oxide, and may contain a material having a low hydrogen permeability and an electrically insulating material as a main component. As shown in FIG. 14B, the hydrogen suppression layer 490 is not provided with the high resistance region 191 and the low resistance region 192. The hydrogen suppression layer 490 is a substantially uniform aluminum oxide film.

  As illustrated in FIG. 14A, the hydrogen suppression layer 490 is provided in a region that does not overlap with the oxide semiconductor layer 130 among a region along the end surface of the gate electrode layer 150 and a region overlapping with the gate electrode layer 150 in plan view. It has been. That is, the hydrogen suppression layer 490 is provided in the non-overlapping regions 202 and 212. In FIG. 14A, the hydrogen suppression layer 490 is hatched in order to clarify the shape of the hydrogen suppression layer 490 in plan view. The planar view shape of the hydrogen suppression layer 490 is substantially rectangular.

  In this embodiment, the hydrogen suppression layer 490 is adjacent to or overlaps with the oxide semiconductor layer 130 in plan view. Specifically, the hydrogen suppression layer 490 is in contact with the oxide semiconductor layer 130. Since aluminum oxide has an electrical insulating property, even if the hydrogen suppression layer 490 and the oxide semiconductor layer 130 are in contact with each other, conduction between the source region 132 and the drain region 133 through the hydrogen suppression layer 490 is suppressed. can do.

  For example, the hydrogen suppression layer 490 is formed after the undercoat layer 120 is formed and before the oxide semiconductor layer 135 is formed. For example, after forming an aluminum oxide film by a sputtering method or the like, the hydrogen suppression layer 490 having a predetermined shape can be formed by patterning the aluminum oxide film by a photolithography method and an etching method. Note that the hydrogen suppression layer 490 may be formed after the oxide semiconductor layer 135 is formed and before the gate insulating film 145 is formed.

  As described above, in the TFT substrate 420 according to this embodiment, the hydrogen suppression layer 490 contains aluminum oxide as a main component.

  Accordingly, since aluminum oxide can suppress hydrogen permeation, the resistance of the channel region 131 can be reduced as in the first embodiment, and the decrease in threshold voltage of the thin film transistor 100 can be suppressed. Can do.

  For example, the hydrogen suppression layer 490 is adjacent to or overlaps with the oxide semiconductor layer 130 in plan view.

  Thereby, since the hydrogen suppression layer 490 is electrically insulated, the region close to the channel region 131 can be covered with the hydrogen suppression layer 490. Accordingly, supply of hydrogen to the channel region 131 can be effectively suppressed.

(Modification of Embodiment 3)
Below, the modification of Embodiment 3 is demonstrated using FIG. 15A and FIG. 15B.

  FIG. 15A is a top view of a TFT substrate 420a according to this modification. FIG. 15B is a cross-sectional view of the TFT substrate 420a according to this variation along line XVB-XVB in FIG. 15A.

  The TFT substrate 420a according to this modification is different from the TFT substrate 420 according to the third embodiment in that a hydrogen suppression layer 490a is provided instead of the hydrogen suppression layer 490. Below, it demonstrates centering on difference with Embodiment 3, and abbreviate | omits or simplifies description about the same point.

  The shape of the hydrogen suppression layer 490a is different from that of the hydrogen suppression layer 490. Specifically, as shown in FIG. 15A, the hydrogen suppression layer 490a is provided in the entire region overlapping with the gate electrode layer 150 in plan view. Specifically, the hydrogen suppression layer 490a is provided not only in the non-overlapping regions 202 and 212 but also in the overlapping regions 201 and 211. That is, the hydrogen suppression layer 490 a is provided on the entire end face region 200 and the entire electrode region 210.

  For this reason, as shown in FIG. 15B, the hydrogen suppression layer 490 a is provided between the oxide semiconductor layer 130 and the undercoat layer 120. That is, the hydrogen suppression layer 490 a is provided in contact with the back gate side of the channel region 131.

  In the present modification, the hydrogen suppression layer 490a is described as an example provided over the entire end face region 200 and the entire electrode region 210, but may be provided so as to cover the entire surface of the undercoat layer 120. That is, the hydrogen suppression layer 490a may not be patterned.

  As described above, in the TFT substrate 420a according to the present modification, for example, the hydrogen suppression layer 490a is further provided over the entire electrode region 210 overlapping the gate electrode layer 150 in plan view.

  Thereby, since the hydrogen suppression layer 490a is electrically insulated, the region close to the channel region 131 can be covered with the hydrogen suppression layer 490a. Accordingly, supply of hydrogen to the channel region 131 can be effectively suppressed.

(Embodiment 4)
Hereinafter, the TFT substrate according to the fourth embodiment will be described.

  FIG. 16 is a cross-sectional view of the TFT substrate 520 according to this embodiment. Note that in FIG. 16, the left side shows a cross section of the thin film transistor 100, the center shows the cross section of the capacitor 591, and the right side shows the cross section of the extended portion 152 of the gate electrode layer 150.

  The TFT substrate 520 according to the present embodiment is different from the TFT substrate 20 according to the first embodiment in that a hydrogen suppression layer 590 is provided instead of the hydrogen suppression layer 190 and a capacitor 591 is provided. . Below, it demonstrates centering on difference with Embodiment 1, and abbreviate | omits or simplifies description about the same point.

  As shown in FIG. 16, the capacitor 591 includes a lower electrode layer 592, an upper electrode layer 593, and an insulating layer 594. The capacitor 591 is, for example, the capacitor 34 shown in FIG.

  The lower electrode layer 592 is provided on the undercoat layer 120. The lower electrode layer 592 contains a conductive material such as a metal material as a main component. For example, the lower electrode layer 592 contains copper, aluminum, or the like as a main component.

  In the present embodiment, the lower electrode layer 592 is patterned into a predetermined shape such as a rectangle, but is not limited thereto. The lower electrode layer 592 may be formed on the entire surface of the undercoat layer 120.

  The upper electrode layer 593 is provided above the lower electrode layer 592. The upper electrode layer 593 faces the lower electrode layer 592 and forms a capacitor 591 with the lower electrode layer 592.

  The upper electrode layer 593 contains a conductive material such as a metal material as a main component. In this embodiment, the upper electrode layer 593 is formed using the same material as the oxide semiconductor layer 130 as a main component. Specifically, the upper electrode layer 593 is an InGaZnO film with reduced resistance.

  The insulating layer 594 is an insulating layer provided between the lower electrode layer 592 and the upper electrode layer 593. The insulating layer 594 contains, for example, an insulating material such as silicon oxide as a main component.

  As shown in FIG. 16, the insulating layer 594 is formed on the entire upper surface of the undercoat layer 120 so as to cover the lower electrode layer 592 and the hydrogen suppression layer 590. Therefore, the insulating layer 594 is provided in contact with the back gate side of the oxide semiconductor layer 130.

  The hydrogen suppression layer 590 contains the same material as the lower electrode layer 592 as a main component. Specifically, the hydrogen suppression layer 590 contains a metal material such as copper as a main component.

  The shape of the hydrogen suppression layer 590 in plan view is the same as, for example, the modification of the third embodiment (specifically, FIG. 15A). Specifically, the hydrogen suppression layer 590 is provided not only in the non-overlapping regions 202 and 212 but also in the overlapping regions 201 and 211. That is, the hydrogen suppression layer 590 is provided on the entire end surface region 200 and the entire electrode region 210.

  For this reason, as shown in FIG. 16, the hydrogen suppression layer 590 is formed between the insulating layer 594 and the undercoat layer 120 in the direction directly below the electrode portion 151 of the gate electrode layer 150 (that is, the direction directly below the channel region 131). Is provided. Further, it is provided between the gate insulating layer 140 and the undercoat layer 120 in a direction directly below the extending portion 152.

  In this embodiment mode, the hydrogen suppression layer 590 contains the same material as the lower electrode layer 592 as a main component, and thus has conductivity. Since the insulating layer 594 is provided between the hydrogen suppression layer 590 and the oxide semiconductor layer 130, the conductive hydrogen suppression layer 590 can be provided directly below the oxide semiconductor layer 130.

  The hydrogen suppression layer 590 and the lower electrode layer 592 are formed, for example, after the undercoat layer 120 is formed and before the oxide semiconductor layer 135 is formed. For example, after a metal film is formed by a sputtering method or the like, the hydrogen suppression layer 590 and the lower electrode layer 592 having a predetermined shape can be formed by patterning the metal film by a photolithography method and an etching method.

  After the hydrogen suppression layer 590 and the lower electrode layer 592 are formed, an insulating layer 594 is formed. For example, a silicon oxide film is formed as an insulating layer 594 by plasma CVD or the like on the upper surface of the undercoat layer 120 so as to cover the hydrogen suppression layer 590 and the lower electrode layer 592.

  The upper electrode layer 593 is formed in the same process as the oxide semiconductor layer 130. At this time, the resistance of the entire upper electrode layer 593 is reduced in the same manner as the source region 132 and the drain region 133.

  As described above, in the TFT substrate 520 according to the present embodiment, for example, the lower electrode layer 592 provided on the undercoat layer 120 and the lower electrode layer 592 provided above the lower electrode layer 592 are further provided. The hydrogen suppression layer 590 contains the same material as that of the lower electrode layer 592 as a main component.

  Thereby, the region close to the channel region 131 can be covered with the hydrogen suppression layer 590. Accordingly, supply of hydrogen to the channel region 131 can be effectively suppressed.

  In the present embodiment, the example in which the planar shape of the hydrogen suppression layer 590 is the same as that of the modification of the third embodiment is described, but the present invention is not limited to this. The hydrogen suppression layer 590 is, for example, substantially rectangular like the hydrogen suppression layer 490 shown in FIG. 14A, and may be provided only in the non-overlapping regions 202 and 212. Alternatively, the hydrogen suppression layer 590 is substantially U-shaped like the hydrogen suppression layer 190a shown in FIG. 11A, or substantially straight like the hydrogen suppression layer 190b shown in FIG. 12, and only in the non-overlapping region 202. It may be provided.

(Other)
As described above, the thin film transistor substrate according to the present invention has been described based on the above embodiment and the modifications thereof, but the present invention is not limited to the above embodiment.

  For example, in the above embodiment, a part of the hydrogen suppression layer 190 is provided directly below the gate electrode layer 150, that is, a part of the non-overlapping region 202 of the end face region 200 is non-overlapping of the electrode region 210. Although an example of overlapping with the area 212 has been described, the present invention is not limited to this. The hydrogen suppression layer 190 may not overlap the gate electrode layer 150 in plan view. That is, the end surface region 200 may be only the outer region without including the region inside the end surface of the gate electrode layer 150.

  Further, for example, in the above-described embodiment, the example in which the undercoat layer 120 has a stacked structure of the first layer 121 and the second layer 122 has been described. However, the undercoat layer 120 has a single-layer structure. Also good.

  Further, for example, in the above-described embodiment, the example in which the TFT substrate 20 is used in the drive circuit of the organic EL display device 10 has been described. However, the TFT substrate 20 may be used in a drive circuit such as a liquid crystal display.

  In addition, the embodiment can be realized by arbitrarily combining the components and functions in each embodiment without departing from the scope of the present invention, or a form obtained by subjecting each embodiment to various modifications conceived by those skilled in the art. Forms are also included in the present invention.

  The thin film transistor substrate according to the present invention can be widely used in, for example, a display device such as a television set, a personal computer, a mobile phone, a solid-state imaging device such as a digital camera, or other various electric devices.

DESCRIPTION OF SYMBOLS 1 Thin film semiconductor array substrate 10 Organic EL display device 20, 20a, 20b, 20x, 320, 320a, 420, 420a, 520 TFT substrate 21 Bank 30 Pixel 30B, 30G, 30R Sub pixel 31 Pixel circuit 32, 33, 100 Thin film transistor 32d 33d, 180d Drain electrodes 32g, 33g Gate electrodes 32s, 33s, 180s Source electrode 34 Capacitor 40 Organic EL element 41 Anode 42 EL layer 43 Cathode 50 Gate wiring 60 Source wiring 70 Power supply wiring 110 Substrate 120 Undercoat layer 121 First layer 122 Second layer 130, 135 Oxide semiconductor layer 131 Channel region 132 Source region 133 Drain region 140 Gate insulating layer 145 Gate insulating film 150 Gate electrode layer 151 Electrode portion 152 Extension portion 155 Gate metal film 16 Aluminum oxide layer 170 Interlayer insulating layer 170d, 170s Contact holes 190, 190a, 190b, 195, 390, 390a, 490, 490a, 590 Hydrogen suppression layer 190b1 First suppression portion 190b2 Second suppression portion 191 and 191a High resistance region 192 Low Resistance region 200 End surface region 201, 211 Overlapping region 202, 212 Non-overlapping region 210 Electrode region 591 Capacitance 592 Lower electrode layer 593 Upper electrode layer 594 Insulating layer

Claims (12)

A substrate,
An undercoat layer provided above the substrate;
An oxide semiconductor layer provided above the undercoat layer and having a channel region and a source region and a drain region having a lower resistivity than the channel region;
A gate insulating layer provided on the channel region;
A gate electrode layer provided at a position facing the channel region on the gate insulating layer;
A first hydrogen suppression layer that suppresses the permeation of hydrogen provided to cover the surface of the gate electrode layer, the source region and the drain region, and the undercoat layer;
A second hydrogen suppression layer provided on the undercoat layer to suppress hydrogen permeation;
The second hydrogen suppression layer is provided in a region not overlapping with the oxide semiconductor layer in a region along the end surface of the gate electrode layer in a plan view. The thin film transistor substrate according to claim 1, wherein the second hydrogen suppression layer contains the same material as that of the oxide semiconductor layer as a main component. The thin film transistor substrate according to claim 1, wherein the second hydrogen suppression layer contains a metal material as a main component. The thin film transistor substrate according to claim 1, wherein the second hydrogen suppression layer contains aluminum oxide as a main component. further,
A lower electrode layer provided on the undercoat layer;
An upper electrode layer provided above the lower electrode layer and forming a capacitance with the lower electrode layer;
The thin film transistor substrate according to claim 1, wherein the second hydrogen suppression layer contains the same material as that of the lower electrode layer as a main component. The thin film transistor substrate according to claim 4, wherein the second hydrogen suppression layer is further adjacent to or overlaps with the oxide semiconductor layer in plan view. The thin film transistor substrate according to claim 6, wherein the second hydrogen suppression layer is further provided in an entire region overlapping with the gate electrode layer in a plan view. The thin film transistor substrate according to claim 2, wherein the second hydrogen suppression layer is separated from the oxide semiconductor layer. The thin film transistor substrate according to claim 6, wherein the second hydrogen suppression layer is further provided in a region not overlapping with the oxide semiconductor layer in a region overlapping with the gate electrode layer in plan view. The second hydrogen suppression layer is
A first suppression unit in contact with the source region;
A second suppression part in contact with the drain region,
The thin film transistor substrate according to claim 2, wherein the first suppression unit and the second suppression unit are separated from each other. The undercoat layer is
A first layer containing silicon nitride as a main component provided above the substrate;
The thin film transistor substrate according to claim 1, further comprising: a second layer containing silicon oxide as a main component provided on the first layer. The gate electrode layer is
An electrode part having substantially the same shape as the channel region in plan view;
The thin film transistor substrate according to claim 1, further comprising: an extending portion that extends from the electrode portion in a channel width direction.

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