JP2015185610A - Thin film transistor and thin film transistor manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor which can inhibit a decrease in on-state current.SOLUTION: A thin film transistor comprises: a substrate 10; a gate electrode 30; a gate insulation layer 40; a semiconductor layer (oxide semiconductor layer 50) including a channel region opposite to the gate electrode 30 across the gate insulation layer 40; a protection layer 60 located above the semiconductor layer; and a source electrode 80S and a drain electrode 80D which are electrically connected with the semiconductor layer. The semiconductor layer includes: a first region 51 located in a lower layer of the protection layer 60 and located above the gate electrode 30; and second regions 52 located on both sides of the first region 51, respectively, in which a resistance value of an upper region is lower than a resistance value at a lower region. One of the second regions 52 is electrically connected with the source electrode 80S and the other of the second regions 52 is electrically connected with the drain electrode 80D. A distance from a top face of the second region 52 to a top face of the gate insulation layer 40 is smaller than a distance from a top face of the first region 51 to the top face of the gate insulation layer 40.

Description

  The present invention relates to a thin film transistor (TFT) and a method for manufacturing the thin film transistor, and more particularly to an oxide semiconductor thin film transistor having an oxide semiconductor layer as an active layer and a method for manufacturing the same.

  A TFT is widely used as a switching element or a driving element in an active matrix display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device.

  In recent years, an oxide semiconductor TFT using an oxide semiconductor, for example, In—Ga—Zn—O as a channel layer has been actively developed as a next-generation TFT. Oxide semiconductor TFTs have already been put into practical use and are used in mobile small display devices and large display devices.

  As an oxide semiconductor TFT, a bottom gate type or top gate type structure is known.

  An oxide semiconductor TFT having a bottom gate type structure is similar in manufacturing process to a bottom gate type amorphous silicon TFT currently commercialized as a driving element for a liquid crystal display. There is a problem that the parasitic capacitance generated in the intersection region with the source electrode or the drain electrode is increased.

  On the other hand, the top gate type oxide semiconductor TFT does not have the above-mentioned parasitic capacitance problem in the bottom gate type structure, but the manufacturing process is different from the bottom gate type amorphous silicon TFT, so that it is compatible with the manufacturing equipment. Absent.

  For this reason, an oxide semiconductor TFT having a bottom gate structure that has high consistency with manufacturing equipment and low parasitic capacitance has been proposed (Patent Document 1). Patent Document 1 discloses an oxide semiconductor TFT having a bottom gate structure using an oxide semiconductor layer having a channel region and an offset region (a source region and a drain region).

JP 2012-151460 A

  An oxide semiconductor TFT having a bottom-gate structure having an offset region (a source region and a drain region) has a problem that an on-current is lowered.

  The present invention has been made to solve such problems, and is a bottom-gate type oxide semiconductor TFT having a source region and a drain region in an oxide semiconductor layer, and suppresses a decrease in on-current. It is an object to provide a thin film transistor that can be used.

  In order to achieve the above object, a thin film transistor according to one embodiment of the present invention includes a substrate, a gate electrode located above the substrate, a gate insulating layer located above the gate electrode, and the gate insulating layer. A semiconductor layer including a channel region opposed to the gate electrode, a protective layer positioned above the semiconductor layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer, The semiconductor layer is located below the protective layer and located above the gate electrode, and located on both sides of the first region, and the resistance value of the upper region is lower than the resistance value of the lower region. A second region, wherein one of the second regions is electrically connected to the source electrode, the other of the second regions is electrically connected to the drain electrode, and an upper surface of the second region To the game Wherein the distance to the upper surface of the insulating layer is smaller than the distance from the upper surface of the first region to the upper surface of the gate insulating layer.

  Since the total carrier path between the source electrode and the drain electrode can be shortened, a decrease in on-current can be suppressed and a high on-current can be maintained.

It is an example of sectional drawing which shows the structure of the thin-film transistor 1 which concerns on embodiment of this invention. It is sectional drawing which shows the channel path of the thin-film transistor of a comparative example. It is sectional drawing which shows the channel path of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of the board | substrate preparation process in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of the undercoat formation process in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of the gate electrode formation process in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of the gate insulating layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of oxide semiconductor layer formation (before thickness reduction and resistance reduction) in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of the protective layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of the thin film formation process of the oxide semiconductor layer in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of the resistance reduction process of the oxide semiconductor layer in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of the interlayer insulation layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is sectional drawing of the source electrode and drain electrode formation process in the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. 1 is a partially cutaway perspective view of an organic EL display device according to an embodiment of the present invention. FIG. 5 is an electric circuit diagram of a pixel circuit in the organic EL display device shown in FIG. 4.

  A thin film transistor according to one embodiment of the present invention is opposite to the gate electrode with the substrate, the gate electrode located above the substrate, the gate insulating layer located above the gate electrode, and the gate insulating layer in between A semiconductor layer including a channel region; a protective layer located above the semiconductor layer; and a source electrode and a drain electrode electrically connected to the semiconductor layer, wherein the semiconductor layer is formed of the protective layer. A first region located in a lower layer and located above the gate electrode, and a second region located on each side of the first region, the resistance value of the upper region being lower than the resistance value of the lower region, One of the second regions is electrically connected to the source electrode, and the other of the second regions is electrically connected to the drain electrode, from the upper surface of the second region to the upper surface of the gate insulating layer The distance of Wherein the from the upper surface of the serial first region is smaller than the distance to the upper surface of the gate insulating layer.

  According to this aspect, the distance from the upper surface of the second region to the upper surface of the gate insulating layer is smaller than the distance from the upper surface of the first region to the upper surface of the gate insulating layer. Thereby, since the distance that carriers move in the stacking direction in the semiconductor layer can be shortened, the total carrier path between the source electrode and the drain electrode can be shortened. Therefore, a reduction in on-current can be suppressed and a high on-current can be maintained.

  Furthermore, in this aspect, a front carrier path formed in a lower portion (front channel) on the gate electrode side in the first region and a back carrier path formed in an upper region (back channel) on the protective layer side in the first region, The distance (interval) can be increased. Thereby, the off-current can be reduced and the deterioration of the TFT operation due to the defect on the back channel side can be suppressed.

  As described above, according to the thin film transistor of one embodiment of the present invention, an oxide semiconductor TFT which has excellent on characteristics and off characteristics can be realized.

  In the thin film transistor according to one embodiment of the present invention, the contact point between the upper surface end of the second region and the side surface of the first region is located below the position of ½ of the thickness of the first region. Good.

  According to this aspect, the interval between the carrier path in the second region and the back carrier path in the first region can be made larger than the interval between the carrier path in the second region and the front carrier path in the first region. Therefore, a high on-current can be maintained more effectively, and the off-current can be further reduced.

  In the thin film transistor according to one embodiment of the present invention, the thickness of the semiconductor layer in the second region is preferably at least 15 nm or more.

  According to this aspect, the film thickness can be sufficient to precipitate or diffuse the resistance-reducing element when forming the second region. Thereby, the resistance value of the semiconductor layer in the second region portion can be sufficiently lowered.

  In the thin film transistor according to one embodiment of the present invention, it is preferable that an end portion of the upper surface of the first region overlaps an end portion of the lower surface of the protective layer in a top view.

  According to this aspect, the semiconductor layer can be processed using the protective layer as a mask. As a result, a convex semiconductor layer having a second region having a thickness smaller than that of the first region can be formed, so that the manufacturing cost can be reduced.

  In the thin film transistor according to one embodiment of the present invention, the protective layer may be formed using a material containing an organic substance as a main component.

  When the protective layer is made of a material mainly composed of an organic substance, the amount of fixed charges existing in the protective layer increases, and the back of the upper part of the first region of the semiconductor layer is affected by the amount of fixed charges. Although the channel path is easily formed, in the thin film transistor of this embodiment, the distance between the front channel path and the back channel path can be increased as described above, so even if the protective layer is made of a material mainly composed of organic matter, The amount of current flowing through the back channel path can be suppressed.

  The thin film transistor manufacturing method according to one embodiment of the present invention includes a step of preparing a substrate, a step of forming a gate electrode above the substrate, a step of forming a gate insulating layer above the gate electrode, Forming a semiconductor layer above the gate insulating layer so as to include at least a first region facing the gate electrode; and exposing the semiconductor layer on both side portions of the first region. A step of forming a protective layer above, a step of thinning a portion of the semiconductor layer exposed from the protective layer, and a resistance value of an upper region of the thinned region is lower than a resistance value of a lower region. A step of forming a second region on both sides of the first region by performing a lowering process, and a source electrode electrically connected to one of the second regions and the other of the second regions are electrically connected Dray Characterized in that it comprises a step of forming an electrode, the.

  According to this aspect, it is possible to form a semiconductor layer in which the thickness of the second region is thinner than that of the first region. That is, the distance from the upper surface of the second region to the upper surface of the gate insulating layer can be made smaller than the distance from the upper surface of the first region to the upper surface of the gate insulating layer. Thereby, a TFT that has a short carrier path in the semiconductor layer and can suppress a decrease in on-current can be obtained.

  Further, the formed semiconductor layer has a large distance between the front channel path in the first region and the back channel path in the first region. As a result, off-current can be reduced and deterioration of TFT operation due to defects on the back channel side can be suppressed.

  As described above, according to the method for manufacturing a thin film transistor according to one embodiment of the present invention, a TFT having excellent on characteristics and off characteristics can be manufactured.

  In the thin film transistor according to one embodiment of the present invention, in the step of thinning the semiconductor layer, the contact point between the upper end portion of the second region and the side surface of the first region is 1 / th of the thickness of the first region. The exposed portion of the semiconductor layer may be thinned so as to be positioned below the position 2.

  According to this aspect, the semiconductor layer in which the distance between the carrier path in the second region and the back carrier path in the first region is larger than the distance between the carrier path in the second region and the front carrier path in the first region. Can be formed. Therefore, an oxide semiconductor TFT having further excellent on and off characteristics can be obtained.

  In the thin film transistor according to one embodiment of the present invention, in the step of thinning the semiconductor layer, the exposed portion of the semiconductor layer is formed so that the thickness of the semiconductor layer in the second region is at least 15 nm or more. It should be thin.

  According to this aspect, the semiconductor layer can be thinned so as to leave a film thickness sufficient for precipitating or diffusing the low resistance element when forming the second region. Thereby, a semiconductor layer having the second region having a desired low resistance value can be formed.

  In the thin film transistor according to one embodiment of the present invention, in the step of thinning the semiconductor layer, the exposed portion of the semiconductor layer may be thinned by etching using the protective layer as a mask.

  According to this aspect, since the oxide semiconductor layer is processed using the protective layer as a mask, portions exposed from the protective layer (portions on both sides of the first region in the semiconductor layer) can be thinned, so that the manufacturing cost can be reduced. The cost can be reduced.

  In the thin film transistor according to one embodiment of the present invention, the protective layer may be formed using a material containing an organic substance as a main component.

  According to this aspect, even when the protective layer is made of a material mainly composed of an organic substance and the protective layer contains a large amount of fixed charges, the amount of current flowing through the back channel path is effectively suppressed. can do.

(Embodiment)
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present invention. Therefore, numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps (steps), order of steps, and the like shown in the following embodiments are merely examples and are intended to limit the present invention. is not. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements.

  Each figure is a schematic diagram and is not necessarily illustrated strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.

[Configuration of thin film transistor]
FIG. 1 is an example of a cross-sectional view illustrating a configuration of a thin film transistor 1 according to an embodiment of the present invention.

  As shown in FIG. 1, a thin film transistor 1 according to this embodiment is a bottom-gate oxide semiconductor TFT in which an oxide semiconductor layer including an offset region is a channel layer.

  The thin film transistor 1 includes a substrate 10, an undercoat layer 20, a gate electrode 30, a gate insulating layer 40, an oxide semiconductor layer 50, a protective layer 60, an interlayer insulating layer 70, a source electrode 80S, and a drain electrode 80D. With. Note that the thin film transistor 1 in this embodiment employs a top contact structure.

  Hereinafter, each component of the thin film transistor 1 according to the present embodiment will be described in detail.

  The substrate 10 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, or high heat resistant glass. The substrate 10 is not limited to a glass substrate but may be a resin substrate or the like. Further, the substrate 10 may be a sheet-like or film-like flexible substrate such as a flexible glass substrate or a flexible resin substrate instead of a rigid substrate.

The undercoat layer 20 is formed on the substrate 10. As the undercoat layer 20, for example, a silicon nitride film (SiN _x ), a silicon oxide film (SiO _y ), a silicon oxynitride film (SiO _y N _x ), or the like is used. The undercoat layer 20 has a function of preventing impurities such as sodium and phosphorus contained in the substrate 10 that is a glass substrate from entering the gate electrode 30, the gate insulating layer 40, and the channel layer 50. The film thickness of the undercoat layer 20 is preferably set to 100 nm to 500 nm. Note that the undercoat layer 20 is not necessarily formed.

  The gate electrode 30 is located above the substrate 10 and is patterned in a predetermined shape on the undercoat layer 20. The gate electrode 30 is an electrode having a single layer structure or a multilayer structure such as a conductive material such as a metal or an alloy thereof, for example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium. (Ti), chromium (Cr), molybdenum tungsten (MoW), or the like. The film thickness of the gate electrode 30 is preferably set to 50 nm to 300 nm.

  The gate insulating layer 40 is formed so as to be located above the gate electrode 30. In the present embodiment, the gate insulating layer 40 is formed on the undercoat layer 20 so as to cover the gate electrode 30. As the gate insulating layer 40, a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a tantalum oxide film or an aluminum oxide film, or a laminated film of these can be used. In the present embodiment, the gate insulating layer 40 is, for example, a stacked film of a silicon oxide film and a silicon nitride film. The film thickness of the gate insulating layer 40 can be designed in consideration of the breakdown voltage of the TFT, and is preferably 50 nm to 500 nm, for example.

  The oxide semiconductor layer 50 is a semiconductor layer including a channel region facing the gate electrode 30 with the gate insulating layer 40 interposed therebetween. The oxide semiconductor layer 50 is formed on the gate insulating layer 40 in a predetermined shape, and includes a first region 51 and second regions 52 formed on both sides of the first region 51.

  In the oxide semiconductor layer 50, the thickness of the portion where the second region 52 is formed is smaller than the thickness of the portion where the first region 51 is formed. That is, the distance from the upper surface of the second region 52 to the upper surface of the gate insulating layer 40 is smaller than the distance from the upper surface of the first region 51 to the upper surface of the gate insulating layer 40.

  The first region 51 is a region located below the protective layer 60 and above the gate electrode 30 in the oxide semiconductor layer 50, and faces the gate electrode 30 with the gate insulating layer 40 interposed therebetween. It is a part including the channel region located.

  The second region 52 is a low-resistance oxide semiconductor layer (offset region) that is located on each side of the first region 51 in the oxide semiconductor layer 50 and has a resistance value lower than that of the first region 51. For example, the second region 52 can be formed by partially reducing the resistance value of the oxide semiconductor layer by selectively performing plasma irradiation such as Ar plasma or hydrogen plasma on the oxide semiconductor layer.

  The source region 52S, which is one of the second regions 52, is located on one end side of the first region 51 in the channel direction and is electrically connected to the source electrode 80S. In the source region 52S, the resistance value of the upper region (region on the interlayer insulating layer 70 side) is lower than the resistance value of the lower region (region on the gate insulating layer 40 side). That is, in the source region 52S, the resistance values are different in the stacking direction, and the resistance value of the upper layer portion is lower than the resistance value of the lower layer portion.

  Further, the drain region 52D which is the other of the second regions 52 is located on the other end side of the first region 51 in the channel direction and is electrically connected to the drain electrode 80D. Also in the drain region 52D, the resistance value in the upper region is lower than the resistance value in the lower region. That is, also in the drain region 52D, the resistance value is different in the stacking direction, and the resistance value of the upper layer portion is lower than the resistance value of the lower layer portion.

The first region 51 and the second region 52 constituting the oxide semiconductor layer 50 are made of the same material. As a material of the oxide semiconductor layer 50, for example, a transparent amorphous oxide semiconductor (TAOS) is used. In this embodiment, the oxide semiconductor layer 50 is formed with a sputtering apparatus using InGaZnO _x (IGZO) which is an oxide containing indium (In), gallium (Ga), and zinc (Zn).

  A thin film transistor using a transparent amorphous oxide semiconductor has high carrier mobility and is suitable for a large-screen and high-definition display device. Further, since the transparent amorphous oxide semiconductor can be formed at a low temperature, it can be easily formed on a flexible substrate.

  The thickness of the oxide semiconductor layer 50 in the first region 51 is, for example, 30 nm to 500 nm. In addition, the thickness of the oxide semiconductor layer 50 in the second region 52 (source region 52S and drain region 52D) may be thinner than the thickness of the oxide semiconductor layer 50 in the first region 51, but at least 15 nm or more. For example, the thickness may be 15 nm to 30 nm. In the present embodiment, the film thickness of the source region 52S and the film thickness of the drain region 52D are the same, but may be different.

  The protective layer 60 is an insulating layer formed in a predetermined shape so as to cover a portion of the first region 51 in the oxide semiconductor layer 50. The protective layer 60 is a layer (channel protective layer) that protects the first region 51 and functions as an etching stopper layer.

  The protective layer 60 may be formed of a material containing an organic substance as a main component, or may be formed of an inorganic substance such as a silicon oxide film. In the present embodiment, the protective layer 60 is made of a material whose main component is an organic substance. The protective layer 60 may be a single layer film or a laminated film.

  The interlayer insulating layer 70 is an insulating layer formed so as to cover the protective layer 60 and the oxide semiconductor layer 50 (the portions of the source region 52S and the drain region 52D). The interlayer insulating layer 70 may be formed of a material mainly containing an organic substance, or may be formed of an inorganic material such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film. . The interlayer insulating layer 70 may be a single layer film or a laminated film.

  The silicon oxide film generates less hydrogen during film formation than the silicon nitride film. Therefore, by using a silicon oxide film as the interlayer insulating layer 70, performance degradation of the oxide semiconductor layer 50 due to hydrogen reduction can be suppressed. Further, by using an aluminum oxide film as the interlayer insulating layer 70, hydrogen and oxygen generated in the upper layer can be blocked by the aluminum oxide film. For these reasons, for example, a laminated film having a three-layer structure of a silicon oxide film, an aluminum oxide film, and a silicon oxide film is preferably used as the interlayer insulating layer 70.

  An opening (contact hole) is formed in the interlayer insulating layer 70 so as to penetrate a part of the interlayer insulating layer 70. The source region 52S and the drain region 52S of the oxide semiconductor layer 50 are connected to the source electrode 80S and the drain electrode 80D through the opening of the interlayer insulating layer 70.

  The source electrode 80S and the drain electrode 80D are formed by patterning in a predetermined shape on the interlayer insulating layer 70. The source electrode 80S is connected to the source region 52S of the oxide semiconductor layer 50 through an opening formed in the interlayer insulating layer 70, and the drain electrode 80D is connected through the opening formed in the interlayer insulating layer 70. And connected to the drain region 52D of the oxide semiconductor layer 50.

  The source electrode 80S and the drain electrode 80D are electrodes having a single layer structure or a multilayer structure such as a conductive material and an alloy thereof. Examples of the material of the source electrode 80S and the drain electrode 80D include molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), chromium (Cr), and molybdenum tungsten alloy (MoW). Alternatively, a copper manganese alloy (CuMn) or the like can be used. The film thickness of the source electrode 80S and the drain electrode 80D is preferably set to, for example, 50 nm to 300 nm.

  Next, the function and effect of the thin film transistor 1 according to this embodiment will be described with reference to FIGS. 2A and 2B. FIG. 2A is a cross-sectional view showing a channel path of a thin film transistor of a comparative example. FIG. 2B is a cross-sectional view showing a channel path of the thin film transistor according to the embodiment of the present invention.

  In the thin film transistor 1 ′ of the comparative example shown in FIG. 2A, the thickness of the oxide semiconductor layer 50 ′ is constant, the thickness of the oxide semiconductor layer 50 ′ corresponding to the first region 51 portion, and the first region 51 The thickness of the oxide semiconductor layer 50 ′ corresponding to the second region 52 ′ (source region 52S ′ and drain region 52D ′) on both sides is the same. That is, the distance from the upper surface of the second region 52 ′ (source region 52S ′ and drain region 52D ′) to the upper surface of the gate insulating layer 40 is the same as the distance from the upper surface of the first region 51 to the upper surface of the gate insulating layer 40. It has become.

  In the case of manufacturing the thin film transistor 1 ′ of the comparative example shown in FIG. 2A, for example, after forming an oxide semiconductor layer having a predetermined shape, the resistance other than the first region 51 is reduced by a method such as Ar plasma or hydrogen plasma. Thus, the second region 52 ′ (source region 52S ′ and drain region 52D ′) is formed as an offset region (low resistance region) having a lower resistance than the first region 51.

  Thus, when the source region 52S ′ and the drain region 52D ′ are formed in the oxide semiconductor layer by Ar plasma, hydrogen plasma, or the like, the diffusion thickness (diffusion depth) of Ar or hydrogen into the oxide semiconductor layer is about several nm. It is thought that it becomes. Therefore, in the source region 52S 'and the drain region 52D' in the oxide semiconductor layer 50 ', the resistance value in the upper region (upper portion) is lower than the resistance value in the lower region (lower portion).

  In this case, in the case of an oxide semiconductor TFT having a top-gate structure, the carrier path in the offset region is formed in the upper region of the oxide semiconductor layer, and the carrier path in the region other than the offset region is also oxidized close to the gate electrode. Since it is formed in the region above the physical semiconductor layer, the carrier path becomes a straight line and a high on-current can be maintained.

  However, as shown in FIG. 2A, in the thin film transistor 1 ′ which is an oxide semiconductor TFT having a bottom gate type structure, the carrier path in the second region 52 ′ (the source region 52S ′ and the drain region 52D ′) is the oxide semiconductor layer 50. The carrier path in the first region 51 (the lower region of the protective layer 60) is formed in the lower region of the oxide semiconductor layer 50 ′ adjacent to the gate electrode 30. Therefore, in the carrier path between the second region 52 ′ and the first region 51, carriers move in the thickness direction (stacking direction) in the first region 51 or the second region 52 ′. That is, carriers move in the stacking direction in the oxide semiconductor layer 50 '. As a result, the total carrier path between the source electrode 80S and the drain electrode 80D becomes longer and the resistance value becomes larger than that of the oxide semiconductor TFT having the top-gate structure. As a result, there is a problem that the on-current is lowered.

  On the other hand, in the thin film transistor 1 in the present embodiment shown in FIG. 2B, the distance from the upper surface of the second region 52 to the upper surface of the gate insulating layer 40 is from the upper surface of the first region 51 to the upper surface of the gate insulating layer 40. It is smaller than the distance. That is, in this embodiment, the oxide semiconductor layer 50 corresponding to the second region 52 (the source region 52S and the drain region 52D) has a film thickness of the oxide semiconductor layer 50 corresponding to the first region 51. It is thinner than the film thickness.

  As a result, as shown in FIG. 2B, the distance that carriers move in the stacking direction in the oxide semiconductor layer 50 can be shortened, so the total between the source electrode 80S and the drain electrode 80D (between the source and drain electrodes). The carrier path can be shortened. Therefore, a reduction in on-current can be suppressed and a high on-current can be maintained.

  Further, like the thin film transistor 1 in this embodiment, the thickness of the oxide semiconductor layer 50 in the second region 52 is made thinner than the thickness of the oxide semiconductor layer 50 in the first region 51. The distance between the front carrier path formed in the lower part (front channel) on the gate electrode 30 side in the first region 51 and the back carrier path formed in the upper region (back channel) on the protective layer 60 side in the first region 51 ( (Interval) can also be increased. Thereby, the off-current can be reduced and the deterioration of the TFT operation due to the defect on the back channel side can be suppressed.

  Thus, according to the thin film transistor 1 according to the present embodiment, an oxide semiconductor TFT having excellent on characteristics and off characteristics can be realized. As a result, a pixel circuit of an organic EL display device that requires a drive transistor that requires excellent on characteristics and a switching transistor that requires excellent off characteristics can be configured by the same thin film transistor 1. Therefore, since all TFTs in the TFT array substrate of the organic EL display device can be formed at the same time, the organic EL display device can be manufactured at a low cost.

  Further, as shown in FIG. 2B, the contact point P between the upper surface end of the second region 52 (source region 52S or drain region 52D) and the side surface of the first region 51 is the oxide semiconductor layer 50 in the first region 51 part. It is good to be located below the position of 1/2 of the thickness L. That is, the distance L2 from the contact P to the lower surface of the oxide semiconductor layer 50 in the first region 51 portion is preferably smaller than the distance L1 from the contact P to the upper surface of the oxide semiconductor layer 50 in the first region 51 portion.

  Thereby, the interval between the carrier path in the second region 52 and the back carrier path in the first region 51 can be made larger than the interval between the carrier path in the second region 52 and the front carrier path in the first region 51. . Therefore, a high on-current can be maintained more effectively, and the off-current can be further reduced.

  In this embodiment, the thickness of the oxide semiconductor layer 50 in the second region 52 is preferably at least 15 nm or more.

  When the second region 52 is formed in the oxide semiconductor layer 50, as described above, for example, a portion other than the first region 51 of the oxide semiconductor layer (a portion exposed from the protective layer 60) is made of Ar plasma, hydrogen plasma, or the like. The resistance is reduced by plasma treatment.

  Specifically, Ar is diffused in the oxide semiconductor layer 50 by Ar plasma irradiation to deposit In in the oxide semiconductor layer 50 to partially reduce the resistance of the oxide semiconductor layer 50, thereby forming the second region 52. (Source region 52S and drain region 52D) are formed. Alternatively, hydrogen is diffused into the oxide semiconductor layer 50 by hydrogen plasma irradiation to partially reduce the resistance of the oxide semiconductor layer 50 to form the second region 52 (the source region 52S and the drain region 52D).

  At this time, by setting the thickness of the oxide semiconductor layer 50 in the second region 52 portion to 15 nm or more, a low-resistance element (such as In or H) at the time of forming the second region 52 is precipitated or diffused. Sufficient film thickness.

  Specifically, when the second region 52 is formed by Ar plasma irradiation, the oxide semiconductor layer 50 in a portion corresponding to the second region 52 has a thickness of 15 nm or more, so that the oxide semiconductor is irradiated by Ar plasma irradiation. In can be sufficiently deposited in the layer 50. Alternatively, in the case where the second region 52 is formed by hydrogen plasma irradiation, the thickness of the oxide semiconductor layer 50 corresponding to the second region 52 is set to 15 nm or more so that the oxide semiconductor layer 50 can be formed by hydrogen plasma irradiation. It is possible to cause sufficient hydrogen diffusion. Thereby, the resistance value of the oxide semiconductor layer 50 in the second region 52 can be sufficiently reduced.

  In this embodiment, the upper end portion of the first region 51 in the oxide semiconductor layer 50 and the lower end portion of the protective layer 60 overlap with each other in a top view. More specifically, in top view, one end of the first region 51 in the oxide semiconductor layer 50 overlaps with one end of the protective layer 60, and the other end of the first region 51 in the oxide semiconductor layer 50. The end and the other end of the protective layer 60 overlap. For example, as shown in FIG. 2B, both side surfaces of the first region 51 and both side surfaces of the protective layer 60 in the oxide semiconductor layer 50 are flush with each other in a cross-sectional view.

  Accordingly, by processing the oxide semiconductor layer 50 using the protective layer 60 as a mask, the convex oxide semiconductor layer 50 having the second region 52 having a thickness smaller than that of the first region 51 can be formed. Therefore, the manufacturing cost can be reduced.

  Further, in the present embodiment, the protective layer 60 is made of a material whose main component is an organic substance.

  A protective layer 60 is disposed on the oxide semiconductor layer 50 in the first region 51 portion. Since fixed charges exist in the protective layer 60, carriers are easily attracted above the first region 51. For example, when positive fixed charges are present in the protective layer 60, negative carriers are attracted to a region above the first region 51 in the oxide semiconductor layer 50. As a result, in addition to the normal channel path, a channel is formed in the upper region (for example, near the interface with the protective layer 60), which is the region on the protective layer 60 side (region opposite to the gate electrode 30) in the first region 51. (Back channel) appears and adversely affects the transistor characteristics.

  In this case, if the protective layer 60 is made of a material mainly composed of an organic substance, the amount of fixed charges existing in the protective layer 60 increases. As a result, the oxide semiconductor layer 50 is more easily affected by the back channel path formed in the region above the first region 51.

  On the other hand, in the thin film transistor 1 in the present embodiment, only the second region 52 is thinned, and the first region 51 is not thinned. Thereby, in the oxide semiconductor layer 50 in the first region 51 portion, as described above, the distance between the front channel path and the back channel path is large, so that the oxide semiconductor layer 50 is not easily affected by the fixed charge of the protective layer 60. . Therefore, even if the protective layer 60 is made of a material mainly composed of an organic substance, the amount of current flowing through the back channel path can be suppressed.

[Thin Film Transistor Manufacturing Method]
Next, a method for manufacturing the thin film transistor 1 according to the present embodiment will be described with reference to FIGS. 3A to 3J. 3A to 3J are cross-sectional views of each step in the method of manufacturing the thin film transistor according to the embodiment of the present invention. Note that although one thin film transistor is described in this embodiment mode, the same applies to the case where a plurality of thin film transistors 1 are simultaneously formed as a TFT array.

  First, as shown in FIG. 3A, a substrate 10 is prepared. For example, a glass substrate is prepared as the substrate 10.

  Next, as shown in FIG. 3B, an undercoat layer 20 is formed on the substrate 10. An undercoat layer 20 composed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like is formed on the substrate 10 by plasma CVD (Chemical Vapor Deposition) or the like.

Next, as shown in FIG. 3C, the gate electrode 30 is formed above the substrate 10. In this embodiment, after a metal film (gate metal film) made of molybdenum tungsten (MoW) is formed on the undercoat layer 20 by sputtering, the metal film is patterned using a photolithography method and a wet etching method. Thus, a gate electrode 30 having a predetermined shape was formed. MoW wet etching can be performed using, for example, a chemical solution in which phosphoric acid (HPO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed in a predetermined composition.

Next, as illustrated in FIG. 3D, the gate insulating layer 40 is formed above the gate electrode 30. In the present embodiment, the gate insulating layer 40 is formed over the entire substrate 10 by plasma CVD or the like so as to cover the gate electrode 30. The gate insulating layer 40 is, for example, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, a tantalum oxide film, an aluminum oxide film, or a laminated film thereof. As an example, when a silicon nitride film is formed by plasma CVD, silane gas (SiH ₄ ), ammonia gas (NH ₃ ), and nitrogen gas (N ₂ ) are used as the introduction gas.

  Next, as illustrated in FIG. 3E, the oxide semiconductor layer 50 </ b> A is formed over the gate insulating layer 40 so as to include at least a portion to be the first region 51 facing the gate electrode 30. In this embodiment, after an oxide semiconductor film is formed over the gate insulating layer 40 by sputtering or the like, patterning is performed using a photolithography method, a wet etching method, or the like, so that a channel is formed in a portion facing the gate electrode 30. An island-shaped oxide semiconductor layer 50A is formed so as to have a region.

In this embodiment, the material of the oxide semiconductor layer 50A is an InGaZnO _X transparent amorphous oxide semiconductor. In this case, in the step of forming the oxide semiconductor film by sputtering, using In, Ga, and Zn as target materials, argon (Ar) gas as an inert gas flows into the vacuum chamber and oxygen as a reactive gas. A gas containing (O ₂ ) is introduced, and a voltage having a predetermined power density is applied to the target material. Thereby, a transparent amorphous InGaZnO film can be formed.

When the oxide semiconductor film is processed into the oxide semiconductor layer 50A having a predetermined shape by using a photolithography method and a wet etching method, specifically, first, a resist having a predetermined shape is formed over the oxide semiconductor film. The island-shaped oxide semiconductor layer 50A can be formed by removing the oxide semiconductor film in a region where the resist is not formed by wet etching. Note that in the case where the oxide semiconductor film is InGaZnO _X , for example, a chemical solution in which phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed is used as the etching solution. Good.

  Next, as illustrated in FIG. 3F, the protective layer 60 is formed above the first region 51 so that a part of the oxide semiconductor layer 50A is exposed. Specifically, the protective layer 60 is formed so that the oxide semiconductor layer 50A on both sides of the portion to be the first region 51 is exposed. In this embodiment, the protective layer 60 is selectively formed in a portion facing the gate electrode 30 with the oxide semiconductor layer 50A interposed therebetween. For example, an insulating film is formed on the entire surface of the substrate 10 so as to cover the oxide semiconductor layer 50A and the gate insulating layer 40, and the insulating film is patterned using a wet etching method or a dry etching method, thereby forming a protective layer having a predetermined shape. 60 can be formed. Note that the protective layer 60 may be formed using a material containing an organic substance as a main component, or may be formed using an inorganic substance such as a silicon oxide film, but in this embodiment, the organic substance is mainly used. The protective layer 60 was formed using the material used as a component.

  Next, the portion of the oxide semiconductor layer 50A exposed from the protective layer 60 is thinned. In this embodiment, as illustrated in FIG. 3G, by etching using the protective layer 60 as a mask, a portion of the oxide semiconductor layer 50A exposed from the protective layer 60 is selectively etched to be thinned. Accordingly, the oxide semiconductor layer 50A can be formed so that a portion facing the gate electrode 30 protrudes.

  In this embodiment, since the oxide semiconductor layer 50A is etched using the protective layer 60 as a mask, both side edges of the first region 51 and both side edges of the protective layer 60 overlap each other in the oxide semiconductor layer 50. Can be processed as follows. That is, the self-alignment can be performed so that both side surfaces of the first region 51 in the oxide semiconductor layer 50 and the both side surfaces of the protective layer 60 are flush with each other.

Note that the etching method may be either wet etching or dry etching, but in this embodiment, the oxide semiconductor layer 50A is etched by dry etching using BCL ₃ gas.

  Next, as shown in FIG. 3H, the first region is obtained by performing a process in which the resistance value of the upper region is lower than the resistance value of the lower region of the thinned region (concave portion) of the oxide semiconductor layer 50A. A source region 52S and a drain region 52D are formed as the second region 52 on both sides of 51.

  In this embodiment, the protective layer 60 is used as a mask to irradiate plasma, thereby reducing the resistance value of the thinned region (concave portion) of the oxide semiconductor layer 50A to be lower than the resistance value of the non-thinned region (convex portion). The resistance value in the upper region in the thinned region (concave portion) is lower than the resistance value in the lower region. Thus, the oxide semiconductor layer 50 having the first region 51 that is a non-thinned region that is not irradiated with plasma and the second region 52 (offset region) that is a thinned region irradiated with plasma can be formed. it can.

  Note that as the plasma irradiation, for example, Ar plasma irradiation or hydrogen plasma irradiation can be used. By using these plasma irradiations, the resistance value of the oxide semiconductor layer 50A can be sufficiently reduced.

  As described above, in this embodiment, the processing step (etching step) of the oxide semiconductor layer 50A and the resistance reduction step of the oxide semiconductor layer 50A are performed using the protective layer 60 as a mask. Accordingly, only the region where the thickness of the oxide semiconductor layer 50A is thin (thinned region) can be lowered in resistance. As a result, the oxide semiconductor layer 50 can be formed in such a shape that the upper end portion of the second region 52 whose resistance is lowered is in contact with the side surface of the thick region (first region 51).

  Next, as illustrated in FIG. 3I, an interlayer insulating layer 70 is formed over the gate insulating layer 40 so as to cover the exposed portions of the protective layer 60 and the oxide semiconductor layer 50. The interlayer insulating layer 70 may be formed using a material whose main component is an organic substance, or may be formed using a material whose main component is an inorganic substance.

After that, an opening (contact hole) is formed in the interlayer insulating layer 70 so as to expose part of the source region 52S and the drain region 52D of the oxide semiconductor layer 50. Specifically, an opening is formed over the source region 52S and the drain region 52D of the oxide semiconductor layer 50 by etching and removing a part of the interlayer insulating layer 70 by a photolithography method and an etching method. For example, when the interlayer insulating layer 70 is a silicon oxide film, the opening can be formed in the silicon oxide film by a dry etching method using a reactive ion etching (RIE) method. In this case, for example, carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ) can be used as the etching gas.

  Next, as illustrated in FIG. 3J, a source electrode 80S electrically connected to the source region 52S and a drain electrode 80D electrically connected to the drain region 52D are formed. In the present embodiment, after a metal film (source / drain metal film) is formed on the interlayer insulating layer 70 by sputtering so as to fill the opening formed in the interlayer insulating layer 70, a photolithography method and a wet etching method are performed. By using this and patterning the metal film, a source electrode 80S and a drain electrode 80D having a predetermined shape are formed.

  As described above, according to the method for manufacturing the thin film transistor 1 in this embodiment, the protective layer 60 is formed above the portion facing the gate electrode 30 (the first region 51) so that a part of the oxide semiconductor layer 50A is exposed. Then, the portion exposed from the protective layer 60 in the oxide semiconductor layer 50A is thinned, and then the thinned region is subjected to a process in which the resistance value in the upper region is lower than the resistance value in the lower region. Region 52 (source region 52S and drain region 52D) is formed.

  Thereby, the oxide semiconductor layer 50 in which the film thickness of the second region 52 is thinner than that of the first region 51 can be formed. Thus, an oxide semiconductor TFT that has a short carrier path in the oxide semiconductor layer 50 and can suppress a decrease in on-state current can be obtained.

  In this case, in the first region 51 portion of the formed oxide semiconductor layer 50, the distance between the front channel path and the back channel path is large. As a result, an oxide semiconductor TFT can be obtained that can reduce off-current and suppress degradation of TFT operation due to defects on the back channel side.

  As described above, according to the method for manufacturing the thin film transistor 1 in this embodiment, an oxide semiconductor TFT having excellent on characteristics and off characteristics can be manufactured.

  In the manufacturing method according to the present embodiment, in the step of thinning the oxide semiconductor layer 50 </ b> A, the contact point between the upper end portion of the second region 52 and the side surface of the first region 51 is 1 in the thickness of the first region 51. A portion of the oxide semiconductor layer 50A exposed from the protective layer 60 is thinned so as to be positioned below the position / 2.

  Thus, an oxide in which the distance between the carrier path in the second region 52 and the back carrier path in the first region 51 is larger than the distance between the carrier path in the second region 52 and the front carrier path in the first region 51. The semiconductor layer 50 can be formed. Therefore, an oxide semiconductor TFT having further excellent on and off characteristics can be obtained.

  Further, in the manufacturing method in this embodiment, in the step of thinning the oxide semiconductor layer 50A, the protective layer 60 is included in the oxide semiconductor layer 50A so that the thickness of the second region 52 portion is at least 15 nm or more. The exposed part is thinned.

  Accordingly, the oxide semiconductor layer 50A can be thinned so as to leave a film thickness sufficient for precipitating or diffusing the low-resistance element when forming the second region 52. Thereby, the oxide semiconductor layer 50 having the second region 52 having a desired low resistance value can be formed.

  In the manufacturing method in this embodiment, in the step of thinning the oxide semiconductor layer 50A, the portion exposed from the protective layer 60 in the oxide semiconductor layer 50 is thinned by etching using the protective layer 60 as a mask. It has become.

  In this manner, by processing the oxide semiconductor layer 50A using the protective layer 60 as a mask, the portion exposed from the protective layer 60 can be thinned, so that the manufacturing cost can be reduced.

  Moreover, in the manufacturing method in this Embodiment, the protective layer 60 is comprised with the material which has organic substance as a main component.

  Thereby, even when the protective layer 60 is made of a material mainly composed of an organic substance and the protective layer 60 contains a lot of fixed charges, the amount of current flowing through the back channel path is effectively suppressed. be able to.

[Display device]
Next, an example in which the thin film transistor 1 according to the above embodiment is applied to a display device will be described with reference to FIGS. In this embodiment, an application example to an organic EL display device will be described.

  FIG. 4 is a partially cutaway perspective view of the organic EL display device according to the embodiment of the present invention. FIG. 5 is an electric circuit diagram of a pixel circuit in the organic EL display device shown in FIG. Note that the pixel circuit is not limited to the configuration shown in FIG.

  The above-described thin film transistor 1 can be used as a switching transistor and a driving transistor of an active matrix substrate in an organic EL display device.

  As shown in FIG. 4, the organic EL display device 100 includes a TFT substrate (TFT array substrate) 110 on which a plurality of thin film transistors are arranged, an anode 131 that is a lower electrode (reflection electrode), and an EL layer (light emitting layer) 132. And a laminated structure with an organic EL element (light emitting part) 130 composed of a cathode 133 which is an upper electrode (transparent electrode).

  The thin film transistor 1 described above is used for the TFT substrate 110 in the present embodiment. A plurality of pixels 120 are arranged in a matrix on the TFT substrate 110, and each pixel 120 is provided with a pixel circuit.

  The organic EL element 130 is formed corresponding to each of the plurality of pixels 120, and the light emission of each organic EL element 130 is controlled by a pixel circuit provided in each pixel 120. The organic EL element 130 is formed on an interlayer insulating layer (planarization film) formed so as to cover a plurality of thin film transistors.

  The organic EL element 130 has a configuration in which an EL layer 132 is disposed between the anode 131 and the cathode 133. A hole transport layer is further laminated between the anode 131 and the EL layer 132, and an electron transport layer is further laminated between the EL layer 132 and the cathode 133. Note that another functional layer may be provided between the anode 131 and the cathode 133. The functional layer formed between the anode 131 and the cathode 133 including the EL layer 132 is an organic layer made of an organic material.

  Each pixel 120 is driven and controlled by a respective pixel circuit. The TFT substrate 110 includes a plurality of gate wirings (scanning lines) 140 arranged along the row direction of the pixels 120 and a plurality of gate wirings 140 arranged along the column direction of the pixels 120 so as to intersect the gate wiring 140. Source wiring (signal wiring) 150 and a plurality of power supply wirings (not shown in FIG. 4) arranged in parallel with the source wiring 150 are formed. Each pixel 120 is partitioned by, for example, an orthogonal gate wiring 140 and a source wiring 150.

  The gate wiring 140 is connected to the gate electrode of the switching transistor included in each pixel circuit for each row. The source wiring 150 is connected to the source electrode of the switching transistor for each column. The power supply wiring is connected to the drain electrode of the drive transistor included in each pixel circuit for each column.

  As shown in FIG. 5, the pixel circuit includes a switching transistor SwTr, a drive transistor DrTr, and a capacitor C that stores data to be displayed on the corresponding pixel 120. In the present embodiment, the switching transistor SwTr is a TFT for selecting the pixel 120, and the drive transistor DrTr is a TFT for driving the organic EL element 130.

  The switching transistor SwTr includes a gate electrode G1 connected to the gate wiring 140, a source electrode S1 connected to the source wiring 150, a drain electrode D1 connected to the capacitor C and the gate electrode G2 of the second thin film transistor DrTr, and an oxidation A physical semiconductor layer (not shown). In the switching transistor SwTr, when a predetermined voltage is applied to the connected gate wiring 140 and source wiring 150, the voltage applied to the source wiring 150 is stored in the capacitor C as a data voltage.

  The drive transistor DrTr is connected to the drain electrode D1 of the switching transistor SwTr and the gate electrode G2 connected to the capacitor C, the drain electrode D2 connected to the power supply wiring 160 and the capacitor C, and the anode 131 of the organic EL element 130. A source electrode S2 and an oxide semiconductor layer (not shown) are provided. The drive transistor DrTr supplies a current corresponding to the data voltage held by the capacitor C from the power supply wiring 160 to the anode 131 of the organic EL element 130 through the source electrode S2. Thereby, in the organic EL element 130, a drive current flows from the anode 131 to the cathode 133, and the EL layer 132 emits light.

  Note that the organic EL display device 100 having the above configuration employs an active matrix system in which display control is performed for each pixel 120 located at the intersection of the gate wiring 140 and the source wiring 150. Thereby, the corresponding organic EL element 130 selectively emits light by the switching transistor SwTr and the drive transistor DrTr in each pixel 120, and a desired image is displayed.

  As described above, since the thin film transistor 1 having excellent on characteristics and off characteristics is used for the TFT substrate 110 in the present embodiment, an organic EL display device having excellent display performance can be realized.

(Other variations)
As described above, the thin film transistor and the manufacturing method thereof have been described based on the embodiment, but the present invention is not limited to the above embodiment.

For example, in the above embodiment, an amorphous oxide semiconductor of InGaZnO _x (IGZO) is used as the oxide semiconductor used for the oxide semiconductor layer, but the present invention is not limited to this, and a polycrystalline oxide semiconductor such as InGaO is used. Also good.

  Moreover, in the said embodiment, although the organic electroluminescent display apparatus was demonstrated as a display apparatus using a thin-film transistor, it is not restricted to this. For example, the thin film transistor in the above embodiment can also be applied to other display devices such as a liquid crystal display device.

  In this case, the organic EL display device (organic EL panel) can be used as a flat panel display. For example, the organic EL display device can be used as a display panel of any electronic device such as a television set, a personal computer, or a mobile phone.

  In addition, the form obtained by making various modifications conceived by those skilled in the art with respect to each embodiment and modification, and the components and functions in each embodiment and modification are arbitrarily set within the scope of the present invention. Forms realized by combining them are also included in the present invention.

  The thin film transistor according to the present invention can be widely used in various electric devices having a thin film transistor such as a display device (display panel) such as an organic EL display device, a television set, a personal computer, and a mobile phone using the display device. it can.

1, 1 ′ thin film transistor 10 substrate 20 undercoat layer 30 gate electrode 40 gate insulating layer 50, 50 ′ oxide semiconductor layer 51 first region 52 second region 52S, 52S ′ source region 52D, 52D ′ drain region 60 protective layer 70 Interlayer insulating layer 80S Source electrode 80D Drain electrode 100 Organic EL display device 110 TFT substrate 120 Pixel 130 Organic EL element 131 Anode 132 EL layer 133 Cathode 140 Gate wiring 150 Source wiring 160 Power supply wiring SwTr Switching transistor DrTr Drive transistor C Capacitor

Claims (10)

A substrate,
A gate electrode located above the substrate;
A gate insulating layer located above the gate electrode;
A semiconductor layer including a channel region facing the gate electrode across the gate insulating layer;
A protective layer located above the semiconductor layer;
A source electrode and a drain electrode electrically connected to the semiconductor layer,
The semiconductor layer is located below the protective layer and located above the gate electrode, and the resistance value of the upper region located on both sides of the first region is lower than the resistance value of the lower region. A low second region,
One of the second regions is electrically connected to the source electrode, and the other of the second region is electrically connected to the drain electrode;
The distance from the upper surface of the second region to the upper surface of the gate insulating layer is smaller than the distance from the upper surface of the first region to the upper surface of the gate insulating layer;
Thin film transistor. 2. The thin film transistor according to claim 1, wherein a contact point between an upper surface end portion of the second region and a side surface of the first region is located on a lower side than a position of ½ of the thickness of the first region. The thin film transistor according to claim 1 or 2, wherein a film thickness of the semiconductor layer in the second region is at least 15 nm or more. 4. The thin film transistor according to claim 1, wherein when viewed from above, an end of the upper surface of the first region overlaps an end of the lower surface of the protective layer. The thin film transistor according to claim 1, wherein the protective layer is made of a material mainly composed of an organic substance. Preparing a substrate;
Forming a gate electrode above the substrate;
Forming a gate insulating layer above the gate electrode;
Forming a semiconductor layer above the gate insulating layer so as to include at least a first region facing the gate electrode;
Forming a protective layer above the first region so that the semiconductor layers on both sides of the first region are exposed;
Thinning a portion of the semiconductor layer exposed from the protective layer;
Forming a second region on both sides of the first region by subjecting the thinned region to a process in which the resistance value of the upper region is lower than the resistance value of the lower region;
Forming a source electrode electrically connected to one of the second regions and a drain electrode electrically connected to the other of the second regions. In the step of thinning the semiconductor layer, the contact point between the upper end of the second region and the side surface of the first region is positioned below the position of ½ of the thickness of the first region. The method of manufacturing a thin film transistor according to claim 6, wherein the exposed portion of the semiconductor layer is thinned. 8. The exposed portion of the semiconductor layer is thinned so that the thickness of the semiconductor layer in the second region is at least 15 nm or more in the step of thinning the semiconductor layer. A method for manufacturing a thin film transistor. 9. The thin film transistor according to claim 6, wherein in the step of thinning the semiconductor layer, the exposed portion of the semiconductor layer is thinned by etching using the protective layer as a mask. Method. The method for manufacturing a thin film transistor according to any one of claims 6 to 9, wherein the protective layer is made of a material containing an organic substance as a main component.

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