JP6500203B2 - Thin film transistor and method of manufacturing thin film transistor - Google Patents

Description

  The present invention relates to a thin film transistor and a method of manufacturing the thin film transistor, and more particularly, to a thin film transistor using an oxide semiconductor and a method of manufacturing the same.

  Generally, an active matrix display such as a liquid crystal display device or an organic electro luminescence (EL) display device includes a plurality of thin film transistors (TFTs).

  In recent years, it has been proposed to use an oxide semiconductor as a material of a semiconductor layer (channel layer) of a thin film transistor. An oxide semiconductor is known to have excellent properties such as high mobility and film formation on a large-area substrate at low temperature. Therefore, development of an oxide semiconductor TFT using an oxide semiconductor for a channel layer is actively conducted. As an example of the oxide semiconductor, InGaZnO (Non-Patent Document 1), InSiO (Non-Patent Document 2), or the like can be given.

H. Omura, H. Kumomi, K. Nomura, T. Kamiya, M. Hirano and H. Hosono, J. Appl. Phys., 105, 93712 (2009) N. Mitoma, S. Aikawa, X. Gao, T. Kizu, M. Shimizu, M.-F. Lin, T. Nabatame and K. Tsukagozhi, Appl. Phys. Lett., 104, 102103 (2014)

  The TFT using InSiO as the oxide semiconductor is made by adding silicon (Si) having a large binding energy with oxygen into indium oxide (InO) to stabilize the characteristics, but the inventors added From the experiments, it has become clear that even in the TFT using InSiO, the resistance to hydrogen (hydrogen resistance) is comparable to that of the TFT using IGZO. Therefore, even in a TFT using InSiO, it is necessary to take measures to suppress the influence of hydrogen.

  The present invention has been made to solve such problems, and it is an object of the present invention to provide a thin film transistor having stable characteristics and high reliability, and a method of manufacturing the same.

  In order to achieve the above object, a thin film transistor according to one aspect of the present invention is provided between a gate electrode, an oxide semiconductor layer facing the gate electrode, and the gate electrode and the oxide semiconductor layer. And a gate insulating layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein the oxide semiconductor layer is formed of an oxide containing at least indium and silicon, and a first region And a second region which is a region closer to the gate insulating layer than the first region, wherein the first region has a silicon concentration higher than that of the second region.

  According to the present invention, since it has excellent hydrogen resistance while maintaining excellent TFT characteristics, it is possible to realize a thin film transistor having stable characteristics and high reliability.

It is sectional drawing which shows typically the structure of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the board | substrate preparatory process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the undercoat layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the gate electrode formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the gate insulating layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the oxide semiconductor layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the protective layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the contact hole formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the source-drain electrode formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is a figure which shows the current-voltage characteristic of TFT which used the InSiO film | membrane whose silicon concentration is 3.3 at% for a channel layer. It is a figure which shows the current-voltage characteristic of TFT which used the InSiO film | membrane whose silicon concentration is 5.5 at% for a channel layer. It is a figure which shows the current-voltage characteristic of TFT which used the InSiO film | membrane whose silicon concentration is 6.8 at% as a channel layer. It is a figure which shows the current-voltage characteristic of TFT which used the InSiO film | membrane whose silicon concentration is 8.6 at% for a channel layer. It is a figure which shows the current-voltage characteristic of TFT which used the InSiO film | membrane whose silicon concentration is 9.6 at% for a channel layer. It is a figure which shows the silicon concentration of an InSiO film | membrane, and carrier mobility (silicon concentration dependence). It is a figure which shows the relationship between the silicon concentration of InSiO film | membrane, and the sheet resistance of InSiO film | membrane. FIG. 5 is a diagram for describing a mechanism in which carriers are generated in an oxide semiconductor film by hydrogen. 13 is a diagram for describing a mechanism by which carriers contained in silicon in the oxide semiconductor film are not generated even if hydrogen intrudes into the oxide semiconductor film. It is a partially cutaway perspective view of the organic electroluminescence display which concerns on embodiment. FIG. 8 is an electric circuit diagram of a pixel circuit in the organic EL display device shown in FIG. 7. FIG. 6 is a cross-sectional view schematically showing a configuration of a thin film transistor according to Modification Example 1; FIG. 10 is a cross-sectional view schematically showing a configuration of a thin film transistor according to a modification 2; FIG. 13 is a cross-sectional view schematically showing a configuration of a thin film transistor according to Modification 3; FIG. 18 is a cross-sectional view schematically showing a configuration of a thin film transistor according to Modified Example 4;

<Outline of one embodiment of the present invention>
The details will be described later, but as a result of investigating the relationship between the silicon concentration of the InSiO film and the TFT characteristics or hydrogen resistance according to the additional experiments of the inventors, when the silicon concentration in InSiO is increased in the TFT using InSiO Although the decrease in current was observed, it was found that the resistance to hydrogen was improved.

  The thin film transistor according to one embodiment of the present invention utilizes such characteristics, and is provided between a gate electrode, an oxide semiconductor layer facing the gate electrode, and the gate electrode and the oxide semiconductor layer. A gate insulating layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein the oxide semiconductor layer is made of an oxide containing at least indium and silicon, There is one region and a second region which is a region closer to the gate insulating layer than the first region, and the first region has a silicon concentration higher than that of the second region.

  According to the above configuration, the region on the back channel side (the first region separated from the gate insulating layer) in the oxide semiconductor layer made of InSiO is closer to the region on the front channel side (the gate insulating layer) in the oxide semiconductor layer. Silicon concentration is higher than 2).

  Thus, hydrogen resistance in the region on the back channel side of the oxide semiconductor layer is improved, so that the influence of hydrogen from the back channel side can be suppressed.

  Furthermore, InSiO films with high silicon concentration have high sheet resistance. Therefore, the resistance value can be increased by increasing the silicon concentration in the region on the back channel side of the oxide semiconductor layer. As a result, the off leak current in the back channel can be reduced, and excellent off characteristics can be obtained.

  On the other hand, in the region on the front channel side of the oxide semiconductor layer, the silicon concentration is kept low as compared to the region on the back channel side, so that the excellent ON characteristics can be maintained without a decrease in ON current.

  As described above, in the oxide semiconductor layer made of InSiO, by maintaining the silicon concentration higher in the region on the back channel side than in the region on the front channel side, excellent hydrogen resistance is maintained while maintaining excellent TFT characteristics. As a result, it is possible to realize a TFT having high reliability, which is stable in particular.

  Further, in the thin film transistor according to one aspect of the present invention, the oxide semiconductor layer has a stacked structure including a first semiconductor layer formed as the first region and a second semiconductor layer formed as the second region. It is good.

  According to this configuration, hydrogen resistance can be secured by the first semiconductor layer having a relatively high silicon concentration. In addition, when the oxide semiconductor layer has a stacked structure, the second semiconductor layer and the first semiconductor layer can be formed by continuous film formation by sputtering or the like. This makes it possible to use silicon TFT manufacturing line equipment (existing equipment) for liquid crystal displays and the like, and to suppress manufacturing costs and manufacturing tact time.

  In the thin film transistor according to one aspect of the present invention, the silicon concentration of the first semiconductor layer is preferably 6.5 at% or more.

  Thereby, effective hydrogen resistance can be secured in the first semiconductor layer. Therefore, the entry of hydrogen from the back channel side can be effectively suppressed.

  In the thin film transistor according to one aspect of the present invention, the silicon concentration of the first semiconductor layer is preferably 11.7 at% or more.

  This dramatically improves the hydrogen tolerance in the first semiconductor layer. Therefore, the entry of hydrogen from the back channel side can be further suppressed.

  In the thin film transistor according to one aspect of the present invention, the silicon concentration of the second semiconductor layer is preferably less than 6.5 at%.

  As a result, the resistance value of the second semiconductor layer located on the front channel side can be reduced, so that the ON current can be easily maintained.

  In the thin film transistor according to one embodiment of the present invention, the silicon concentration of the oxide semiconductor layer is preferably higher than the hydrogen concentration contained in the oxide semiconductor layer.

  Thus, the influence of hydrogen can be further suppressed, so that a TFT having stable characteristics can be obtained.

  In the thin film transistor according to one aspect of the present invention, the thickness of the one semiconductor layer is preferably 5 nm or more.

  Thereby, the effect which can suppress the approach of hydrogen can be exhibited enough. Therefore, a TFT having stable characteristics can be obtained.

  In the thin film transistor according to one aspect of the present invention, the thickness of the second semiconductor layer is preferably 15 nm or more.

  As a result, since the second semiconductor layer with a small resistance value located on the front channel side can be sufficiently secured, the ON current can be more easily maintained.

  In the thin film transistor according to one embodiment of the present invention, the thickness of the oxide semiconductor layer is preferably 20 nm or more.

  As a result, a sufficient channel region can be secured, and a TFT having excellent characteristics can be realized. In addition, the processing (patterning) of the oxide semiconductor layer is sufficiently possible. Further, by setting the thickness of the oxide semiconductor layer to 20 nm or more, the thickness of the first semiconductor layer can be set to 20 nm or more. Therefore, even in the case where hydrogen diffuses due to the annealing process, The first semiconductor layer having a high silicon concentration can effectively block hydrogen from being mixed in the oxide semiconductor layer.

  Further, in the thin film transistor according to one embodiment of the present invention, the silicon concentration in the oxide semiconductor layer may be continuously increased as it approaches an interface opposite to the gate insulating layer side.

  Thus, the composition of the oxide semiconductor layer changes continuously, so that defects in the bulk of the oxide semiconductor layer can be suppressed. In addition, defects (interface states) in the interface on the opposite side to the gate insulating layer side in the oxide semiconductor layer can be reduced. Therefore, a TFT having more excellent characteristics can be obtained.

  In the thin film transistor according to one aspect of the present invention, the gate electrode, the gate insulating layer, and the oxide semiconductor layer are stacked in this order on a substrate, and the source electrode and the drain electrode are oxidized. It may be formed above the object semiconductor layer.

  With this configuration, the consistency with the silicon TFT manufacturing line equipment (existing equipment) is enhanced, and therefore the manufacturing cost can be suppressed.

  In the thin film transistor according to one embodiment of the present invention, a protective layer may be further provided over the oxide semiconductor layer.

  Accordingly, process damage in the region on the back channel side of the oxide semiconductor layer can be reduced. For example, the surface on the back channel side of the oxide semiconductor layer is not exposed in the etching step. Therefore, a TFT having uniform characteristics in the plane can be obtained.

  In the thin film transistor according to one aspect of the present invention, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in this order on a substrate, and the source electrode and the drain electrode are the gate. The oxide semiconductor layer may be connected to the oxide semiconductor layer through a contact hole formed in the insulating layer.

  With this configuration, the TFT size can be reduced, and high definition can be achieved.

  In the thin film transistor manufacturing method according to one aspect of the present invention, a step of forming a gate electrode, a step of forming an oxide semiconductor layer facing the gate electrode, a step of forming the gate electrode and the oxide semiconductor layer Between the step of forming a gate insulating layer and the step of forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, the oxide semiconductor layer containing at least indium and silicon oxide A first region and a second region which is a region closer to the gate insulating layer than the first region, and the first region has a silicon concentration higher than that of the second region.

  As a result, the influence of hydrogen from the back channel side can be suppressed, and a reduction in the ON current can be suppressed to maintain excellent TFT characteristics. Therefore, a TFT having stable characteristics can be manufactured with high yield.

Embodiment
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Each embodiment described below shows one specific example of the present invention. Therefore, the numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps (steps), order of steps, etc. shown in the following embodiments are merely examples, and the scope of the present invention is defined. is not. Therefore, among the components in the following embodiments, components that are not described in the independent claims indicating the highest concept of the present invention are described as optional components.

  Each drawing is a schematic view and is not necessarily strictly illustrated. Further, in the drawings, substantially the same components are denoted by the same reference numerals, and overlapping descriptions will be omitted or simplified.

(Structure of thin film transistor)
First, the thin film transistor 1 according to the embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing the configuration of the thin film transistor according to the embodiment. FIG. 1 shows a TFT array substrate, and two thin film transistors 1 are shown in FIG.

  As shown in FIG. 1, the thin film transistor 1 is a bottom gate oxide semiconductor TFT in which an oxide semiconductor layer is used as a channel layer. Further, the thin film transistor 1 in the present embodiment is a channel protection type, and a top contact structure is adopted.

  The thin film transistor 1 includes a substrate 10, an undercoat layer 20, a gate electrode 30, a gate insulating layer 40, an oxide semiconductor layer 50, a protective layer 60, and a source electrode 70S and a drain electrode 70D.

  Hereinafter, each component of the thin film transistor 1 according to the present embodiment will be described in detail.

  The substrate 10 is, for example, a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistance glass. The substrate 10 is not limited to the glass substrate, and, for example, polyimide, polyamide, polyamide imide, polyester, polycarbonate, polymethyl methacrylate, polyurea, polyacetal, polyether ketone, polyether ether ketone, polyether imide, poly arylate, etc. It may be a plastic substrate (resin substrate) made of a plastic material or the like.

  The substrate 10 may not be a rigid substrate, but may be a flexible substrate (film substrate) having flexibility. Alternatively, a glass substrate may be used as a supporting substrate, and a plastic material such as polyimide may be formed thereon.

  The undercoat layer 20 is formed on the substrate 10. By forming the undercoat layer 20, impurities such as sodium and phosphorus contained in the substrate 10 (glass substrate) or moisture and the like transmitted from the air are prevented from entering the oxide semiconductor layer 50. be able to. The undercoat layer 20 also plays a role of alleviating the influence of heat on the substrate 10 in a high temperature heat treatment process such as laser annealing.

The undercoat layer 20 is a single layer insulating layer or a laminated insulating layer using an oxide insulating layer or a nitride insulating layer. As an example, the undercoat layer 20 may be a single layer film of silicon nitride (SiN _x ), silicon oxide (SiO _y ), silicon oxynitride (SiO _y N _x ), aluminum oxide (AlO _x ) or the like, or A laminated film can be used. The film thickness of the undercoat layer 20 is, for example, about 100 nm to 2000 nm. The undercoat layer 20 need not necessarily be formed.

  The gate electrode 30 is located above the substrate 10, and is formed, for example, above the substrate 10. In the present embodiment, the gate electrode 30 is patterned on the undercoat layer 20 in a predetermined shape. The gate electrode 30 is made of a conductive material, and has a single layer structure or a multilayer structure. As the conductive material, for example, a metal or an alloy can be used. As the metal or alloy, for example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), niobium (Nb), nickel (Ni), titanium (Ti), chromium ( Cr) or molybdenum tungsten (MoW) or the like can be used. The film thickness of the gate electrode 2 is, for example, about 20 nm to 500 nm.

  The gate insulating layer 40 is disposed between the gate electrode 30 and the oxide semiconductor layer 50. In the present embodiment, the gate insulating layer 40 is formed at least above the gate electrode 30. Specifically, the gate insulating layer 40 is formed on the entire surface of the undercoat layer 20 so as to cover the gate electrode 30.

The gate insulating layer 40 is made of an electrically insulating material, and has a single layer structure or a multilayer structure. As the electrically insulating material, for example, silicon oxide (SiO _y ), silicon nitride (SiN _x ), silicon oxynitride (SiO _y N _x ), aluminum oxide (AlO _z ), tantalum oxide (TaO _w ) may be used. it can. In the present embodiment, the gate insulating layer 40 is, for example, a laminated film of a silicon oxide film and a silicon nitride film. The film thickness of the gate insulating layer 40 can be designed in consideration of the withstand voltage of the TFT and the like, and is, for example, about 50 nm to 500 nm.

  The oxide semiconductor layer 50 is formed on the gate insulating layer 40 in a predetermined shape. The oxide semiconductor layer 50 is used as a channel layer and faces the gate electrode. That is, the oxide semiconductor layer 50 is a semiconductor layer including a region (channel region) opposed to the gate electrode 30 with the gate insulating layer 40 interposed therebetween.

  For example, a transparent amorphous oxide semiconductor (TAOS) is used as a material of the oxide semiconductor layer 50. Specifically, it is composed of an oxide containing at least indium (In) and silicon (Si). In the present embodiment, the oxide semiconductor layer 50 contains indium (In), silicon (Si) and oxygen (O), and is made of InSiO (ISO). The transparent amorphous oxide semiconductor not only has the property of high mobility, but is also useful when utilizing a plastic material as the material of the substrate 10 because low temperature film formation is possible.

  The oxide semiconductor layer 50 has a first region and a second region which is a region closer to the gate insulating layer 40 than the first region, and the first region has a silicon concentration higher than that of the second region. There is. That is, in the oxide semiconductor layer 50, the silicon concentration is higher in the region on the side opposite to the gate insulating layer 40 side (the protective layer 60 side) than in the region on the gate insulating layer 40 side. Specifically, the region (first region) in the oxide semiconductor layer 50 which is separated from the gate insulating layer 40 has a higher silicon concentration than the region (second region) in the oxide semiconductor layer 50 closer to the gate insulating layer 40. It has become.

  In this embodiment, the oxide semiconductor layer 50 has a stacked structure, and for example, the first semiconductor layer 51 formed as a first region far from the gate insulating layer 40 in the oxide semiconductor layer 50, and an oxide This is a two-layered structure with the second semiconductor layer 52 formed as a second region closer to the gate insulating layer 40 in the semiconductor layer 50. Specifically, the oxide semiconductor layer 50 includes the second semiconductor layer 52 and the first semiconductor layer 51 formed on the second semiconductor layer 52.

  The first semiconductor layer 51 is a high silicon concentration layer having a silicon concentration (Si concentration) higher than that of the second semiconductor layer 52. The first semiconductor layer 51 is a layer on the protective layer 60 side (relatively far from the gate insulating layer 40) in the oxide semiconductor layer 50, and in the present embodiment, the upper layer (upper part of the oxide semiconductor layer 50). Area).

  On the other hand, the second semiconductor layer 52 is a low silicon concentration layer having a silicon concentration (Si concentration) lower than that of the first semiconductor layer 51. The second semiconductor layer 52 is a layer on the gate insulating layer 40 side (relatively close to the gate insulating layer 40) in the oxide semiconductor layer 50, and in the present embodiment, the lower layer of the oxide semiconductor layer 50 Lower region).

  Thus, in the oxide semiconductor layer 50, the silicon concentration of the first semiconductor layer 51 is higher than the silicon concentration of the second semiconductor layer 52. Although the details will be described later, excellent hydrogen resistance can be realized in the upper first semiconductor layer 51 by using the first semiconductor layer 51 having a high silicon concentration. Thereby, the influence of hydrogen from the back channel side (the protective layer 60 side) can be suppressed. Furthermore, since the InSiO film having a high silicon concentration has a high sheet resistance, the off leak current in the back channel can also be reduced.

  The silicon concentration of the first semiconductor layer 51 may be 6.5 at% or more, preferably 11.7 at% or more. As a result, the resistance to hydrogen in the first semiconductor layer 51 is dramatically improved, so that the influence of hydrogen from the back channel side can be further suppressed.

  Further, the silicon concentration of the second semiconductor layer 52 may be less than 6.5 at%. Thus, the resistance value of the second semiconductor layer 52 located on the front channel side can be reduced, and the ON current can be easily maintained.

  As an example, the silicon concentration of the first semiconductor layer 51 is 11.7 at%, and the silicon concentration of the second semiconductor layer 52 is 6.5 at%, but it is not limited thereto.

  The first semiconductor layer 51 and the second semiconductor layer 52 are made of the same element, and both are made of InSiO (InSiO film). In the first semiconductor layer 51 and the second semiconductor layer 52, silicon is mixed in a chemically bonded state.

  The film thickness of the first semiconductor layer 51 may be 5 nm or more. Thus, the first semiconductor layer 51 can sufficiently exhibit hydrogen resistance in the oxide semiconductor layer 50. Therefore, the entry of hydrogen can be effectively suppressed.

  The film thickness of the second semiconductor layer 52 may be 15 nm or more. As a result, since the second semiconductor layer 52 with a small resistance value located on the front channel side can be sufficiently secured, the ON current can be more easily maintained.

  The total film thickness of the oxide semiconductor layer 50 may be 20 nm or more. As a result, a sufficient channel region can be secured, and a TFT having excellent characteristics can be realized. In addition, by setting the film thickness of the oxide semiconductor layer 50 to 20 nm or more, the processing process of the oxide semiconductor layer 50 can be sufficiently performed. That is, film formation by sputtering or the like of the oxide semiconductor layer 50 and patterning by photolithography and etching can be easily performed.

  Furthermore, by setting the film thickness of the first semiconductor layer 51 to 20 nm or more, even if hydrogen diffuses due to annealing or the like, the first semiconductor layer 51 having a high silicon concentration causes hydrogen to be added to the oxide semiconductor layer 50. Can be effectively blocked. For example, damage due to hydrogen diffused from the protective layer 60 side can be suppressed.

  Further, the silicon concentration in the entire oxide semiconductor layer 50 is preferably higher than the hydrogen concentration contained in at least the entire oxide semiconductor layer 50. Thereby, the influence of hydrogen can be further suppressed.

  The protective layer 60 is formed on the oxide semiconductor layer 50. The protective layer 60 is a channel etching stopper (CES) that protects the channel region to prevent the channel region of the oxide semiconductor layer 50 from being etched in the etching process for forming the source electrode 70S and the drain electrode 70D. Functions as a layer). Accordingly, in the bottom gate TFT, process damage on the back channel side of the oxide semiconductor layer 50 can be reduced. Moreover, in the present embodiment, the protective layer 60 is an interlayer insulating layer formed on the entire surface of the substrate 10.

  The protective layer 60 is made of an insulating material having an insulating property. As a material of the protective layer 60, for example, a material containing an oxide or an oxynitride as a main component can be used. As a material containing an oxide or an oxynitride as a main component, for example, an inorganic substance such as silicon oxide, silicon oxynitride, aluminum oxide, or yttrium oxide can be used. Silicon oxide has a lower hydrogen content than silicon nitride. Therefore, by using silicon oxide as the protective layer 60, deterioration in characteristics of the oxide semiconductor layer 50 due to hydrogen can be suppressed. The protective layer 60 may have a single-layer structure or a laminated structure. In the case of a stacked structure, aluminum oxide has a function of blocking hydrogen and oxygen, and thus, for example, a three-layer stacked structure of silicon oxide, aluminum oxide, and silicon oxide is preferable.

  The material of the protective layer 60 is not limited to the inorganic material, and may be a material containing an organic matter as a main component.

  In addition, an opening (contact hole) is formed in the protective layer 60 so as to penetrate a part of the protective layer 60. The oxide semiconductor layer 50 is connected to the source electrode 70S and the drain electrode 70D through the opening of the protective layer 60.

  The source electrode 70S and the drain electrode 70D are formed on the protective layer 60 in a predetermined shape. The source electrode 70S and the drain electrode 70D are arranged to face each other in the horizontal direction of the substrate at an interval, and are electrically connected to the oxide semiconductor layer 50 through the openings formed in the protective layer 60, respectively. .

  The source electrode 70S and the drain electrode 70D are each made of a conductive material, and have a single layer structure or a multilayer structure. As the conductive material, for example, a metal or an alloy can be used. As the metal or alloy, for example, aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), titanium (Ti), chromium (Cr), molybdenum tungsten (MoW) or the like can be used. . In the present embodiment, the source electrode 70S and the drain electrode 70D are formed by a three-layer structure of MoW / Al / MoW. The film thickness of the source electrode 70S and the drain electrode 70D can be, for example, about 100 nm to 500 nm.

  Further, the arrangement position of the source electrode 70S and the drain electrode 70D is not limited to the position shown in FIG. 1, and it is a position at which the oxide semiconductor layer 50 is electrically connected to the source electrode 70S and the drain electrode 70D. Good.

  Although not shown, a passivation layer may be formed in a protective layer 60 so as to cover the source electrode 70S and the drain electrode 70D. The film thickness of the passivation layer 9 can be, for example, 20 nm or more and 1000 nm or less. The passivation layer 9 is, for example, an insulating film made of an inorganic material such as silicon oxide or silicon nitride, and can be formed, for example, by plasma CVD (Chemical Vapor Deposition) or the like.

(Method of manufacturing thin film transistor)
Next, a method of manufacturing the thin film transistor 1 according to the embodiment will be described with reference to FIGS. 2A to 2H. 2A to 2H are cross-sectional views schematically showing configurations of respective steps in the method of manufacturing the thin film transistor according to the embodiment.

  In the method of manufacturing the thin film transistor 1 according to the present embodiment, a substrate preparing step of preparing the substrate 10, an undercoat layer forming step of forming the undercoat layer 20, a gate electrode forming step of forming the gate electrode 30, and a gate A gate insulating layer forming step of forming the insulating layer 40, an oxide semiconductor layer forming step of forming the oxide semiconductor layer 50 including the first semiconductor layer 51 and the second semiconductor layer 52, and a protection of forming the protective layer 60 A layer forming step, a contact hole forming step of forming a contact hole in the protective layer 60, and a source / drain electrode forming step of forming the source electrode 70S and the drain electrode 70D are included. After that, if necessary, a passivation layer forming step of forming a passivation layer may be included.

  Hereafter, each process of the manufacturing method of the thin-film transistor 1 in this Embodiment is demonstrated in detail.

  First, as shown in FIG. 2A, the substrate 10 is prepared. For example, a glass substrate is prepared as the substrate 10.

  Next, as shown in FIG. 2B, the undercoat layer 20 is formed on the substrate 10. An undercoat layer 20 composed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film or the like is formed on the substrate 10 by plasma CVD or the like.

  Next, as shown in FIG. 2C, a gate electrode 30 having a predetermined shape is formed above the substrate 10. In the present embodiment, after forming a metal film (gate metal film) on the undercoat layer 20 by sputtering, the metal film is processed using a photolithography method and a wet etching method to be patterned into a predetermined shape. The gate electrode 30 was formed.

Next, as shown in FIG. 2D, a gate insulating layer 40 is formed to cover the gate electrode 30. As a method of forming the gate insulating layer 40, for example, plasma CVD can be used. As an example, when forming a silicon nitride film as the gate insulating layer 40 by plasma CVD, the silicon nitride film can be formed by using silane gas (SiH ₄ ), ammonia gas (NH ₃ ) and nitrogen gas (N ₂ ) as the introduced gas. Can be deposited.

  Next, as illustrated in FIG. 2E, an oxide semiconductor layer 50 having a predetermined shape is formed above the gate insulating layer 40 so as to face at least the gate electrode 30. In this embodiment, the oxide semiconductor layer 50 including the first semiconductor layer 51 and the second semiconductor layer 52 is formed in an island shape on the gate insulating layer 40.

  Specifically, an InSiO film having a low silicon concentration is formed on the gate insulating layer 40, and then an InSiO film having a high silicon concentration is formed, and thereafter, an oxide semiconductor layer 50 having a predetermined shape is formed. A stacked film of a low silicon concentration InSiO film and a high silicon concentration InSiO film is processed.

As a film formation method of the InSiO film, for example, a sputtering method can be used. For example, using a target material containing indium, silicon and oxygen, argon (Ar) gas is flowed into the vacuum chamber as an inert gas and a gas containing oxygen (O ₂ ) is flowed as a reactive gas. An InSiO film can be formed by applying a power density voltage to the target material. In this case, as a method of forming InSiO films (InSiO films having different Si concentrations) having different compositions, for example, films are sequentially formed in the same chamber using targets made of InSiO having different compositions (InSiO having different Si concentrations). Alternatively, it is conceivable to control the composition by simultaneously performing sputtering film formation by changing the power ratio applied to each target using In ₂ O ₃ and SiO ₂ targets.

  Further, as a method of processing a stacked film, for example, a photolithography method and an etching method can be used. Specifically, first, a resist having a predetermined shape is formed on a laminated film of InSiO films different in composition, and the laminated film in a region where the resist is not formed is removed by wet etching to form the second semiconductor layer 52 An island-shaped oxide semiconductor layer 50 including the first semiconductor layer 51 can be formed.

  Next, as shown in FIG. 2F, a protective layer 60 is formed to cover the oxide semiconductor layer 50. The protective layer 60 is made of, for example, a material containing an oxide or an oxynitride as a main component, and can be formed using a plasma CVD method. When aluminum oxide or yttrium oxide is formed as the protective layer 60, the protective layer 60 may be formed by sputtering.

  Thereafter, by performing heat treatment (annealing treatment) as necessary, oxygen defects present in the oxide semiconductor layer 50 can be complemented, and TFT characteristics can be stabilized. For example, heat treatment may be performed at a temperature of 300 ° C. to 350 ° C. for one hour in the air (in an oxygen atmosphere).

  As a method of heat treatment, for example, a hot plate, a furnace, laser irradiation or infrared irradiation can be used. In addition, the above heat treatment serves also as stabilization treatment of the oxide semiconductor layer by applying energy. The method of the stabilization treatment is not limited to the heat treatment, and the same effect can be obtained by, for example, ultraviolet irradiation or X-ray irradiation. Note that heat treatment for complementing oxygen defects in the oxide semiconductor layer 50 (step for stabilizing the oxide semiconductor layer 50) is performed after the source electrode 70S and the drain electrode 70D are formed, or after the passivation layer is formed. It may be done after forming.

Next, as shown in FIG. 2G, a contact hole CH (opening) is formed in the protective layer 60 so as to expose a part of the oxide semiconductor layer 50. Specifically, an opening is formed over a connection portion of the oxide semiconductor layer 50 with the source electrode 70S and the drain electrode 70D by etching away part of the protective layer 60 by a photolithography method and an etching method. For example, when the protective layer 60 is a silicon oxide film, the contact holes CH can be formed in the silicon oxide film by a dry etching method by a reactive ion etching (RIE) method. In this case, for example, carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ) can be used as the etching gas.

  Next, as shown in FIG. 2H, the source electrode 70S and the drain electrode 70D connected to the oxide semiconductor layer 50 through the contact holes CH formed in the protective layer 60 are formed. In the present embodiment, for example, a metal film (source / drain metal film) is formed on the protective layer 60 so as to fill the contact holes CH formed in the protective layer 60, and then metal is formed by photolithography and wet etching. By processing the film, the source electrode 70S and the drain electrode 70D patterned in a predetermined shape were formed. During the wet etching, the protective layer 60 functions as an etching protective layer.

  Although not shown, a passivation layer may be formed to cover the whole. For example, a passivation layer made of silicon nitride, silicon oxide, or the like may be formed on the protective layer 60, the source electrode 70S, and the drain electrode 70D by plasma CVD or the like.

(Action effect)
Next, the operation and effect of the thin film transistor 1 according to the present embodiment will be described, including the background to one aspect of the present invention.

  A TFT using InGaZnO (IGZO), which is a typical oxide semiconductor, is susceptible to hydrogen, and has the problem that the TFT characteristics fluctuate during the process of manufacturing the TFT or during driving after manufacturing the TFT. is there.

  On the other hand, in a TFT using InSiO as an oxide semiconductor, silicon (Si) having a large binding energy to oxygen is added to indium oxide to stabilize the characteristics.

  The inventors conducted additional experiments on the relationship between the silicon concentration of the InSiO film and the TFT characteristics, and the relationship between the silicon concentration of the InSiO film and hydrogen resistance, in order to realize the TFT using InSiO.

  Specifically, the inventors first made five types of InSiO films (silicon single crystals having different compositions of 3.3 at%, 5.5 at%, 6.8 at%, 8.6 at%, and 9.6 at%). A TFT having a layer film as a channel layer was produced, and the TFT characteristics were evaluated. The results are shown in FIGS. 3A to 3E and FIG. 3A to 3E are diagrams showing the relationship between the silicon concentration of the InSiO film and the current-voltage characteristic of the TFT (depending on the silicon concentration). FIG. 4 is a diagram showing the relationship between the silicon concentration of the InSiO film and the carrier mobility (depending on the silicon concentration).

  As shown in FIGS. 3A to 3E, it was found that the ON current decreased as the silicon concentration in the InSiO film increased. Further, as shown in FIGS. 3A to 3E, it is also understood that the on / off ratio is high when the silicon concentration in the InSiO film is low, but the on / off ratio decreases as the silicon concentration in the InSiO film increases.

Further, as shown in FIG. 4, it was found that the carrier mobility also decreased as the silicon concentration in the InSiO film increased. In particular, it can be seen that in TFTs having a silicon concentration of 5.5 at% or less, the carrier mobility exhibits excellent performance of 17 cm ² / Vs or more, and performance substantially equivalent to the TFT characteristics shown in Non-Patent Document 2 Was able to reproduce.

  Furthermore, the present inventors used as the oxide semiconductor film a glass substrate with four types of InSiO films (30 nm) having different compositions of silicon at 0.1 at%, 3.3 at%, 6.5 at%, and 11.7%. A film is formed on a 6-inch wafer, and a silicon nitride film (SiN: H) containing hydrogen is formed on these InSiO films via a silicon oxide film (SiO film), and the resistance to hydrogen is evaluated did. The results are shown in FIG.

  FIG. 5 is a diagram showing the relationship between the silicon concentration of the InSiO film and the sheet resistance of the InSiO film (depending on the silicon concentration), and shows the relationship between the silicon concentration of the InSiO film and the hydrogen resistance. That is, FIG. 5 shows the sheet resistance of the InSiO film after resistance reduction due to the influence of hydrogen of the silicon nitride film. Note that FIG. 5 also illustrates a case where an IGZO film is used as the oxide semiconductor layer for comparison. Further, the sheet resistance of each InSiO film in FIG. 5 is an average value of sheet resistances of nine points on the wafer.

  As shown in FIG. 5, it was found that the sheet resistance of the InSiO films having a silicon concentration of 0.1 at% and 3.3 at% decreased to about 1 kΩ after forming the silicon nitride film. In addition, it was found that the InSiO film having a silicon concentration of 3.3 at% receives the same level of hydrogen damage as the IGZO film.

  On the other hand, it has been found that when the silicon concentration in the InSiO film is 6.5 at% or more, the sheet resistance decreases only to about 2 kΩ after forming the silicon nitride film, and the reduction in the sheet resistance is suppressed to improve the hydrogen resistance. The

  Furthermore, it was found that when the silicon concentration is 11.7 at% or more, the sheet resistance decreases only to about 26 kΩ even after the silicon nitride film formation, the reduction in the sheet resistance is remarkably suppressed, and the hydrogen resistance is dramatically improved. .

  Here, the influence of hydrogen and the action of improving the hydrogen resistance by silicon in the oxide semiconductor film are described with reference to FIGS. 6A and 6B. FIG. 6A is a diagram for describing a mechanism in which carriers are generated in the oxide semiconductor film by hydrogen, and FIG. 6B is a diagram illustrating carriers contained in silicon in the oxide semiconductor film even if hydrogen intrudes into the oxide semiconductor film. It is a figure for demonstrating the mechanism which does not occur.

  As illustrated in FIG. 6A, when hydrogen diffuses and penetrates into the oxide semiconductor film, the hydrogen acts as a donor in the oxide semiconductor film. That is, intruding hydrogen bonds (Metal-O-H (i)) to a metal in a state where oxygen and an oxide semiconductor film are bonded to each other, and electrons are released from hydrogen. As a result, the sheet resistance of the oxide semiconductor film is considered to be reduced.

  On the other hand, the improvement in hydrogen resistance of the InSiO film having a high silicon concentration is due to the fact that hydrogen is contained in the oxide semiconductor film, as shown in FIG. 6B, the hydrogen termination site changes from oxygen to silicon (Metal It is guessed that it is because -O-Si-H). Here, in general, Si-H bonds are known to be electrically inactive. For this reason, in the InSiO film containing silicon, since silicon will capture hydrogen, carriers are not released from hydrogen. As a result, it is presumed that the sheet resistance of the oxide semiconductor film does not decrease.

  From such a mechanism, in FIG. 5, when the silicon concentration in the InSiO film is 0.1 at% and 3.3 at%, the sheet resistance is greatly reduced because the amount of hydrogen diffused from silicon nitride is in the InSiO film It is believed that the amount of silicon present in the

  On the other hand, when the silicon concentration in the InSiO film is 6.5 at%, the reduction in sheet resistance is suppressed because the silicon present in the InSiO film is present in large amounts. In particular, at 11.7 at%, the decrease in sheet resistance is dramatically suppressed because the amount of silicon present in the InSiO film is sufficient relative to the amount of hydrogen diffused from silicon nitride. It is believed that there is.

  As a result of the above-mentioned additional experiments, the inventors have found that, in the TFT using InSiO, as the silicon concentration of the InSiO film increases, the ON current decreases while the hydrogen resistance improves. In particular, it has been found that the hydrogen resistance is dramatically improved when the silicon concentration in the InSiO film is 11.7 at% or more.

  Therefore, in the thin film transistor 1 according to the present embodiment, the oxide semiconductor layer 50 is made of InSiO, and the silicon concentration of the oxide semiconductor layer 50 is the gate of the region (first region) separated from the gate insulating layer 40. It is made to be higher than the region (second region) near the insulating layer 40.

  Thus, the hydrogen resistance in the region (first semiconductor layer 51) on the back channel side of the oxide semiconductor layer 50 is improved, so hydrogen entering the oxide semiconductor layer 50 from the back channel side (the protective layer 60 side) Can reduce the influence of For example, damage due to hydrogen diffused from the protective layer 60 side can be suppressed.

  Further, by increasing the concentration of silicon in the region (first semiconductor layer 51) on the back channel side of the oxide semiconductor layer 50, the resistivity in the region on the back channel side of the oxide semiconductor layer 50 can be increased. As a result, the off leak current in the back channel can be reduced, and excellent off characteristics can be obtained.

  On the other hand, in the region on the front channel side of the oxide semiconductor layer 50 (the second semiconductor layer 52), the silicon concentration is maintained lower than the region on the back channel side. Therefore, since the ON current does not decrease, excellent ON characteristics can be maintained.

  As described above, in the oxide semiconductor layer 50 made of InSiO, by making the region on the back channel side higher in silicon concentration than the region on the front channel side, excellent hydrogen resistance is maintained while maintaining excellent TFT characteristics. Since it can be ensured, it becomes possible to realize a TFT with stable characteristics and high reliability, and it is possible to obtain the TFT with a high yield.

  In the thin film transistor 1 according to the present embodiment, the insulating layer in contact with the oxide semiconductor layer 50 (the first semiconductor layer 51) may be a silicon compound such as a silicon oxide film (SiO).

  Thus, lattice matching between the oxide semiconductor layer 50 and the insulating layer is increased, so that the interface state between the oxide semiconductor layer 50 and the insulating layer can be improved. Therefore, a highly reliable thin film transistor having high robustness can be realized.

<Display device>
Next, an example in which the thin film transistor 1 according to the above embodiment is applied to a display device will be described with reference to FIGS. 7 and 8. FIG. In the present embodiment, an application example to an organic EL display device will be described.

  FIG. 7 is a partially cutaway perspective view of the organic EL display device according to the embodiment. 8 is an electric circuit diagram of the pixel circuit in the organic EL display device shown in FIG. The pixel circuit is not limited to the configuration shown in FIG.

  The thin film transistor 1 described above can be used as the switching transistor SwTr and the driving transistor DrTr of the active matrix substrate in the organic EL display device.

  As shown in FIG. 7, the organic EL display device 100 includes a TFT substrate (TFT array substrate) 110 in which a plurality of thin film transistors are arranged, an anode 131 which is a lower electrode (reflection electrode), and an EL layer (light emitting layer) 132. And it is comprised by the laminated structure with the organic EL element (light emission part) 130 which consists of the cathode 133 which is upper electrode (transparent electrode).

  The thin film transistor 1 described above is used for the TFT substrate 110 in the present embodiment. A plurality of pixels 120 are arranged in a matrix on the TFT substrate 110, and each pixel 120 is provided with a pixel circuit.

  The organic EL element 130 is formed corresponding to each of the plurality of pixels 120, and the light emission control of each organic EL element 130 is performed by the pixel circuit provided in each pixel 120. The organic EL element 130 is formed on an interlayer insulating layer (planarizing film) formed to cover a plurality of thin film transistors.

  In addition, the organic EL element 130 has a configuration in which the EL layer 132 is disposed between the anode 131 and the cathode 133. A hole transport layer is further stacked between the anode 131 and the EL layer 132, and an electron transport layer is further stacked between the EL layer 132 and the cathode 133. Another functional layer may be provided between the anode 131 and the cathode 133. The functional layer formed between the anode 131 and the cathode 133 including the EL layer 132 is an organic layer made of an organic material.

  Each pixel 120 is driven and controlled by the respective pixel circuit. Further, on the TFT substrate 110, a plurality of gate wirings (scanning lines) 140 arranged along the row direction of the pixels 120 and a plurality of pixels arranged along the column direction of the pixels 120 so as to intersect the gate wirings 140. Source wiring (signal wiring) 150 and a plurality of power supply wirings (not shown in FIG. 7) arranged in parallel with the source wiring 150 are formed. Each pixel 120 is partitioned by, for example, orthogonal gate wiring 140 and source wiring 150.

  The gate wiring 140 is connected to the gate electrode of the switching transistor included in each pixel circuit and for each row. The source wiring 150 is connected to the source electrode of the switching transistor and for each column. The power supply wiring is connected to the drain electrode of the drive transistor included in each pixel circuit for each column.

  As shown in FIG. 8, the pixel circuit is configured of a switching transistor SwTr, a driving transistor DrTr, and a capacitor C that stores data to be displayed on the corresponding pixel 120. In the present embodiment, the switching transistor SwTr is a TFT for selecting the pixel 120, and the driving transistor DrTr is a TFT for driving the organic EL element 130.

  The switching transistor SwTr includes a gate electrode G1 connected to the gate wiring 140, a source electrode S1 connected to the source wiring 150, a drain electrode D1 connected to the capacitor C and the gate electrode G2 of the second thin film transistor DrTr, and oxidation. And an object semiconductor layer (not shown). In the switching transistor SwTr, when a predetermined voltage is applied to the connected gate line 140 and source line 150, the voltage applied to the source line 150 is stored in the capacitor C as a data voltage.

  The driving transistor DrTr is connected to the gate electrode G2 connected to the drain electrode D1 of the switching transistor SwTr and the capacitor C, the drain electrode D2 connected to the power supply wiring 160 and the capacitor C, and the anode 131 of the organic EL element 130. A source electrode S2 and an oxide semiconductor layer (not shown) are provided. The driving transistor DrTr supplies a current corresponding to the data voltage held by the capacitor C from the power supply wiring 160 to the anode 131 of the organic EL element 130 through the source electrode S2. Thereby, in the organic EL element 130, a drive current flows from the anode 131 to the cathode 133, and the EL layer 132 emits light.

  In the organic EL display device 100 configured as described above, an active matrix method is employed in which display control is performed for each pixel 120 located at the intersection of the gate wiring 140 and the source wiring 150. As a result, the corresponding organic EL element 130 selectively emits light by the switching transistor SwTr and the driving transistor DrTr in each pixel 120, and a desired image is displayed.

  As described above, in the organic EL display device 100 according to the present embodiment, since the thin film transistor 1 having stable characteristics and high reliability is used as the switching transistor SwTr and the driving transistor DrTr, an organic EL display device excellent in reliability is realized. it can.

<Modification>
Although the thin film transistor according to the present invention has been described above based on the embodiment, the present invention is not limited to the above embodiment.

  For example, although the oxide semiconductor layer 50 has a two-layer structure of the second semiconductor layer 52 and the first semiconductor layer 51 in the above embodiment, the present invention is not limited to this, and as shown in FIG. , And may have a three-layer structure. In this case, the third semiconductor layer 53 having a silicon concentration higher than that of the second semiconductor layer 52 can be formed under the second semiconductor layer 52 having a low silicon concentration. Thus, the influence of hydrogen from the gate insulating layer 40 side can be suppressed by the third semiconductor layer 53 having a high silicon concentration.

  In addition, the oxide semiconductor layer 50 may not have a stacked structure clearly divided into a plurality of layers, and may have a concentration gradient of silicon in the thickness direction. In this case, for example, the silicon concentration in the oxide semiconductor layer 50 is continuously increased as it approaches the interface (the interface between the oxide semiconductor layer 50 and the protective layer 60) opposite to the gate insulating layer 40 side. It can be configured. Thus, defects at the interface between the oxide semiconductor layer 50 and the protective layer 60 can be reduced, so that a TFT with more excellent characteristics can be realized.

  Further, in the above embodiment, the bottom gate thin film transistor is described in which the gate electrode 30, the gate insulating layer 40, and the oxide semiconductor layer 50 are stacked on the substrate 10 in this order from the bottom to the top. Absent. For example, as illustrated in FIG. 10, a top gate thin film transistor may be employed in which the oxide semiconductor layer 50, the gate insulating layer 40, and the gate electrode 30 are stacked on the substrate 10 in this order from bottom to top. In this case, the source electrode 70S is connected to the source region (resistance reduction region) of the oxide semiconductor layer 50 through the contact hole formed in the gate insulating layer 40. Further, the drain electrode 70D is connected to the drain region (resistance reduction region) of the oxide semiconductor layer 50 through the contact hole formed in the gate insulating layer 40. As described above, by using top gate thin film transistors, the size of the TFT can be reduced, and high definition can be achieved.

  Further, although the channel protective thin film transistor is used in the above embodiment, as shown in FIG. 11, the present invention may be applied to a channel etch thin film transistor. Alternatively, as shown in FIG. 12, the present invention may be applied to a low capacitance bottom gate thin film transistor with reduced parasitic capacitance. In the thin film transistor in FIG. 12, the insulating layer 80 is formed to cover the protective layer 60 and the oxide semiconductor layer 50, and the source electrode 70S and the drain electrode 70D are oxidized through the contact holes formed in the insulating layer 80. It is connected to the object semiconductor layer 50.

  In FIGS. 9, 10, 11, and 12, the undercoat layer 20 may be formed on the substrate 10, or a passivation layer may be formed to cover the whole.

  In the above embodiment, although the n-type thin film transistor is used, it may be a p-type thin film transistor.

  Although the organic EL display device has been described as a display device using thin film transistors in the above embodiment, the present invention is not limited to this. For example, the thin film transistor in the above embodiment can also be applied to other display devices such as a liquid crystal display device.

  In addition, an embodiment obtained by applying various modifications that those skilled in the art would think to each embodiment and modification, and components and functions in each embodiment and modification can be arbitrarily made without departing from the spirit of the present invention. The form realized by combining is also included in the present invention.

  The thin film transistor according to the present invention is widely used in various electric devices having a thin film transistor, such as a display such as an organic EL display device, a television set, a personal computer, a tablet terminal, a mobile phone and a smartphone using the display. be able to. Note that the display includes a plurality of pixels, and each pixel includes a plurality of sub-pixels. The sub-pixel includes a display element (an organic EL element in the case of an organic EL display) and a drive circuit for driving the display element. In general, each drive circuit includes at least a select transistor and a drive transistor. The thin film transistors described above can be used as the selection transistor and the drive transistor.

Reference Signs List 1 thin film transistor 10 substrate 20 undercoat layer 30, G1, G2 gate electrode 40 gate insulating layer 50 oxide semiconductor layer 51 first semiconductor layer 52 second semiconductor layer 60 protective layer 70S, S1, S2 source electrode 70D, D1, D2 drain Electrode 80 Insulating layer 100 Organic EL display 110 TFT substrate 120 Pixel 130 Organic EL element 131 Anode 132 EL layer 133 Cathode 140 Gate wiring 150 Source wiring 160 Power supply wiring SwTr switching transistor DrTr driving transistor C capacitor

Claims (11)

A gate electrode,
An oxide semiconductor layer facing the gate electrode;
A gate insulating layer disposed between the gate electrode and the oxide semiconductor layer;
A source electrode and a drain electrode electrically connected to the oxide semiconductor layer;
The oxide semiconductor layer includes an oxide containing at least indium and silicon, and includes a first region and a second region which is a region closer to the gate insulating layer than the first region.
The first region and the second region have the same composition,
Wherein the first region, the silicon concentration than the second region rather high,
The oxide semiconductor layer has a stacked structure including a first semiconductor layer formed as the first region and a second semiconductor layer formed as the second region,
The silicon concentration of the first semiconductor layer is 6.5 at% or more.
The silicon concentration of the second semiconductor layer is less than 6.5 at%,
The film thickness of the one semiconductor layer is 5 nm or more.
Thin film transistor.   The first region and the second region are made of InSiO.
  The thin film transistor according to claim 1. The silicon concentration of the first semiconductor layer is 11.7 at% or more.
The thin film transistor according to claim 1 . The silicon concentration of the oxide semiconductor layer is higher than the hydrogen concentration contained in the oxide semiconductor layer.
The thin film transistor according to any one of claims 1 to 3 . The film thickness of the second semiconductor layer is 15 nm or more.
The thin film transistor according to any one of claims 1 to 4 . The film thickness of the oxide semiconductor layer is 20 nm or more.
The thin film transistor according to any one of claims 1 to 4 . The gate electrode, the gate insulating layer, and the oxide semiconductor layer are stacked in this order on a substrate,
The source electrode and the drain electrode are formed above the oxide semiconductor layer,
The thin film transistor according to any one of claims 1 to 6 . Furthermore, a protective layer is provided on the oxide semiconductor layer,
The thin film transistor according to claim 7 . The oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in this order on a substrate,
The source electrode and the drain electrode are connected to the oxide semiconductor layer through a contact hole formed in the gate insulating layer.
The thin film transistor according to any one of claims 1 to 6 . Forming a gate electrode;
Forming an oxide semiconductor layer facing the gate electrode;
Forming a gate insulating layer between the gate electrode and the oxide semiconductor layer;
Forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,
The oxide semiconductor layer includes an oxide containing at least indium and silicon, and includes a first region and a second region which is a region closer to the gate insulating layer than the first region.
The first region and the second region have the same composition,
Wherein the first region, the silicon concentration than the second region rather high,
The oxide semiconductor layer has a stacked structure including a first semiconductor layer formed as the first region and a second semiconductor layer formed as the second region,
The silicon concentration of the first semiconductor layer is 6.5 at% or more.
The silicon concentration of the second semiconductor layer is less than 6.5 at%,
The film thickness of the one semiconductor layer is 5 nm or more.
Method of manufacturing a thin film transistor   The first region and the second region are made of InSiO.
  The manufacturing method of the thin-film transistor of Claim 10.

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