WO2016067585A1 - Thin film semiconductor device, organic el display device and method for manufacturing thin film semiconductor device - Google Patents

Abstract

This thin film semiconductor device comprises an oxide semiconductor layer (4), an insulating film (a third insulating film (73)), and a hydrogen barrier film (a second insulating film (72)) that is formed between the oxide semiconductor layer (4) and the insulating film and has hydrogen barrier properties that suppress permeation of hydrogen. The insulating film contains such an amount of hydrogen that can permeate through the hydrogen barrier film.

Description

Thin film semiconductor device, organic EL display device, and method of manufacturing thin film semiconductor device

The present disclosure relates to a thin film semiconductor device, an organic EL display device, and a method for manufacturing a thin film semiconductor device, and in particular, a thin film transistor (TFT: Thin Film Transistor) having an oxide semiconductor layer, a method for manufacturing the thin film transistor, and an organic film using the thin film transistor The present invention relates to an EL display device.

In an active matrix display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device, a TFT substrate on which TFTs are formed as switching elements or driving elements is used. For example, Patent Document 1 discloses an active matrix organic EL display device using a TFT substrate.

The channel layer of the TFT has a channel region in which carrier movement is controlled by a voltage applied to the gate electrode. As a material for the channel layer, various semiconductor materials such as silicon have been studied.

In recent years, development of an oxide semiconductor TFT using an oxide semiconductor such as a transparent amorphous oxide semiconductor (TAOS: Transparent Amorphous Oxide Semiconductor) as a channel layer has been promoted. For example, an oxide semiconductor TFT using TAOS made of a metal oxide (IGZO) of indium (In), gallium (Ga), and zinc (Zn) as a channel layer has been put into practical use.

JP 2010-27584 A

However, a TFT having a channel layer made of an oxide semiconductor has a problem that it is difficult to obtain desired performance.

It is an object of the technology of the present disclosure to provide a thin film semiconductor device, an organic EL display device, and a thin film semiconductor device manufacturing method having desired performance.

In order to achieve the above object, one embodiment of a thin film semiconductor device includes an oxide semiconductor layer, an insulating film, and hydrogen that is formed between the oxide semiconductor layer and the insulating film and suppresses permeation of hydrogen. A hydrogen barrier film having a barrier property, and the insulating film contains hydrogen in an amount capable of passing through the hydrogen barrier film.

One embodiment of a method for manufacturing a thin film semiconductor device includes a step of forming an oxide semiconductor layer, a step of forming an insulating film, and transmitting hydrogen between the oxide semiconductor layer and the insulating film. And a step of forming a hydrogen barrier film having a hydrogen barrier property, wherein the insulating film contains an amount of hydrogen that can pass through the hydrogen barrier film.

A thin film semiconductor device having desired performance can be realized.

FIG. 1 is a cross-sectional view of a thin film transistor according to an embodiment. FIG. 2 is a diagram for explaining a manufacturing method of the TFT. FIG. 3 is a diagram illustrating the relationship between the standby time from when the resist is removed and the oxide semiconductor layer is exposed until it is covered with the insulating layer, and the threshold voltage of the TFT. FIG. 4A is a diagram showing film formation conditions for the three types of silicon nitride films used in the experiment. FIG. 4B is a diagram showing physical property values of three types of silicon nitride films deposited under the deposition conditions of FIG. 4A. FIG. 5 shows a waiting time from when the resist is removed and the oxide semiconductor layer is exposed to covering with an insulating layer in a TFT using three types of silicon nitride films formed under the film forming conditions of FIG. 4A. It is a figure which shows the relationship with the threshold voltage of TFT. 6A is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 1. FIG. FIG. 6B is a diagram for explaining hydrogen diffusion in the thin film transistor according to the embodiment having the structure shown in FIG. 1. 6C is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 2. FIG. FIG. 7A is a cross-sectional view of the gate electrode formation step in the TFT manufacturing method according to the embodiment. FIG. 7B is a cross-sectional view of the gate insulating layer forming step in the TFT manufacturing method according to the embodiment. FIG. 7C is a cross-sectional view of the oxide semiconductor film formation step in the TFT manufacturing method according to the exemplary embodiment. FIG. 7D is a cross-sectional view of a resist formation step in the TFT manufacturing method according to the embodiment. FIG. 7E is a cross-sectional view of the oxide semiconductor film processing step in the manufacturing method of the TFT according to the exemplary embodiment. FIG. 7F is a cross-sectional view of the resist removal step in the TFT manufacturing method according to the embodiment. FIG. 7G is a cross-sectional view of the insulating layer forming step in the TFT manufacturing method according to the embodiment. FIG. 7H is a cross-sectional view of the contact hole forming step in the TFT manufacturing method according to the embodiment. FIG. 7I is a cross-sectional view of the source electrode and drain electrode forming step in the TFT manufacturing method according to the embodiment. FIG. 7J is a cross-sectional view of an insulating layer forming step in the TFT manufacturing method according to the embodiment. FIG. 8 is a partially cutaway perspective view of the organic EL display device according to the embodiment. FIG. 9 is a perspective view illustrating an example of a pixel bank of the organic EL display device according to the embodiment. FIG. 10 is an electric circuit diagram illustrating a configuration of a pixel circuit in the organic EL display device according to the embodiment.

Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present disclosure. Accordingly, the numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps (steps), order of steps, and the like shown in the following embodiments are merely examples and are intended to limit the present disclosure. is not. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are described as arbitrary constituent elements.

Each figure is a schematic diagram and is not necessarily shown strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.

(Embodiment)
In the following embodiments, a thin film transistor including an oxide semiconductor layer as a channel layer will be described as an example of a thin film semiconductor device including an oxide semiconductor layer.

[Configuration of thin film transistor]
First, the structure of the thin film transistor 10 according to the embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view of a thin film transistor according to an embodiment.

As shown in FIG. 1, the thin film transistor 10 is an oxide semiconductor TFT having an oxide semiconductor as a channel layer, and includes a substrate 1, a gate electrode 2, a gate insulating layer 3, an oxide semiconductor layer 4, and an insulating layer. A layer 5, a source electrode 6 </ b> S and a drain electrode 6 </ b> D, and an insulating layer 7 are provided. The thin film transistor 10 in this embodiment is a channel protection type bottom gate type TFT and adopts a top contact structure.

Hereinafter, each component of the thin film transistor 10 according to the present embodiment will be described in detail.

The substrate 1 is an insulating substrate made of an insulating material, for example, a glass substrate made of a glass material such as quartz glass, non-alkali glass, or high heat resistant glass. The substrate 1 is, for example, a G8 glass substrate.

The substrate 1 is not limited to a glass substrate but may be a resin substrate or the like. The substrate 1 may be a flexible substrate instead of a rigid substrate. Further, an undercoat layer may be formed on the surface of the substrate 1.

The gate electrode 2 is an electrode having a single layer structure or a multilayer structure of a conductive film made of a conductive material such as metal or an alloy thereof, and is formed in a predetermined shape above the substrate 1. The film thickness of the gate electrode 2 is, for example, about 20 nm to 500 nm.

Examples of the material of the gate electrode 2 include molybdenum, aluminum, copper, tungsten, titanium, manganese, chromium, tantalum, niobium, silver, gold, platinum, palladium, indium, nickel, neodymium, or the like. An alloy of a metal selected from (for example, molybdenum tungsten) is used.

The material of the gate electrode 2 is not limited to these, and conductive metal oxides such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO), polythiophene, A conductive polymer material such as polyacetylene can also be used. In addition, in order to improve the adhesion of the film, for example, titanium, aluminum, gold, or the like can be used as the gate electrode 2 as a metal having good adhesion to the oxide, and a sandwich between these metals is used. .

The gate insulating layer (gate insulating film) 3 is disposed between the gate electrode 2 and the oxide semiconductor layer 4. In the present embodiment, the gate insulating layer 3 is disposed so as to be located above the gate electrode 2. For example, the gate insulating layer 3 is formed so as to cover the gate electrode 2 over the entire surface of the substrate 1 on which the gate electrode 2 is formed. The film thickness of the gate insulating layer 3 is, for example, about 50 nm to 300 nm.

The gate insulating layer 3 is made of a material having electrical insulation, and as an example, a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or a hafnium oxide film, or A laminated film in which a plurality of these films are laminated.

The oxide semiconductor layer 4 is formed in a predetermined shape on the gate insulating layer 3 above the gate electrode 2. For example, the oxide semiconductor layer 4 is formed in an island shape over the gate insulating layer 3. In this embodiment, the oxide semiconductor layer 4 is a channel layer of the thin film transistor 10. That is, the oxide semiconductor layer 4 is a semiconductor layer including a channel region facing the gate electrode 2 with the gate insulating layer 3 interposed therebetween. The film thickness of the oxide semiconductor layer 4 is, for example, 10 nm to 200 nm.

The oxide semiconductor layer 4 is composed of an oxide semiconductor. The oxide semiconductor layer 4 is made of, for example, an oxide semiconductor containing at least one of indium (In), gallium (Ga), and zinc (Zn), specifically zinc oxide (ZnO _x ), oxide Indium gallium (InGaO _x ), indium gallium zinc oxide (InGaZnO _x ), or the like. In this embodiment, the oxide semiconductor layer 4 is a transparent amorphous oxide semiconductor (TAOS), and is an IGZO film made of InGaZnO _x which is a metal oxide of In, Ga, and Zn.

The oxide semiconductor of InGaZnO _X can be formed, for example, by a vapor deposition method such as a sputtering method or a laser deposition method using a polycrystalline sintered body having an InGaO ₃ (ZnO) ₄ composition as a target.

The insulating layer 5 (first insulating layer) is disposed on the oxide semiconductor layer 4. Specifically, the insulating layer 5 is formed over the gate insulating layer 3 so as to cover the oxide semiconductor layer 4. In this embodiment, the insulating layer 5 functions as a protective film (channel protective layer) that protects the channel region of the oxide semiconductor layer 4. In the present embodiment, the insulating layer 5 is an interlayer insulating film formed on the entire upper surface of the substrate 1. The film thickness of the insulating layer 5 is, for example, about 50 nm to 500 nm.

The insulating layer 5 is made of a material having electrical insulation properties, and is, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a single layer film of an aluminum oxide film, or a laminated film of these oxide films. .

In addition, an opening (contact hole) is formed in the insulating layer 5 so as to penetrate a part of the insulating layer 5. The oxide semiconductor layer 4 is connected to the source electrode 6S and the drain electrode 6D through the opening of the insulating layer 5.

The source electrode 6 </ b> S and the drain electrode 6 </ b> D are formed in a predetermined shape so that at least a part thereof is located above the insulating layer 5 and is connected to the oxide semiconductor layer 4. Specifically, the source electrode 6S and the drain electrode 6D are disposed on the insulating layer 5 so as to be spaced apart from each other in the horizontal direction (substrate horizontal direction) with respect to the substrate 1 and opposed to each other. It is connected to the oxide semiconductor layer 4 through the formed opening. The film thickness of the source electrode 6S and the drain electrode 6D is, for example, about 100 nm to 500 nm.

The source electrode 6S and the drain electrode 6D are electrodes having a single layer structure or a multilayer structure of a conductive film made of a conductive material or an alloy thereof. As the material of the source electrode 6S and the drain electrode 6D, for example, aluminum, tantalum, molybdenum, tungsten, silver, copper, titanium, or chromium is used. As an example, the source electrode 6S and the drain electrode 6D are electrodes having a three-layer structure in which a molybdenum film (Mo film), a copper film (Cu film), and a copper manganese alloy film (CuMn film) are formed in order from the bottom. Thus, by using the Cu film which is a low resistance material as the source electrode 6S and the drain electrode 6D, the resistance of the source electrode 6S and the drain electrode 6D can be reduced, and the source electrode 6S and the drain electrode 6D The resistance of the wiring in the same layer can be reduced.

The insulating layer 7 (second insulating layer) is a passivation film, and is formed on the insulating layer 5 so as to cover the source electrode 6S and the drain electrode 6D. In the present embodiment, the insulating layer 7 has a three-layer structure, and includes a first insulating film 71, a second insulating film 72, and a third insulating film 73.

The first insulating film 71 is formed on the insulating layer 5 so as to cover the source electrode 6S and the drain electrode 6D. The first insulating film 71 is preferably a film having good adhesion to the source electrode 6S and the drain electrode 6D and having a low hydrogen content in the film. In some cases, the insulating layer 7 is used as an interlayer insulating film, contact holes are formed in the insulating layer 7 and wirings, electrodes, and the like are connected to the source electrode 6S and the drain electrode 6D. Furthermore, it is preferable that the film can ensure workability by etching. Therefore, for example, a silicon oxide film is preferably used as the first insulating film 71. The film thickness of the first insulating film 71 is, for example, about 50 nm to 500 nm.

The second insulating film 72 is formed between the oxide semiconductor layer 4 and the third insulating film 73. In the present embodiment, the second insulating film 72 is formed over the first insulating film 71. The second insulating film 72 is a hydrogen barrier film having a hydrogen barrier property that suppresses permeation of hydrogen. Further, like the first insulating film 71, the second insulating film 72 is preferably a film that can ensure workability by etching. Therefore, for example, an aluminum oxide film (alumina film) is preferably used as the second insulating film 72.

The aluminum oxide film used as the second insulating film 72 in this embodiment has a film quality with a relatively low film density (that is, a film quality is coarse), and a part of hydrogen that permeates the aluminum oxide film Is blocked, and part of it is transmitted. In other words, the second insulating film 72 is a hydrogen barrier film having a film quality that does not completely block hydrogen but allows hydrogen to permeate. As described above, by using the aluminum oxide film as the second insulating film 72, a hydrogen barrier film having a performance capable of simultaneously realizing hydrogen permeation and hydrogen blocking according to the amount of hydrogen can be easily realized.

Such second insulating film 72, the film density can be used 2.80 g / cm ³ or more 3.25 g / cm ³ or less of the aluminum oxide film. Note that the above hydrogen barrier property can be obtained by setting the film density of the aluminum oxide film to 2.80 g / cm ³ or more. Further, when the film density of the aluminum oxide film is set to 3.25 g / cm ³ or less, workability by etching can be ensured. From the viewpoint of the hydrogen barrier property and processability, film density of the aluminum oxide film may further When it is 2.85 g / cm ³ or more 2.95 g / cm ³ or less.

Incidentally, the film density is deposited 2.80 g / cm ³ or more 3.25 g / cm ³ or less in the range aluminum oxide film may if the film thickness of the aluminum oxide film is 3nm or 30nm or less, The refractive index of the aluminum oxide film is preferably from 1.58 to 1.66.

The aluminum oxide film is expressed by a composition formula of AlO _{x, and} the number of oxygen atoms x is preferably 1.5 <x <2.0. The aluminum oxide film having a stoichiometric composition is Al ₂ O ₃ and the number of oxygen atoms x is 1.5. In this case, the Al ₂ O ₃ aluminum oxide film has a crystal structure. On the other hand, in the aluminum oxide film (AlO _x ) in which the number of oxygen atoms x is 1.5 <x <2.0, the aluminum oxide constituting the aluminum oxide film has an amorphous structure and the film quality is rough. Note that as the aluminum oxide film contains more oxygen atoms, the etchant used for wet etching (for example, phosphoric acid (HPO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and It becomes easy to react with a chemical solution mixed with water. Therefore, the aluminum oxide film in which the aluminum oxide has an amorphous structure is improved in the processability to etching than the aluminum oxide film having a crystalline structure. Therefore, in the aluminum oxide film represented by AlO _x , the number of oxygen atoms x is preferably 1.5 <x <2.0, and more preferably 1.79 ≦ x ≦ 1.85.

The third insulating film 73 is formed on the second insulating film 72. The third insulating film 73 contains an amount of hydrogen that can pass through the second insulating film 72 (hydrogen barrier film). That is, the third insulating film 73 is a high hydrogen film. The third insulating film 73 in this embodiment is made of a compound containing silicon and nitrogen, and specifically made of silicon nitride.

In the third insulating film 73 made of silicon nitride, the ratio of the Si—H bond concentration to the N—H bond concentration (Si—H / N—H) is greater than 0.3 (Si—H / N). -H> 0.3) and more preferably larger than 0.4 (Si-H / N-H> 0.4).

Further, the third insulating film 73 may be a film having a barrier property against moisture or the like in order to suppress entry of moisture or oxygen into the lower layer, and further, similarly to the first insulating film 71. A film that can ensure workability by etching is preferable. Therefore, as the third insulating film 73, for example, a single layer film of a silicon nitride film or a silicon oxynitride film, or a stacked film in which a plurality of these films are stacked may be used. The film thickness of the third insulating film 73 is, for example, about 50 nm to 700 nm.

In the insulating layer 7 in this embodiment, a silicon oxide film is used as the first insulating film 71, an aluminum oxide film is used as the second insulating film 72, and a silicon nitride film is used as the third insulating film 73. .

[Features of the present disclosure]
Next, features of the present disclosure will be described in detail, including the background to obtaining the knowledge of the present disclosure.

The TFT is formed, for example, by the method shown in FIG. FIG. 2 is a diagram for explaining a manufacturing method of the TFT.

As shown in FIG. 2A, a gate insulating layer 3 is formed so as to cover the gate electrode 2 formed on the substrate 1. The gate insulating layer 3 is a silicon oxide film, for example, and can be formed by a plasma CVD Chemical Vapor Deposition method.

Next, as illustrated in FIG. 2B, an oxide semiconductor film 4 a is formed on the gate insulating layer 3. For example, an IGZO film is formed as the oxide semiconductor film 4a over the entire surface of the gate insulating layer 3 by a sputtering method.

Next, as shown in FIG. 2C, a resist R having a predetermined shape is formed on the oxide semiconductor film 4a. The resist R is, for example, a photosensitive resin material, and the resist R having a predetermined shape can be formed by exposing and developing the resist film formed on the entire surface of the oxide semiconductor film 4a.

Next, as shown in FIG. 2D, the oxide semiconductor film 4a is processed into a predetermined shape by etching the oxide semiconductor film 4a using the resist R as a mask. Thus, the island-shaped oxide semiconductor layer 4 can be formed at a position facing the gate electrode 2. Etching is, for example, wet etching.

Next, as shown in FIG. 2E, the resist R is removed. At this time, the surface of the oxide semiconductor layer 4 is exposed by removing the resist R.

Next, as shown in FIG. 2F, an insulating layer 5 such as a silicon oxide film is formed on the gate insulating layer 3 so as to cover the oxide semiconductor layer 4.

Next, as shown in FIG. 2G, a contact hole is formed in the insulating layer 5, a metal film is formed and etched, thereby forming a source electrode 6S and a drain electrode 6D.

Next, as shown in FIG. 2H, an insulating layer 7A is formed on the insulating layer 5 so as to cover the source electrode 6S and the drain electrode 6D. Specifically, as the insulating layer 7A, a first insulating film 71A, a second insulating film 72A, and a third insulating film 73A are sequentially formed. For example, a silicon oxide film is formed as the first insulating film 71A, an aluminum oxide film is formed as the second insulating film 72A, and a silicon nitride film is formed as the third insulating film 73A.

The TFT can be manufactured in this way, but in the process of processing the oxide semiconductor film 4a in FIG. 2, the waiting time from the exposure of the oxide semiconductor layer 4 to the covering of the insulating layer 5 Exists. During standby, the film is left in the atmosphere, and the film surface during production is exposed to the atmosphere.

The present inventor considered that this standby time might affect the threshold voltage (Vth) of the TFT, and conducted an experiment on the dependence between the standby time and the threshold voltage of the TFT. The result is shown in FIG.

FIG. 3 shows data relating to the TFT manufactured by the method shown in FIG. 2. The waiting time until the resist R is removed and the oxide semiconductor layer 4 is exposed and covered with the insulating layer 5 and the threshold voltage of the TFT are shown. Shows the relationship. In FIG. 3, an IGZO film is used as the oxide semiconductor film 4a.

As shown in FIG. 3, after the oxide semiconductor film 4a is etched, the resist R is removed to expose the oxide semiconductor layer 4 (FIG. 2E), and then the oxide semiconductor layer 4 is insulated. It has been found that there is a correlation between the waiting time until coating with the layer 5 and the threshold voltage of the TFT using the oxide semiconductor layer 4.

Specifically, as the standby time (the surface exposure time of the oxide semiconductor layer 4) from the exposure of the oxide semiconductor layer 4 to the covering of the oxide semiconductor layer 4 with the insulating layer 5 increases, It was found that the threshold voltage (Vth) increases. An increase in the threshold voltage of the TFT causes a decrease in display uniformity and reliability of the display panel, and also causes an increase in power consumption.

Therefore, as a result of intensive studies on means for solving this problem, the inventor of the present application has adjusted the threshold value of the TFT by adjusting the amount of hydrogen contained in the third insulating film 73A (SiN) of the insulating layer 7A in FIG. An experiment was conducted on the third insulating film 73A (SiN) on the assumption that the voltage could be controlled.

Specifically, using the third insulating film 73A (SiN) having different physical properties, the oxide semiconductor layer 4 is covered with the insulating layer 5 after the oxide semiconductor layer 4 is exposed as shown in FIG. The relationship between the waiting time until the TFT and the threshold voltage of the TFT using the oxide semiconductor layer 4 was examined. In this experiment, an IGZO film is used as the oxide semiconductor film 4a.

FIG. 4A shows the deposition conditions for the three types of third insulating films 73A used at that time. Samples 1, 2 and 3 were all silicon nitride films (SiN) and were formed using a parallel plate RF plasma CVD apparatus.

The film formation conditions (numerical values) shown in FIG. 4A are standardized with the film formation conditions of Sample 1 as “1”, and the film formation conditions of Samples 1, 2, and 3 are shown as relative ratios. Note that the film formation temperature is the same in all cases.

As shown in FIG. 4A, the film forming conditions of sample 1 are conditions for forming a silicon nitride film having a high stress and low hydrogen film quality, and the film forming conditions of sample 2 are low stress and high hydrogen. This is a condition for forming a silicon nitride film having a film quality, and the film forming condition for the sample 3 is a condition for forming a silicon nitride film having a low stress and a low hydrogen film quality. Thus, the high hydrogen film (sample 2) can be produced by increasing the SiH ₄ / NH ₃ flow rate ratio, the RF power, and the pressure with respect to the low hydrogen film (sample 1, sample 3).

FIG. 4B shows physical property values of three types of third insulating films 73A (SiN) of Sample 1, Sample 2, and Sample 3 obtained under the film forming conditions of FIG. 4A.

In FIG. 4B, “Si—H” is a bond between silicon and hydrogen (Si—H bond), and the value indicates the concentration of Si—H bond in the silicon nitride film. Similarly, “N—H” is a bond between nitrogen and hydrogen (N—H bond), and the value indicates the concentration of the N—H bond in the silicon nitride film. “Si—H” and “N—H” were measured by a Fourier transform infrared spectrophotometer (FTIR: Fourier Transform Infrared Spectroscopy).

As shown in FIG. 4B, the high-hydrogen silicon nitride (sample 2) has a higher concentration of Si—H bonds in the silicon nitride film, compared to the low-hydrogen silicon nitride (sample 1, sample 3). It can be seen that the ratio of the Si—H bond concentration to the N—H bond concentration (Si—H / NH) is large.

Specifically, Si—H / N—H> 0.4 for high hydrogen silicon nitride (sample 2), and Si—H / N— for low hydrogen silicon nitride (sample 1, sample 3). H <0.1, and high-hydrogen silicon nitride (sample 2) has a Si—H / N—H ratio five times or more that of low-hydrogen silicon nitride (sample 1 and sample 3). .

FIG. 5 shows a waiting time from when the resist R is removed and the oxide semiconductor layer 4 is exposed to covering with the insulating layer 5 with respect to the TFTs manufactured using the samples 1, 2 and 3. The relationship with the threshold voltage of TFT is shown.

As can be seen from FIG. 5, the threshold voltage of the TFT increases as the standby time increases for silicon nitride (sample 1) having a low hydrogen and high stress film quality. It can also be seen that the threshold voltage of the TFT increases as the standby time increases for silicon nitride (sample 3) having a low hydrogen and low stress film quality. In other words, regardless of the magnitude of the film stress, it is considered that the threshold voltage of the TFT of low hydrogen silicon nitride increases as the standby time increases.

On the other hand, in the case of silicon nitride (sample 2) having a high hydrogen and low stress film quality, the threshold voltage of the TFT does not change much even when the standby time is increased. Rather, the threshold voltage of the TFT is increased as the standby time is increased. It can be seen that it gradually decreases and then saturates.

From the results shown in FIG. 5, the threshold voltage of the third insulating film 73, which is a silicon nitride film, increases as the standby time increases in the case of low hydrogen (Si—H / N—H <0.1). However, in the case of high hydrogen (Si—H / N—H> 0.4), it gradually decreases as the standby time increases and then saturates.

As a result of examining this result, the inventors of the present application have found that the threshold voltage of the TFT changes for the following reason. The reason for this will be described with reference to FIGS. 6A, 6B, and 6C. 6A is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 1. FIG. FIG. 6B is a diagram for explaining hydrogen diffusion in the thin film transistor according to the embodiment having the structure shown in FIG. 1. 6C is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 2. FIG.

In the oxide semiconductor TFT, when a silicon nitride film is used as a passivation film formed above the oxide semiconductor layer, a low-hydrogen silicon nitride film is usually used from the viewpoint of ensuring reliability. This is to prevent hydrogen contained in the silicon nitride film from entering the oxide semiconductor layer by a thermal process or the like and causing hydrogen damage to the oxide semiconductor layer. When the oxide semiconductor layer is damaged by hydrogen, the threshold voltage of the TFT changes. In other words, hydrogen is likely to diffuse if there are many Si—H bonds in the silicon nitride film, and therefore it is generally considered that it is important to keep the Si—H bonds low. It is common sense.

Moreover, in order to further prevent hydrogen in the silicon nitride film from diffusing into the lower layer, as shown in FIG. 6A, between the oxide semiconductor layer 4 and the third insulating film 73J (silicon nitride film), It is also considered to insert aluminum oxide, which is a hydrogen barrier film, as the second insulating film 72. Thereby, hydrogen diffused from the third insulating film 73J (silicon nitride film) can be blocked by the second insulating film 72 (aluminum oxide film), so that damage to the oxide semiconductor layer 4 due to hydrogen can be prevented. Has been.

Thus, so far, a low-hydrogen silicon nitride film has been used as the passivation film above the oxide semiconductor layer, and a hydrogen barrier film has been introduced between the silicon nitride film and the oxide semiconductor layer. It was.

However, when the thin film transistor having the structure shown in FIG. 6A is actually manufactured, sufficient TFT characteristics cannot be obtained. The inventor of the present application diligently studied this point and found that the surface exposure time of the oxide semiconductor layer 4 has an influence on the threshold voltage. This point will be described in detail below.

As shown in FIG. 2, when the oxide semiconductor layer 4 is formed by etching the oxide semiconductor film, the oxide semiconductor layer 4 (IGZO film) immediately after the etching process (FIG. 2D) In, Ga, and Zn are bonded to oxygen at an equal ratio, and oxygen vacancies are generated at an equal ratio. That is, the oxide semiconductor layer 4 immediately after the etching process has a uniform film quality.

However, after that, as shown in FIG. 2E, when the resist R on the oxide semiconductor layer 4 is removed and the oxide semiconductor layer 4 is left in the atmosphere, the surface of the oxide semiconductor layer 4 is exposed to the atmosphere. Be exposed. Thereby, as shown in FIG. 6A, it was found that a Ga-excess layer (Ga-rich layer) 41 containing gallium (Ga) excessively was generated as the surface layer of the oxide semiconductor layer 4.

This is because the Ga—O bond is stronger than the In—O bond and the Zn—O bond, so that the oxygen deficiency of Ga fills preferentially over In and Zn on the surface of the oxide semiconductor layer 4, and In and Zn This is probably because Ga—O bonds are increased on the surface of the oxide semiconductor layer 4 as a result of Ga depriving of oxygen.

Note that the bond energy of the Ga—O bond is 374 (kJmol ⁻¹ ) and the bond energy of the In—O bond is 346 (kJmol ⁻¹ ), but the bond energy of the Zn—O bond is 250 (kJmol ^−1). ). In addition, it is considered that the Ga excess layer 41 is locally generated on the surface of the oxide semiconductor layer 4.

Thus, when the Ga excess layer 41 is generated as the surface layer of the oxide semiconductor layer 4, the composition of the oxide semiconductor layer 4 is changed, and the threshold voltage (Vth) of the TFT is positively shifted. As a result, it is considered that the result shown in FIG. 3 was obtained. That is, it is considered that an increase in the surface exposure time (standby time) of the oxide semiconductor layer 4 leads to an increase in the threshold voltage of the TFT.

Therefore, as a result of intensive studies, the inventor of the present application has increased the waiting time (the surface exposure time of the oxide semiconductor layer 4) by making the upper insulating film (silicon nitride film) of the hydrogen barrier film a high hydrogen film. It was found that the increase in the threshold voltage accompanying the above can be mitigated.

That is, in a thin film semiconductor device having a structure in which a hydrogen barrier film is formed between an oxide semiconductor layer and an insulating film, the threshold voltage of the TFT can be controlled by controlling the amount of hydrogen contained in the insulating film. I found it. The principle will be described with reference to FIG. 6B.

As shown in FIG. 6B, in the thin film transistor in this embodiment, as the third insulating film 73, an insulating film containing hydrogen in an amount that can pass through the second insulating film 72 that is a hydrogen barrier film is used. Yes. That is, the third insulating film 73 has such an amount that hydrogen blocked by the second insulating film 72 (hydrogen barrier film) and hydrogen that passes through the second insulating film 72 (hydrogen barrier film) exist. Contains hydrogen.

Specifically, as the second insulating film 72, a silicon nitride film formed under the film forming conditions of the sample 2 in FIG. 4A is used. Therefore, the second insulating film 72 is a high-hydrogen, low-stress silicon nitride film (Si—H / N—H> 0.4) having the physical property values of the sample 2 in FIG. 4B.

Thereby, as shown in FIG. 6B, when hydrogen contained in the third insulating film 73 (silicon nitride film) is diffused by a thermal process or the like, part of the hydrogen is the second insulating film 72 which is a hydrogen barrier film. However, the other part of hydrogen passes through the second insulating film 72 which is a hydrogen barrier film. Then, the hydrogen that has passed through the second insulating film 72 reduces the Ga excess layer 41 generated on the surface of the oxide semiconductor layer 4. That is, the excess oxide in the Ga excess layer 41 is reduced by the hydrogen that has passed through the second insulating film 72. As a result, the surface of the oxide semiconductor layer 4 is modified, the characteristics of the threshold voltage changed by the Ga excess layer 41 are restored, and the threshold voltage is normalized.

As described above, as the insulating film (passivation film) formed above the oxide semiconductor layer 4, a low-hydrogen silicon nitride film (Si—H / N—H <0.1) is usually used. In the thin film transistor in this embodiment, a silicon nitride film of high hydrogen (Si—H / N—H> 0.4) is used. Thereby, an increase in threshold fluctuation accompanying an increase in the surface exposure time (standby time) of the oxide semiconductor layer 4 can be suppressed.

As shown in FIG. 6C, a structure in which the second insulating film 72 (aluminum oxide film) that is a hydrogen barrier film is not formed in the thin film transistor in this embodiment is also conceivable. However, in this case, if hydrogen contained in the third insulating film 73 (silicon nitride film) is diffused by a thermal process or the like, the excess oxide of the Ga excess layer 41 is caused by a large amount of hydrogen diffused all at once without being blocked. In addition to being reduced, the oxide in the original oxide semiconductor layer 4 may be reduced. As a result, the oxide semiconductor layer 4 becomes conductive, and there is a possibility that the original operation as a TFT cannot be obtained.

Therefore, as shown in FIG. 6B, a hydrogen barrier film (second insulating film 72) having a hydrogen barrier property is provided between the oxide semiconductor layer 4 and the insulating film containing hydrogen (third insulating film 73). ) Is desired. In other words, with respect to the side effect of the decrease in TFT reliability due to the high hydrogenation of the third insulating film 73, a hydrogen barrier film is inserted between the oxide semiconductor layer 4 and the insulating film (third insulating film 73). Therefore, it is preferable to suppress excessive diffusion of hydrogen from the insulating film (third insulating film 73).

Thus, the inventors of the present application have found that the threshold voltage of the TFT can be controlled by controlling the amount of hydrogen contained in the insulating film (third insulating film 73).

[Thin Film Transistor Substrate Manufacturing Method]
Next, a method for manufacturing the thin film transistor 10 according to the embodiment will be described with reference to FIGS. 7A to 7J. 7A to 7J are cross-sectional views of each step in the method of manufacturing the thin film transistor according to the embodiment.

First, as shown in FIG. 7A, a substrate 1 is prepared, and a gate electrode 2 having a predetermined shape is formed above the substrate 1. For example, a glass substrate is prepared as the substrate 1, a gate metal film is formed on the glass substrate by a sputtering method, and the gate metal film is processed using a photolithography method and a wet etching method, whereby a predetermined shape is obtained. The gate electrode 2 is formed. When an undercoat layer is formed on the surface of the substrate 1, the gate electrode 2 is formed on the undercoat layer.

Next, as shown in FIG. 7B, a gate insulating layer 3 is formed on the gate electrode 2. For example, a film is formed on the entire upper surface of the substrate 1 so as to cover the gate electrode 2. The gate insulating layer 3 is, for example, a silicon oxide film. In this case, a silicon oxide film can be formed by a plasma CVD method using silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as an introduction gas.

Note that the gate insulating layer 3 may be a single layer film or a laminated film. For example, as the gate insulating layer 3, a stacked film in which a silicon nitride film and a silicon oxide film are sequentially formed can be used. The silicon nitride film can be formed by a plasma CVD method using, for example, silane gas (SiH ₄ ), ammonia gas (NH ₃ ), and nitrogen gas (N ₂ ) as introduction gases.

Next, as illustrated in FIG. 7C, the oxide semiconductor film 4 a is formed over the substrate 1. Specifically, the oxide semiconductor film 4 a is formed over the gate insulating layer 3. The oxide semiconductor film 4a is an IGZO film made of, for example, InGaZnO _X and can be formed by a sputtering method.

Specifically, for example, an oxide semiconductor (In—Ga—Zn—O) made of In, Ga, and Zn having a composition ratio of In: Ga: Zn = 1: 1: 1 is used as a sputtering target. Sputtering in an oxygen atmosphere. In this case, argon (Ar) gas as an inert gas flows into the vacuum chamber and a gas containing oxygen (O ₂ ) as a reactive gas flows, and a voltage with a predetermined power density is applied to the target material. Thus, the oxide semiconductor film 4a made of an amorphous IGZO film can be formed on the gate insulating layer 3.

Next, as shown in FIGS. 7D to 7F, the oxide semiconductor film 4a is patterned to form the oxide semiconductor layer 4 having a predetermined shape. The patterning of the oxide semiconductor film 4a can be performed using a photolithography method and an etching method.

Specifically, first, as shown in FIG. 7D, a resist R having a predetermined shape is formed on the oxide semiconductor film 4a. The resist R is, for example, a photosensitive resin material, and the resist R having a predetermined shape can be formed by exposing and developing the resist film formed on the entire surface of the oxide semiconductor film 4a. Specifically, the resist film is exposed and developed so as to leave the resist R at least at a position facing the gate electrode 2.

Next, as shown in FIG. 7E, the oxide semiconductor film 4a is etched using the resist R as a mask. Accordingly, the oxide semiconductor film 4a in a region where the resist R is not formed is removed by etching, and the oxide semiconductor film 4a is processed, so that the oxide semiconductor layer 4 having a predetermined shape can be formed. Specifically, the island-shaped oxide semiconductor layer 4 is formed so as to include a position facing the gate electrode 2.

Etching is, for example, wet etching. In this case, when the oxide semiconductor film 4a is an IGZo film, as an etching solution, for example, a chemical solution in which phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed is used. Use it.

Next, as shown in FIG. 7F, the resist R is removed (peeled). The resist R can be removed with a stripping solution. At this time, the surface of the oxide semiconductor layer 4 is exposed by removing the resist R. Thereby, the oxide semiconductor layer 4 having a predetermined shape can be formed.

Next, as shown in FIG. 7G, an insulating layer 5 is formed on the oxide semiconductor layer 4. In this embodiment, the insulating layer 5 is formed over the entire surface of the gate insulating layer 3 so as to cover the oxide semiconductor layer 4.

The insulating layer 5 is, for example, a silicon oxide film. In this case, a silicon oxide film can be formed by a plasma CVD method using silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as an introduction gas.

Next, as shown in FIG. 7H, contact holes CH (openings) are formed in the insulating layer 5. For example, the contact hole CH is formed by removing a part of the insulating layer 5 using a photolithography method and an etching method so that a part of the oxide semiconductor layer 4 is exposed.

For example, when the insulating layer 5 is a silicon oxide film, the contact hole CH can be formed in the silicon oxide film by a dry etching method using a reactive ion etching (RIE) method. In this case, for example, carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ) can be used as the etching gas. Note that the contact hole CH is formed over a region to be a source contact region and a drain contact region of the oxide semiconductor layer 4.

Next, as shown in FIG. 7I, a source electrode 6S and a drain electrode 6D having a predetermined shape are formed so as to be connected to the oxide semiconductor layer 4. Specifically, a source / drain metal film is formed on the insulating layer 5 by a sputtering method so as to fill the contact hole CH of the insulating layer 5, and then the source / drain metal film is formed using a photolithography method and an etching method. By processing, a source electrode 6S and a drain electrode 6D having a predetermined shape can be formed.

As the source / drain metal film, a metal film having a three-layer structure of a Mo film, a Cu film, and a CuMn film can be used. In addition, wet etching of a source / drain metal film made of a Mo film, a Cu film, and a CuMn film can be performed using, for example, a chemical solution in which a hydrogen peroxide solution (H ₂ O ₂ ) and an organic acid are mixed.

Next, as shown in FIG. 7J, the insulating layer 7 is formed on the substrate 1 on which the source electrode 6S and the drain electrode 6D are formed. In this embodiment mode, an insulating layer 7 having a three-layer structure including a first insulating film 71, a second insulating film 72, and a third insulating film 73 is formed. As an example, the first insulating film 71 is a silicon oxide film, the second insulating film 72 is an aluminum oxide film, the third insulating film 73 is a silicon nitride film, and these are sequentially deposited. Yes.

Specifically, the first insulating film 71, which is a silicon oxide film, can be formed by, for example, plasma CVD.

The second insulating film 72, which is an aluminum oxide film, is formed by sputtering, for example. For example, an aluminum oxide film can be formed by performing sputtering using aluminum as a target and argon gas and oxygen gas as process gases. Note that aluminum oxide may be used as a target. In this case, argon gas is used as the process gas.

The third insulating film 73, which is a silicon nitride film, can be formed by plasma CVD or the like, for example. In this embodiment mode, a silicon nitride film is formed under the film formation conditions of the sample 2 in FIG. 4A. Accordingly, the third insulating film 73 is a high-hydrogen silicon nitride film, and contains at least hydrogen in an amount that can pass through the second insulating film 72 (aluminum oxide film).

Thus, the thin film transistor 10 can be manufactured. After that, if necessary, a contact hole may be formed in the insulating layer 7 to form an electrode or a wiring, or a passivation film may be formed on the insulating layer 7. Further, heat treatment (annealing) may be performed at a temperature exceeding 290 ° C. in order to repair oxygen vacancies in the oxide semiconductor layer 4 and stabilize the characteristics of the oxide semiconductor layer 4.

[Summary]
As described above, according to the thin film transistor 10 of the present embodiment, the oxide semiconductor layer 4, the insulating film (third insulating film 73), the oxide semiconductor layer 4 and the insulating film (third insulating film). And a hydrogen barrier film (second insulating film 72) formed between the insulating film (third insulating film 73) and the hydrogen barrier film (second insulating film 72). An amount of hydrogen that can permeate is included.

As a result, part of hydrogen contained in the insulating film (third insulating film 73) permeates the hydrogen barrier film (second insulating film 72) and modifies the surface of the oxide semiconductor layer 4 to thereby improve the original property. It can be returned to the state. As a result, the threshold voltage of the TFT is increased as the standby time (the surface exposure time of the oxide semiconductor layer 4) from when the resist R is removed and the oxide semiconductor layer 4 is exposed until it is covered with the insulating layer 5 increases. The increase can be suppressed. Therefore, the thin film transistor 10 having desired performance can be realized.

In the thin film transistor 10 according to the present embodiment, the insulating film (third insulating film 73) is made of a compound containing silicon and nitrogen (for example, silicon nitride), and the insulating film (third insulating film 73). The ratio of the Si—H bond concentration to the N—H bond concentration in) is greater than 0.3. That is, the insulating film (third insulating film 73) is a high hydrogen film containing a large amount of hydrogen.

Thus, an insulating film (third insulating film 73) containing hydrogen that can pass through the hydrogen barrier film (second insulating film 72) and modify the surface of the oxide semiconductor layer 4 can be obtained. The thin film transistor 10 having desired performance can be easily realized.

In the thin film transistor 10 according to the present embodiment, the second insulating film 72 that is a hydrogen barrier film is an aluminum oxide film.

Thereby, it is possible to realize a hydrogen barrier film capable of simultaneously allowing hydrogen permeation and hydrogen blocking according to the amount of hydrogen diffusing from the insulating film (third insulating film 73).

Further, in the thin film transistor 10 according to this embodiment, the film density of the second insulating film 72 is aluminum oxide film is 2.80 g / cm ³ or more 3.25 g / cm ³ or less.

This makes it possible to reliably realize a hydrogen barrier film capable of simultaneously realizing hydrogen permeation and hydrogen blocking.

[Organic EL display device]
Next, an example in which the thin film transistor 10 according to the above embodiment is applied to a display device will be described with reference to FIGS. In this embodiment, an application example to an organic EL display device will be described.

FIG. 8 is a partially cutaway perspective view of the organic EL display device according to the embodiment. FIG. 9 is a perspective view illustrating an example of a pixel bank of the organic EL display device according to the embodiment. The above-described thin film transistor 10 can be used as a switching element or a driving element of an active matrix substrate in an organic EL display device.

As shown in FIGS. 8 and 9, the organic EL display device 100 includes a TFT substrate (TFT array substrate) 110 on which a plurality of thin film transistors (not shown) are arranged, an anode 131 as a lower electrode, and an organic material. It is composed of a laminated structure of an EL layer 132 that is a light emitting layer and an organic EL element (light emitting portion) 130 that includes a cathode 133 that is a transparent upper electrode.

The organic EL display device 100 in this embodiment is a top emission type, and the anode 131 is a reflective electrode. The organic EL display device 100 is not limited to the top emission type, and may be a bottom emission type.

The TFT substrate 110 has a plurality of pixels 120 arranged in a matrix, and each pixel 120 is provided with a pixel circuit.

The organic EL element 130 is formed corresponding to each of the plurality of pixels 120, and the light emission of each organic EL element 130 is controlled by a pixel circuit provided in each pixel 120. The organic EL element 130 is formed on an interlayer insulating film (planarization layer) formed so as to cover a plurality of thin film transistors.

The organic EL element 130 has a configuration in which an EL layer 132 is disposed between the anode 131 and the cathode 133. A hole transport layer is further stacked between the anode 131 and the EL layer 132, and an electron transport layer is further stacked between the EL layer 132 and the cathode 133. Note that another functional layer such as a hole injection layer or an electron injection layer may be provided between the anode 131 and the cathode 133.

Each pixel 120 is driven and controlled by each pixel circuit. Further, as shown in FIG. 8, the TFT substrate 110 includes a plurality of gate wirings (scanning lines) 140 arranged along the row direction of the pixels 120 and the column direction of the pixels 120 so as to intersect the gate wirings 140. A plurality of source wirings (signal wirings) 150 arranged along the lines and a plurality of power source wirings (not shown in FIG. 8) arranged in parallel with the source wirings 150 are formed. Each pixel 120 is partitioned by, for example, an orthogonal gate wiring 140 and a source wiring 150.

The gate wiring 140 is connected to the gate electrode of the thin film transistor operating as a switching element included in each pixel circuit for each row. The source wiring 150 is connected to the source electrode of the thin film transistor operating as a switching element included in each pixel circuit for each column. The power supply wiring is connected to the drain electrode of the thin film transistor operating as a driving element included in each pixel circuit for each column.

As shown in FIG. 9, each pixel 120 of the organic EL display device 100 is composed of sub-pixels 120R, 120G, and 120B of three colors (red, green, and blue), and these sub-pixels 120R, 120G, and 120B. Are arranged in a matrix. The sub-pixels 120R, 120G, and 120B are separated from each other by the bank 121. The banks 121 are formed in a lattice shape so that the ridges extending in parallel to the gate wiring 140 and the ridges extending in parallel to the source wiring 150 intersect each other. Each of the portions surrounded by the protrusions (that is, the opening of the bank 121) and each of the sub-pixels 120R, 120G, and 120B have a one-to-one correspondence. In the present embodiment, the bank 121 is a pixel bank, but may be a line bank.

The anode 131 is formed for each of the sub-pixels 120R, 120G, and 120B on the interlayer insulating film (flattening layer) on the TFT substrate 110 and in the opening of the bank 121. Similarly, the EL layer 132 is formed for each of the sub-pixels 120R, 120G, and 120B on the anode 131 and in the opening of the bank 121. The transparent cathode 133 is continuously formed on the plurality of banks 121 so as to cover all the EL layers 132 (all the sub-pixels 120R, 120G, and 120B).

Furthermore, the pixel circuit is provided for each of the sub-pixels 120R, 120G, and 120B, and each of the sub-pixels 120R, 120G, and 120B and the corresponding pixel circuit are electrically connected by a contact hole and a relay electrode. Yes. Note that the sub-pixels 120R, 120G, and 120B have the same configuration except that the emission color of the EL layer 132 is different.

Here, an example of the circuit configuration of the pixel circuit in the pixel 120 will be described with reference to FIG. FIG. 10 is an electric circuit diagram illustrating a configuration of a pixel circuit in the organic EL display device according to the embodiment. Note that the pixel circuit is not limited to the configuration shown in FIG.

As shown in FIG. 10, the pixel circuit in each pixel 120 includes a thin film transistor SwTr that operates as a switching element, a thin film transistor DrTr that operates as a drive element, and a capacitor C that stores data to be displayed on the corresponding pixel 120. Composed. In the present embodiment, the thin film transistor SwTr is a switching transistor for selecting the pixel 120, and the thin film transistor DrTr is a drive transistor for driving the organic EL element 130.

The thin film transistor SwTr includes a gate electrode G1 connected to the gate wiring 140, a source electrode S1 connected to the source wiring 150, a drain electrode D1 connected to the capacitor C and the gate electrode G2 of the thin film transistor DrTr, and a channel layer (FIG. Not shown). In the thin film transistor SwTr, when a predetermined voltage is applied to the connected gate wiring 140 and source wiring 150, the voltage applied to the source wiring 150 is stored in the capacitor C as a data voltage.

The thin film transistor DrTr includes a gate electrode G2 connected to the drain electrode D1 of the thin film transistor SwTr and the capacitor C, a drain electrode D2 connected to the power supply wiring 160 and the capacitor C, and a source electrode connected to the anode 131 of the organic EL element 130. It is comprised by S2 and a semiconductor film (not shown). The thin film transistor DrTr supplies a current corresponding to the data voltage held by the capacitor C from the power supply wiring 160 to the anode 131 of the organic EL element 130 through the source electrode S2. Thereby, in the organic EL element 130, a drive current flows from the anode 131 to the cathode 133, and the EL layer 132 emits light.

Note that the organic EL display device 100 having the above configuration employs an active matrix system in which display control is performed for each pixel 120 located at the intersection of the gate wiring 140 and the source wiring 150. Thereby, the corresponding organic EL element 130 selectively emits light by the thin film transistors SwTr and DrTr of each pixel 120 (each sub-pixel 120R, 120G, 120B), and a desired image is displayed.

As described above, since the thin film transistor 10 in the above embodiment is used in the organic EL display device 100 in the present embodiment, a display device having excellent display performance can be realized.

(Modification)
As described above, the thin film transistor and the manufacturing method thereof have been described based on the embodiment, but the technology of the present disclosure is not limited to the above embodiment.

For example, in the above embodiment, the insulating layer 7 has a three-layer structure, but without forming the first insulating film 71, an aluminum oxide film (lower layer) and silicon nitride are formed from the oxide semiconductor layer 4 side. It is good also as a layer structure which laminated | stacked the film | membrane (upper layer).

In the above embodiment, the oxide semiconductor film 4a and the oxide semiconductor layer 4 are oxide semiconductors (in particular, IGZO films) including at least one of In, Ga, and Zn. However, the present invention is not limited to this. Absent. For example, as the oxide semiconductor film 4a and the oxide semiconductor layer 4, an ISO film made of an oxide semiconductor (In—Si—O) containing indium (In) and silicon (Si), indium (In), and tungsten (W ) Containing an oxide semiconductor (In—W—O), an oxide semiconductor in which Zn (zinc) is further added to In and W (In—W—Zn—O), and the like. In addition, an In oxide-based oxide semiconductor film containing Hf or Ti as an additive, or a Zn oxide-based oxide semiconductor film containing Si, W, Ga, Hf, and Ti as additives. Etc.

In the above embodiment, the thin film transistor 10 is a bottom gate type, but the technology of the present disclosure can also be applied to a top gate type thin film transistor.

In the above embodiment, the thin film transistor 10 is a channel etching stopper type (channel protection type), but the technique of the present disclosure can also be applied to a channel etching type thin film transistor.

In the above embodiment, an example in which the thin film transistor is applied to an organic EL display device has been described. However, the thin film transistor in the above embodiment can also be applied to another display device such as a liquid crystal display device.

In this case, the display device (display panel) can be used as a flat panel display. For example, a display device such as an organic EL display device can be used as a display panel of any electronic device such as a television set, a personal computer, or a mobile phone. In particular, it is suitable for a large-screen and high-definition display device.

In addition, the form obtained by making various modifications conceived by those skilled in the art with respect to each embodiment and modification, and the components and functions in each embodiment and modification are arbitrarily set within the scope of the present disclosure. A form realized by combination is also included in the present disclosure.

The technique disclosed herein can be widely used in a thin film transistor using an oxide semiconductor, a manufacturing method thereof, a display device such as an organic EL display device using the thin film transistor, and the like.

DESCRIPTION OF SYMBOLS 1 Substrate 2, G1, G2 Gate electrode 3 Gate insulating layer 4 Oxide semiconductor layer 4a Oxide semiconductor film 5, 7, 7A Insulating layer 6S, S1, S2 Source electrode 6D, D1, D2 Drain electrode 10 Thin film transistor 41 Ga excess layer 71, 71A First insulating film 72, 72A Second insulating film 73, 73A, 73J Third insulating film 100 Organic EL display device 110 TFT substrate 120 Pixel 120R, 120G, 120B Subpixel 121 Bank 130 Organic EL element 131 Anode 132 EL layer 133 Cathode 140 Gate wiring 150 Source wiring 160 Power supply wiring SwTr, DrTr Thin film transistor C Capacitor CH Contact hole

Claims (14)

1. An oxide semiconductor layer;
   An insulating film;
   A hydrogen barrier film formed between the oxide semiconductor layer and the insulating film and having a hydrogen barrier property to suppress permeation of hydrogen;
   The thin film semiconductor device, wherein the insulating film contains an amount of hydrogen that can pass through the hydrogen barrier film.
2. The insulating film is made of a compound containing silicon and nitrogen,
   2. The thin film semiconductor device according to claim 1, wherein a ratio of the Si—H bond concentration to the N—H bond concentration in the insulating film is greater than 0.3.
3. The insulating film is made of a compound containing silicon and nitrogen,
   2. The thin film semiconductor device according to claim 1, wherein a ratio of the Si—H bond concentration to the N—H bond concentration in the insulating film is greater than 0.4.
4. The thin film semiconductor device according to claim 2, wherein the insulating film is a silicon nitride film.
5. The thin film semiconductor device according to any one of claims 1 to 4, wherein the hydrogen barrier film is an aluminum oxide film.
6. The film density of the aluminum oxide film, a thin film semiconductor device according to claim 5 is 2.80 g / cm ³ or more 3.25 g / cm ³ or less.
7. The aluminum oxide film is represented by AlO _x
   The thin film semiconductor device according to claim 5, wherein 1.5 <x <2.0.
8. The thin film semiconductor device according to any one of claims 5 to 7, wherein a refractive index of the aluminum oxide film is 1.58 or more and 1.66 or less.
9. The thin film semiconductor device according to any one of claims 5 to 8, wherein the aluminum oxide film has a thickness of 3 nm to 30 nm.
10. The thin film semiconductor device according to any one of claims 5 to 9, wherein the aluminum oxide constituting the aluminum oxide film has an amorphous structure.
11. The thin film semiconductor device according to any one of claims 1 to 10, wherein the oxide semiconductor layer is made of a metal oxide of indium, gallium, and zinc.
12. The thin film semiconductor device is a thin film transistor,
    The thin film semiconductor device according to any one of claims 1 to 11, wherein the oxide semiconductor layer is a channel layer.
13. An organic EL display device comprising the thin film semiconductor device according to any one of claims 1 to 12.
14. Forming an oxide semiconductor layer;
    Forming an insulating film;
    Forming a hydrogen barrier film having a hydrogen barrier property that suppresses permeation of hydrogen between the oxide semiconductor layer and the insulating film;
    The method for manufacturing a thin film semiconductor device, wherein the insulating film contains an amount of hydrogen that can pass through the hydrogen barrier film.

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