JP2016058554A - Thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor having intended characteristics.SOLUTION: A thin film transistor comprises a gate electrode 20, an oxide semiconductor layer 40 composed of an oxide semiconductor containing at least indium and tungsten, and a gate insulation layer 30 disposed between the gate electrode 20 and the oxide semiconductor layer 40. An amount of tungsten oxide added in the oxide semiconductor layer 40 is at least 0.1 wt% to 10 wt% or less, and a band gap of the oxide semiconductor layer 40 is at least 2.3 eV to 3.3 eV or smaller.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a thin film transistor (TFT), and more particularly to a thin film transistor in which a channel layer is an oxide semiconductor layer.

  A thin film transistor is used as a switching element or a driving element in an active matrix type display device such as a liquid crystal display device using liquid crystal or an organic light emitting diode (OLED) display device using organic EL (Electro Luminescence). It has been.

  The channel layer of the thin film transistor has a channel region in which carrier movement is controlled by a voltage applied to the gate electrode. As a material for the channel layer, various semiconductor materials such as amorphous silicon have been studied.

  In recent years, development of an oxide semiconductor TFT using a transparent amorphous oxide semiconductor (TAOS) as a channel layer has been promoted. For example, an oxide semiconductor TFT using TAOS made of a metal oxide (IGZO) of indium (In), gallium (Ga), and zinc (Zn) as a channel layer has been put into practical use.

However, since carrier mobility can only be expected up to 10 cm ² / V · s in IGZO, in recent years, a TAOS material having higher carrier mobility has been studied (Patent Document 1).

JP 2010-251604 A

As a TAOS material with high carrier mobility, for example, an oxide semiconductor in which tungsten oxide (WO ₃ ), silicon oxide (SiO ₂ ), ZnO (zinc oxide), or the like is added to indium oxide (In ₂ O ₃ ) has been proposed. ing.

  However, a thin film transistor using such an oxide semiconductor has a problem that it is difficult to obtain desired characteristics.

  An object of the present disclosure is to provide a thin film transistor having desired characteristics.

  In order to achieve the above object, one embodiment of a thin film transistor is provided between a gate electrode, an oxide semiconductor layer including an oxide semiconductor containing at least indium and tungsten, and the gate electrode and the oxide semiconductor layer. A gate insulating layer, and an addition amount of tungsten oxide in the oxide semiconductor layer is 0.1 wt% or more and 10 wt% or less, and a band gap of the oxide semiconductor layer is 2.3 eV or more. It is 3 eV or less.

  Even when an oxide semiconductor with high mobility is used, a thin film transistor capable of obtaining desired characteristics can be realized.

Sectional drawing of the thin-film transistor which concerns on embodiment Sectional drawing of each process in the manufacturing method of the thin-film transistor which concerns on embodiment FIG. 11 is a graph showing the relationship between the concentration of tungsten oxide and the electron carrier density in the oxide semiconductor layer of the thin film transistor according to the embodiment. FIG. 11 is a graph showing the relationship between the concentration of tungsten oxide and the carrier mobility in the oxide semiconductor layer of the thin film transistor according to the embodiment. FIG. 11 is a graph showing a relationship between a band gap and an electron carrier density in an oxide semiconductor layer of a thin film transistor according to an embodiment FIG. 6 is a graph showing a relationship between a band gap and carrier mobility in an oxide semiconductor layer of a thin film transistor according to an embodiment. FIG. 11 is a graph showing the relationship between the film density and the electron carrier density in the oxide semiconductor layer of the thin film transistor according to the embodiment FIG. 11 is a graph showing the relationship between the film density and the carrier mobility in the oxide semiconductor layer of the thin film transistor according to the embodiment. FIG. 11 is a graph showing the relationship between the impurity concentration of argon and the carrier mobility in the oxide semiconductor layer of the thin film transistor according to the embodiment. FIG. 11 is a graph showing the relationship between the impurity concentration of hydrogen and the electron carrier density in the oxide semiconductor layer of the thin film transistor according to the embodiment. FIG. 11 is a graph showing the relationship between the refractive index @ 633 nm and the electron carrier density in the oxide semiconductor layer of the thin film transistor according to the embodiment. FIG. 11 shows a relationship between a refractive index @ 633 nm and carrier mobility in an oxide semiconductor layer of a thin film transistor according to an embodiment. FIG. 11 is a graph showing a relationship between an extinction coefficient @ 633 nm and an electron carrier density in an oxide semiconductor layer of a thin film transistor according to an embodiment. FIG. 11 is a graph showing a relationship between an X-ray photoelectron intensity ratio due to oxygen deficiency and an electron carrier density in an oxide semiconductor layer of a thin film transistor according to an embodiment. Partially cutaway perspective view of an organic EL display device according to an embodiment FIG. 1 is an electric circuit diagram illustrating a configuration of an example of a pixel circuit in an organic EL display device according to an embodiment. Sectional drawing of the thin-film transistor which concerns on the modification 1 Sectional drawing of the thin-film transistor which concerns on the modification 2.

  Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present disclosure. Accordingly, the numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps (steps), order of steps, and the like shown in the following embodiments are merely examples and are intended to limit the present disclosure. is not. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are described as arbitrary constituent elements.

  Each figure is a schematic diagram and is not necessarily illustrated strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.

(Embodiment)
Hereinafter, a thin film transistor 1 according to an embodiment and a manufacturing method thereof will be described with reference to the drawings.

[Configuration of thin film transistor]
First, the structure of the thin film transistor 1 according to the embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view of a thin film transistor 1 according to an embodiment.

  As shown in FIG. 1, the thin film transistor 1 is an oxide semiconductor TFT having an oxide semiconductor as a channel layer, and includes a substrate 10, a gate electrode 20, a gate insulating layer 30, an oxide semiconductor layer 40, and an insulating layer. The layer 50 includes a source electrode 60S and a drain electrode 60D. The thin film transistor 1 in this embodiment is a channel protection type bottom gate type TFT and adopts a top contact structure.

  Hereinafter, each component of the thin film transistor 1 according to the present embodiment will be described in detail.

  The substrate 10 is an insulating substrate made of an insulating material, for example, a glass substrate made of a glass material such as quartz glass, non-alkali glass, or high heat resistant glass.

  The substrate 10 is not limited to a glass substrate, and may be a resin substrate made of a resin material such as polyethylene, polypropylene, and polyimide. Further, the substrate 10 may be a flexible substrate having sheet-like or film-like flexibility, such as a flexible glass substrate or a flexible resin substrate, instead of a rigid substrate. As the flexible resin substrate, for example, a substrate composed of a single layer or a laminate of film materials such as polyimide, polyethylene terephthalate, and polyethylene naphthalate can be used. An undercoat layer may be formed on the surface of the substrate 10.

  The gate electrode 20 is an electrode having a single layer structure or a multilayer structure of a conductive film made of a conductive material such as metal or an alloy thereof, and is formed in a predetermined shape above the substrate 10. The film thickness of the gate electrode 20 is, for example, 20 nm to 500 nm.

  Examples of the material of the gate electrode 20 include molybdenum, aluminum, copper, tungsten, titanium, manganese, chromium, tantalum, niobium, silver, gold, platinum, palladium, indium, nickel, neodymium, and the like, An alloy of a metal selected from (such as molybdenum tungsten) is used.

  Note that the material of the gate electrode 20 is not limited to these, and conductive metal oxides such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO), polythiophene, A conductive polymer material such as polyacetylene can also be used.

  The gate insulating layer (gate insulating film) 30 is disposed between the gate electrode 20 and the oxide semiconductor layer 40. In the present embodiment, the gate insulating layer 30 is disposed so as to be located above the gate electrode 20. For example, the gate insulating layer 30 is formed so as to cover the gate electrode 20 on the entire surface of the substrate 10 on which the gate electrode 20 is formed. The film thickness of the gate insulating layer 30 is, for example, 50 nm to 500 nm.

  The gate insulating layer 30 is made of a material having electrical insulation, and as an example, a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or a hafnium oxide film, or A laminated film in which a plurality of these films are laminated.

  The oxide semiconductor layer 40 is formed in a predetermined shape on the gate insulating layer 30 above the gate electrode 20. For example, the oxide semiconductor layer 40 is formed in an island shape over the gate insulating layer 30. In this embodiment, the oxide semiconductor layer 40 is a channel layer of the thin film transistor 1. That is, the oxide semiconductor layer 40 is a semiconductor layer including a channel region facing the gate electrode 20 with the gate insulating layer 30 interposed therebetween. The film thickness of the oxide semiconductor layer 40 is, for example, 10 nm to 100 nm.

  The oxide semiconductor layer 40 is made of an oxide semiconductor containing at least indium (In) and tungsten (W). In this embodiment, a transparent amorphous oxide semiconductor (TAOS) is used as a material for the oxide semiconductor layer 40, and indium (In) and tungsten (as a metal element constituting the oxide semiconductor layer 40) are used. In addition to W), zinc (Zn) is contained. That is, the oxide semiconductor layer 40 in this embodiment is an IWZO film made of an oxide semiconductor containing In, W, and Zn (In—W—Zn—O). Note that details of the film physical properties of the oxide semiconductor layer 40 will be described later.

  The insulating layer 50 is disposed on the oxide semiconductor layer 40. Specifically, the insulating layer 50 is formed over the gate insulating layer 30 so as to cover the oxide semiconductor layer 40. The film thickness of the insulating layer 50 is, for example, 50 nm to 500 nm.

  In this embodiment, the insulating layer 50 functions as a protective film (channel protective layer) that protects the channel region of the oxide semiconductor layer 40. Specifically, the insulating layer 50 is an etch stopper that prevents the oxide semiconductor layer 40 from being etched when the source electrode 60S and the drain electrode 60D formed above the oxide semiconductor layer 40 are patterned by etching. Acts as a layer. Accordingly, process damage on the back channel side of the oxide semiconductor layer 40 can be reduced in the bottom-gate TFT. In the present embodiment, the insulating layer 50 is an interlayer insulating layer formed on the entire surface of the substrate 10.

  The insulating layer 50 is made of a material having electrical insulation, and is, for example, a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, or a laminated film thereof.

  The silicon oxide film generates less hydrogen during film formation than the silicon nitride film. Therefore, by using a silicon oxide film as the insulating layer 50, performance degradation of the oxide semiconductor layer 40 due to hydrogen reduction can be suppressed. Further, by forming an aluminum oxide film as the insulating layer 50, hydrogen and oxygen generated in the upper layer can be blocked by the aluminum oxide film. For these reasons, as the insulating layer 50, for example, a laminated film having a three-layer structure of a silicon oxide film, an aluminum oxide film, and a silicon oxide film is preferably used.

  The material of the insulating layer 50 is not limited to the inorganic material as described above, and a material mainly composed of an organic material may be used.

  In addition, an opening (contact hole) is formed in the insulating layer 50 so as to penetrate part of the insulating layer 50. The oxide semiconductor layer 40 is connected to the source electrode 60S and the drain electrode 60D through the opening of the insulating layer 50.

  The source electrode 60 </ b> S and the drain electrode 60 </ b> D are formed in a predetermined shape so as to be at least partially located above the insulating layer 50 and connected to the oxide semiconductor layer 40. Specifically, the source electrode 60 </ b> S and the drain electrode 60 </ b> D are arranged on the insulating layer 50 so as to be spaced apart from each other in the horizontal direction (substrate horizontal direction) with respect to the substrate 10, and on the insulating layer 50. The oxide semiconductor layer 40 is connected to the formed opening. The film thickness of the source electrode 60S and the drain electrode 60D on the insulating layer 50 is, for example, 100 nm to 500 nm.

  The source electrode 60S and the drain electrode 60D are electrodes having a single layer structure or a multilayer structure of a conductive film made of a conductive material or an alloy thereof. As a material of the source electrode 60S and the drain electrode 60D, for example, aluminum, tantalum, molybdenum, tungsten, silver, copper, titanium, chromium, or the like is used. As an example, the source electrode 60S and the drain electrode 60D are electrodes having a three-layer structure in which a molybdenum film (Mo film), a copper film (Cu film), and a copper manganese alloy film (CuMn film) are formed in order from the bottom.

[Thin Film Transistor Manufacturing Method]
Next, a method for manufacturing the thin film transistor 1 according to the embodiment will be described with reference to FIGS. FIG. 2 is a cross-sectional view of each step in the method for manufacturing the thin film transistor 1 according to the embodiment.

  First, as shown in FIG. 2A, a substrate 10 is prepared, and a gate electrode 20 having a predetermined shape is formed above the substrate 10. For example, a metal film is formed on the substrate 10 by a sputtering method, and the metal film is processed using a photolithography method and a wet etching method, whereby the gate electrode 20 having a predetermined shape is formed. Note that an undercoat layer such as a silicon oxide film may be formed on the surface of the substrate 10 before the gate electrode 20 is formed.

  Next, as shown in FIG. 2B, a gate insulating layer 30 is formed on the gate electrode 20. In this embodiment, the gate insulating layer 30 is formed over the entire surface of the substrate 10 so as to cover the gate electrode 20. In the case where an undercoat layer is formed on the surface of the substrate 10, the gate electrode 20 is formed on the undercoat layer.

The gate insulating layer 30 is, for example, a silicon oxide film. In this case, a silicon oxide film can be formed by a plasma CVD (Chemical Vapor Deposition) method using silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as introduction gases.

The gate insulating layer 30 may be a single layer film or a laminated film. For example, as the gate insulating layer 30, a stacked film in which a silicon nitride film and a silicon oxide film are sequentially formed can be used. The silicon nitride film can be formed by plasma CVD using, for example, silane gas (SiH ₄ ), ammonia gas (NH ₃ ), and nitrogen gas (N ₂ ) as the introduction gas.

  Next, as illustrated in FIG. 2C, the oxide semiconductor film 40 a is formed over the substrate 10. Specifically, on the gate insulating layer 30, an oxide semiconductor film 40a (IWZO film) made of TAOS made of an oxide semiconductor containing In, W, and Zn (In—W—Zn—O) is sputtered. To form a film.

Specifically, an oxide semiconductor containing In, W, and Zn (In—W—Zn—O) is used as a sputtering target, and argon (Ar) gas is allowed to flow as an inert gas into the vacuum chamber and react. A gas containing oxygen (O ₂ ) is introduced as a reactive gas, and a voltage having a predetermined power density is applied to the target material. Thus, the oxide semiconductor film 40a made of an IWZO film can be formed on the gate insulating layer 30.

In this case, as the film forming conditions, the amount of oxygen added, that is, the flow rate ratio of argon gas to oxygen gas (O ₂ / (Ar + O ₂ )) may be 5 to 30%, for example. By adjusting this flow ratio, the band gap of the oxide semiconductor film 40a (IWZO film) can be changed. Further, the substrate temperature may be set to room temperature, for example.

Note that the addition amount of tungsten oxide (WO ₃ ) contained in the target material (In—W—Zn—O) is adjusted within a range of 0.1 wt% to 10 wt%. The amount of zinc oxide (ZnO) contained in the target material (In—W—Zn—O) is 0.5 wt% (fixed).

  Next, as illustrated in FIG. 2D, the oxide semiconductor layer 40 having a predetermined shape is formed by processing the oxide semiconductor film 40a into a predetermined shape.

  For example, the oxide semiconductor film 40a can be processed into the oxide semiconductor layer 40 having a predetermined shape by using a photolithography method and a wet etching method. Specifically, first, a resist is formed over the oxide semiconductor film 40a, and the resist is processed so that the resist is left at least at a position facing the gate electrode 20. Then, the oxide semiconductor film 40a in a region where the resist is not formed is removed by etching. Accordingly, the island-shaped oxide semiconductor layer 40 can be formed so as to include a position facing the gate electrode 20.

Note that in the case where the oxide semiconductor film 40a is InWZnO, for example, a chemical solution obtained by mixing phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water may be used as the etching solution. Good.

  Next, as illustrated in FIG. 2E, the insulating layer 50 is formed over the oxide semiconductor layer 40. In this embodiment, the insulating layer 50 is formed over the entire surface of the gate insulating layer 30 so as to cover the oxide semiconductor layer 40.

The insulating layer 50 is, for example, a silicon oxide film. In this case, a silicon oxide film can be formed by plasma CVD using silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as introduction gases.

  Next, a contact hole is formed in the insulating layer 50 so that a part of the oxide semiconductor layer 40 is exposed. In the present embodiment, a part of the second oxide semiconductor layer 42 is exposed by forming a contact hole in the insulating layer 50. Specifically, a part of the insulating layer 50 is removed by etching using a photolithography method and an etching method, whereby contact holes (openings) are formed over the regions that serve as the source contact region and the drain contact region of the oxide semiconductor layer 40. Form.

For example, when the insulating layer 50 is a silicon oxide film, a contact hole can be formed in the silicon oxide film by a dry etching method using a reactive ion etching (RIE) method. In this case, for example, carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ) can be used as the etching gas.

  Next, as illustrated in FIG. 2F, a source electrode 60S and a drain electrode 60D connected to the oxide semiconductor layer 40 are formed. For example, the source electrode 60S and the drain electrode 60D having a predetermined shape are formed on the insulating layer 50 so as to fill the contact holes formed in the insulating layer 50.

  In the present embodiment, an electrode having a three-layer structure of a Mo film, a Cu film, and a CuMn film is formed as the source electrode 60S and the drain electrode 60D. In this case, first, a Mo film, a Cu film, and a CuMn film are sequentially formed on the insulating layer 50 by a sputtering method so as to fill the contact hole of the insulating layer 50. Thereafter, the laminated film of the Mo film, the Cu film, and the CuMn film is patterned by a photolithography method and a wet etching method. Thereby, the source electrode 60S and the drain electrode 60D having a predetermined shape can be formed.

In addition, as an etching solution for the laminated film of the Mo film, the Cu film, and the CuMn film, for example, a chemical solution in which hydrogen peroxide water (H ₂ O ₂ ) and an organic acid are mixed can be used.

  As described above, the thin film transistor 1 having the configuration shown in FIG. 1 can be manufactured.

[Characteristics of Thin Film Transistor (Film Properties of Oxide Semiconductor Layer)]
Next, the characteristics of the thin film transistor 1 in this embodiment will be described including the background of obtaining one embodiment of the present disclosure.

  In a semiconductor having a strong covalent bond such as silicon, an sp3 hybrid orbit having a structure having a strong spatial directivity is a carrier conduction path. For this reason, in the case of an amorphous state in which the structure is distorted, the conduction path is interrupted and carrier transport is hindered, resulting in deterioration of carrier mobility. Therefore, in a semiconductor material with strong covalent bonding such as silicon, generally, higher carrier mobility can be obtained in a crystalline state (polycrystalline state or microcrystalline state).

  On the other hand, in an oxide semiconductor based on strong ionic indium oxide or the like, the s orbital of the metal ion serving as a carrier conduction path has a spherically symmetric structure spreading spatially. Therefore, even in the amorphous state where the structure is distorted, the conduction path is not interrupted and carrier transport is not hindered. Therefore, in an oxide semiconductor, relatively high carrier mobility can be obtained both in an amorphous state and in a crystalline state.

  Rather, in the polycrystalline state, the carrier barrier is inhibited by the potential barrier due to the grain boundary and the carrier mobility is deteriorated. Therefore, in the oxide semiconductor, the amorphous state without the grain boundary can obtain higher carrier mobility. Can do.

  Therefore, in order to maintain high carrier mobility in an oxide semiconductor, it is better to maintain an amorphous state without crystallizing the oxide semiconductor.

  By the way, although an In-based oxide semiconductor is used in this embodiment, the temperature at which indium oxide itself crystallizes is about 100 ° C. to 200 ° C., and is a process in a general manufacturing process of an oxide semiconductor TFT. It is as low as 100 ° C. or higher compared to the temperature (300 ° C. to 400 ° C.). For this reason, since an In-based oxide semiconductor is easily crystallized in the manufacturing process of the oxide semiconductor TFT, carrier mobility is deteriorated.

On the other hand, among In-based oxide semiconductors, a thin film transistor using an oxide semiconductor (IGZO film) made of In—Ga—Zn—O has been put into practical use, but the carrier mobility of the IGZO film is 10 cm ² / V.・ You can only expect up to s.

  Under these circumstances, the inventors of the present application have proposed an IWO film, which is a TAOS film in which tungsten (W) is added to indium (In), or indium (In) as a TAOS that can obtain higher carrier mobility than an IGZO film. ) Was focused on an IWZO film which is a TAOS film in which tungsten (W) and zinc (Zn) are added.

  Since the IWO film or the IWZO film is an oxide semiconductor, as described above, the carrier mobility is deteriorated (decreased) when crystallized. Therefore, the crystallization is preferably suppressed to suppress the deterioration of the carrier mobility.

  On the other hand, when an IWO film or an IWZO film is used as a channel layer of a TFT, the IWO film or the IWZO film must have a desired carrier density in order to obtain a desired switching characteristic as the TFT.

Accordingly, the inventors of the present application first focused on the point that the addition of tungsten oxide (WO ₃ ) in the IWO film or IWZO film can suppress the crystallization of the film, and the desired addition amount of tungsten oxide in the IWO film or IWZO film. We studied earnestly.

  As a result of the study, it was found that crystallization cannot be sufficiently suppressed when the amount of tungsten oxide added is less than 0.1 wt%. On the other hand, when the added amount of tungsten oxide exceeds 10 wt%, it has been found that tungsten (W) itself works as a donor and the carrier density is increased, so that desired switching characteristics cannot be obtained as a TFT.

  Therefore, by making the addition amount of tungsten oxide in the IWO film or the IWZO film within the range of 0.1 wt% or more and 10 wt% or less, it is possible to suppress the deterioration of carrier mobility and obtain desired switching characteristics. I understood.

  By the way, since the amorphous IWO film or the IWZO film has a disordered structure, a shallow level is formed in the band gap. For this reason, the optical band gap is smaller than that of a semiconductor in a crystalline state.

Therefore, as described above, if only the amount of tungsten oxide (WO ₃ ) is specified, that is, only the composition of the IWO film or IWZO film is specified, the desired carrier mobility and carrier density are affected by the influence of oxygen deficiency. May not be obtained.

  As a result of studying this point, when the band gap of the IWO film or the IWZO film is less than 2.2 eV, the structural order becomes very bad, and a lot of shallow levels are formed in the band gap. It was found that the carrier density increased due to working as a donor, and the switching characteristics deteriorated. On the other hand, it was found that when the band gap of the IWO film or the IWZO film exceeds 3.2 eV, the carrier mobility is deteriorated because crystallization occurs instead of the amorphous state.

  The technology of the present disclosure has been made on the basis of such knowledge. In a TFT having an oxide semiconductor layer made of an IWO film or an IWZO film as a channel layer, the amount of tungsten oxide added to the IWO film or the IWZO film is set. By setting the band gap of the IWO film or IWZO film to not less than 0.1 wt% and not more than 10 wt% and not less than 2.3 eV and not more than 3.3 eV, the carrier mobility is suppressed and deterioration of the carrier mobility is higher than that of the IGZO film. A thin film transistor capable of obtaining a desired degree of switching characteristics can be realized.

Hereinafter, desired ranges regarding various physical properties of the oxide semiconductor layer 40 (IWZO film) of the thin film transistor 1 according to the embodiment will be described in more detail. In this case, the physical property range that is more advantageous than the IGZO film is defined so that the carrier mobility is 10 cm ² / V · s or more and the carrier density is 1 × 10 ¹⁸ / cm ³ or less.

  Although the following physical property ranges are described for the IWZO film, similar results can be obtained with the IWO film. In addition, the following physical property ranges may be satisfied in at least a portion of the oxide semiconductor layer 40 that serves as a channel region. Furthermore, the electron carrier density and electron mobility of the IWZO film in each figure were calculated by Hall effect measurement.

[Tungsten oxide concentration]
FIG. 3 is a diagram illustrating the relationship between the concentration (addition amount) of tungsten oxide (WO ₃ ) and the electron carrier density in the oxide semiconductor layer (IWZO film) of the thin film transistor according to the embodiment. it is a diagram showing the relationship between concentration (addition amount) carrier mobility (electron mobility) of tungsten oxide in the oxide semiconductor layer (IWZO film) (WO _3).

As shown in FIG. 3, when the added amount of tungsten oxide (WO ₃ ) in the IWZO film exceeds 7 wt%, tungsten itself acts as a donor, and the carrier density increases to exceed 1 × 10 ¹⁸ / cm ^3. As a result, the switching characteristics of the TFT deteriorate.

On the other hand, as shown in FIG. 4, when the added amount of tungsten oxide in the IWZO film is less than 0.5 wt%, crystallization cannot be sufficiently suppressed, and the electron mobility is 10 cm ² / V · s. It will fall below.

  Therefore, the amount of tungsten oxide added to the IWZO film is preferably in the range of 0.5 wt% to 7 wt%.

  Note that the amount of tungsten oxide added to the IWO film or the IWZO film can be measured by, for example, Rutherford Backscattering Spectroscopy (RBS).

[Band gap]
FIG. 5 is a diagram illustrating the relationship between the band gap and the electron carrier density in the oxide semiconductor layer (IWZO film) of the thin film transistor according to the embodiment, and FIG. 6 is the band in the oxide semiconductor layer (IWZO film). It is a figure which shows the relationship between a gap and carrier mobility (electron mobility).

As shown in FIG. 5, when the band gap of the IWZO film is less than 2.67 eV, the structural order becomes very poor, and a large number of shallow levels are formed in the band gap, and this acts as a donor. density is increased, the switching characteristics of the TFT gone beyond the 1 × ¹⁰ 18 / cm ³ is deteriorated.

On the other hand, as shown in FIG. 6, when the band gap of the IWZO film exceeds 3.1 eV, the crystallization occurs instead of the amorphous state, and the electron mobility falls below 10 cm ² / V · s.

  Therefore, the band gap in the IWZO film is preferably in the range of 2.67 eV or more and 3.1 eV or less.

  Note that the band gap in the IWO film or the IWZO film can be measured by, for example, a spectroscopic ellipsometry (SE).

[Film density]
FIG. 7 is a diagram illustrating the relationship between the film density and the electron carrier density in the oxide semiconductor layer (IWZO film) of the thin film transistor according to the embodiment, and FIG. 8 illustrates the film in the oxide semiconductor layer (IWZO film). It is a figure which shows the relationship between a density and carrier mobility (electron mobility).

  In an oxide semiconductor having an amorphous structure, the film density is reduced due to structural disorder, and thus the film density tends to be smaller than that of an oxide semiconductor having a crystalline structure.

As shown in FIG. 7, when the film density of the IWZO film is less than 6.5 g / cm ³ , the structural order becomes very bad, and many defect levels are generated in the band gap due to many lattice defects. Since it acts as a donor, the carrier density rises, exceeds 1 × 10 ¹⁸ / cm ^3, and the switching characteristics as a TFT deteriorate.

On the other hand, as shown in FIG. 8, when the film density of the IWZO film exceeds 7.1 g / cm ³ , crystallization occurs instead of the amorphous state, and therefore the electron mobility falls below 10 cm ² / V · s. End up.

Therefore, the film density of the IWZO film is preferably in the range of 6.5 g / cm ³ or more and 7.1 g / cm ³ or less.

  Note that the film density of the IWO film or the IWZO film can be measured by, for example, an X-ray reflectometry (XRR) method.

[Ar impurity concentration]
FIG. 9 is a diagram illustrating a relationship between the impurity concentration of argon (Ar) and carrier mobility (electron mobility) in the oxide semiconductor layer (IWZO film) of the thin film transistor according to the embodiment.

As shown in FIG. 9, the Ar impurity concentration in the IWZO film is 0.8 at. If the ratio exceeds 50%, defects in the lattice are generated due to disorder in the structural order of the amorphous structure, and this impedes carrier transport, resulting in deterioration of carrier mobility and electron mobility of 10 cm ² / V · will fall below s.

  Therefore, the Ar impurity concentration in the IWZO film is 0.8 at. % Or less.

  In addition, the impurity concentration of Ar in the IWO film or the IWZO film can be measured by, for example, secondary ion mass spectrometry (SIMS) or RBS.

[H impurity concentration]
FIG. 10 is a diagram illustrating a relationship between an impurity concentration of hydrogen (H) and an electron carrier density in the oxide semiconductor layer (IWZO film) of the thin film transistor according to the embodiment.

  When hydrogen is mixed into an oxide semiconductor, a shallow level is formed in the band gap, and this acts as a donor, so that the carrier density increases.

As shown in FIG. 10, when the H impurity concentration in the IWZO film exceeds 1 × 10 ²² cm ³ , a large number of shallow levels are formed, which increases the carrier density because it acts as a donor, If it exceeds 1 × 10 ¹⁸ / cm ³ , the switching characteristics as a TFT deteriorate.

Therefore, the concentration of H impurity contained in the IWZO film is preferably 1 × 10 ²² / cm ³ or less.

  Note that the impurity concentration of H in the IWO film or the IWZO film can be measured by, for example, secondary ion mass spectrometry (SIMS).

[Refractive index]
FIG. 11 is a diagram illustrating a relationship between the refractive index @ 633 nm and the electron carrier density in the oxide semiconductor layer (IWZO film) of the thin film transistor according to the embodiment, and FIG. 12 illustrates the oxide semiconductor layer (IWZO film). It is a figure which shows the relationship between the refractive index @ 633nm and carrier mobility (electron mobility) in FIG.

  In an oxide semiconductor having an amorphous structure, the film density is reduced due to structural disorder, so that the film density is lower than that of an oxide semiconductor having a crystalline structure, and accordingly, the refractive index of the film is also reduced.

As shown in FIG. 11, when the refractive index of the IWZO film is less than 2.013, the structural order is very poor, and a large number of defect levels are generated in the band gap due to many lattice defects, which act as donors. For this reason, the carrier density rises, exceeds 1 × 10 ¹⁸ / cm ^3, and the switching characteristics as a TFT deteriorate.

On the other hand, as shown in FIG. 12, when the refractive index of the IWZO film exceeds 2.057, crystallization occurs instead of the amorphous state, and thus the electron mobility falls below 10 cm ² / V · s.

  Therefore, the refractive index of the IWZO film is preferably in the range of 2.013 or more and 2.057 or less.

  Note that the refractive index of the IWO film or the IWZO film can be measured by, for example, SE.

[Extinction coefficient]
FIG. 13 is a diagram illustrating a relationship between the extinction coefficient @ 633 nm and the electron carrier density in the oxide semiconductor layer (IWZO film) of the thin film transistor according to the embodiment.

  In an oxide semiconductor having an amorphous structure, a large number of defect levels are formed in the band gap due to structural disorder, so that the series coefficient of light increases, and the extinction coefficient increases accordingly.

As shown in FIG. 13, when the extinction coefficient of the IWZO film exceeds 0.037, the structural order becomes very poor, and a large number of defect levels are generated in the band gap due to many lattice defects. As a result, the carrier density rises, exceeds 1 × 10 ¹⁸ / cm ^3, and the switching characteristics of the TFT deteriorate.

  Therefore, the extinction coefficient in the IWZO film is preferably 0.037 or less.

  The extinction coefficient of the IWO film or the IWZO film can be measured by SE, for example.

[X-ray photoelectron intensity ratio due to oxygen deficiency]
FIG. 14 is a diagram illustrating a relationship between an X-ray photoelectron intensity ratio due to oxygen deficiency and an electron carrier density in the oxide semiconductor layer (IWZO film) of the thin film transistor according to the embodiment.

  The X-ray photoelectron intensity ratio caused by oxygen vacancies means that the integrated intensity of the peak caused by oxygen in the oxide semiconductor film is 0I with respect to the 01 s peak in the X-ray photoelectron spectrum of the oxide semiconductor film. When the integrated intensity of the peak due to oxygen deficiency in the inside is 0II, the value is 0II / 0I.

  When there is an oxygen vacancy in the oxide semiconductor film, an oxygen vacancy level is formed in the band gap. When oxygen deficiency is present in the oxide semiconductor film, X-ray photoelectron spectroscopy (XPS) measurement is performed, not only the peak due to oxygen in the oxide semiconductor but also the peak due to oxygen deficiency. Also appears.

At this time, as shown in FIG. 14, when the X-ray photoelectron intensity ratio due to oxygen vacancies in the IWZO film exceeds 0.48, a large number of oxygen vacancies are generated, and this acts as a donor. Rises and exceeds 1 × 10 ¹⁸ / cm ³ , which deteriorates the switching characteristics of the TFT.

  Therefore, the X-ray photoelectron intensity ratio due to oxygen deficiency in the IWZO film is preferably 0.48 or less.

  Note that the X-ray photoelectron intensity ratio due to oxygen deficiency of the IWO film or the IWZO film can be measured by XPS, for example.

[Transmissivity]
In an oxide semiconductor having an amorphous structure, a large number of defect levels are formed in the band gap due to structural disorder, so that the light series coefficient increases, and the transmittance decreases accordingly.

  When the transmittance of the IWZO film is less than 70%, the structural order becomes very poor, and a large number of defect levels are generated in the band gap due to many lattice defects, and this acts as a donor, thereby increasing the carrier density. Switching characteristics as a TFT deteriorate.

  Therefore, the transmittance of the IWZO film is preferably 70% or more.

  In addition, the transmittance | permeability of an IWO film | membrane or an IWZO film | membrane can be measured with an ultraviolet visible near infrared (UV-Vis-NIR) spectrophotometer, for example.

[Surface roughness]
If the underlying film (underlying film) is rough, the roughness tends to be a seed of crystallization starting point during film formation (growth) of the film deposited thereon, and the deposited film is easily crystallized.

  If the average surface roughness (Ra) of the IWZO film is larger than 2 nm, the film is considered to be crystallized.

  Therefore, the average surface roughness of the IWZO film is preferably 2 nm or less.

  The surface roughness of the IWO film or the IWZO film can be measured by, for example, an atomic force microscope (AFM).

[Membrane stress]
When the film stress of the oxide semiconductor film exceeds a certain range, process flow failure due to substrate warpage occurs. In this respect, the film stress of the IWZO film is preferably in the range of −400 to +400 MPa.

  The film stress of the IWO film or the IWZO film can be measured with a film stress measuring device.

(Display device)
Next, an example in which the thin film transistor 1 according to the above embodiment is applied to a display device will be described with reference to FIGS. In this embodiment, an application example to an organic EL display device will be described.

  FIG. 15 is a partially cutaway perspective view of the organic EL display device according to the embodiment. The above-described thin film transistor 1 can be used as a switching element or a driving element of an active matrix substrate in an organic EL display device.

  As shown in FIG. 15, the organic EL display device 100 includes a TFT substrate (TFT array substrate) 110 on which a plurality of thin film transistors are arranged, an anode 131 as a lower electrode (reflection electrode), and an EL layer (light emitting layer) 132. And a laminated structure with an organic EL element (light emitting part) 130 composed of a cathode 133 which is an upper electrode (transparent electrode).

  The thin film transistor 1 in the above embodiment is used for the TFT substrate 110 in this embodiment. A plurality of pixels 120 are arranged in a matrix on the TFT substrate 110, and each pixel 120 is provided with a pixel circuit.

  The organic EL element 130 is formed corresponding to each of the plurality of pixels 120, and the light emission of each organic EL element 130 is controlled by a pixel circuit provided in each pixel 120. The organic EL element 130 is formed on an interlayer insulating layer (planarization film) formed so as to cover a plurality of thin film transistors.

  The organic EL element 130 has a configuration in which an EL layer 132 is disposed between the anode 131 and the cathode 133. A hole transport layer is further laminated between the anode 131 and the EL layer 132, and an electron transport layer is further laminated between the EL layer 132 and the cathode 133. Note that another functional layer may be provided between the anode 131 and the cathode 133. The functional layer formed between the anode 131 and the cathode 133 including the EL layer 132 is an organic layer made of an organic material.

  Each pixel 120 is driven and controlled by a respective pixel circuit. The TFT substrate 110 includes a plurality of gate wirings (scanning lines) 140 arranged along the row direction of the pixels 120 and a plurality of gate wirings 140 arranged along the column direction of the pixels 120 so as to intersect the gate wiring 140. Source wiring (signal wiring) 150 and a plurality of power supply wirings (not shown in FIG. 12) arranged in parallel with the source wiring 150 are formed. Each pixel 120 is partitioned by, for example, an orthogonal gate wiring 140 and a source wiring 150.

  The gate wiring 140 is connected to the gate electrode of the first thin film transistor that operates as a switching element included in each pixel circuit for each row. The source wiring 150 is connected to the source electrode of the first thin film transistor for each column. The power supply wiring is connected to the drain electrode of the second thin film transistor that operates as a driving element included in each pixel circuit for each column.

  Here, an example of a pixel circuit in the pixel 120 will be described with reference to FIGS. FIG. 16 is an electric circuit diagram showing a configuration of an example of a pixel circuit in the organic EL display device according to the embodiment. Note that the pixel circuit is not limited to the configuration shown in FIG.

  As shown in FIG. 16, the pixel circuit includes a first thin film transistor SwTr that operates as a switching element, a second thin film transistor DrTr that operates as a driving element, and a capacitor C that stores data to be displayed on the corresponding pixel 120. Composed. In the present embodiment, the first thin film transistor SwTr is a switching transistor for selecting the pixel 120, and the second thin film transistor DrTr is a drive transistor for driving the organic EL element 130.

  The first thin film transistor SwTr includes a gate electrode G1 connected to the gate line 140, a source electrode S1 connected to the source line 150, a drain electrode D1 connected to the capacitor C and the gate electrode G2 of the second thin film transistor DrTr, An oxide semiconductor layer (not shown). In the first thin film transistor SwTr, when a predetermined voltage is applied to the connected gate line 140 and source line 150, the voltage applied to the source line 150 is stored in the capacitor C as a data voltage.

  The second thin film transistor DrTr is connected to the drain electrode D1 of the first thin film transistor SwTr and the gate electrode G2 connected to the capacitor C, the drain electrode D2 connected to the power supply wiring 160 and the capacitor C, and the anode 131 of the organic EL element 130. Source electrode S2 and an oxide semiconductor layer (not shown). The second thin film transistor DrTr supplies a current corresponding to the data voltage held by the capacitor C from the power supply wiring 160 to the anode 131 of the organic EL element 130 through the source electrode S2. Thereby, in the organic EL element 130, a drive current flows from the anode 131 to the cathode 133, and the EL layer 132 emits light.

  Note that the organic EL display device 100 having the above configuration employs an active matrix system in which display control is performed for each pixel 120 located at the intersection of the gate wiring 140 and the source wiring 150. Thereby, the corresponding organic EL element 130 selectively emits light by the first thin film transistor SwTr and the second thin film transistor DrTr in each pixel 120, and a desired image is displayed.

  As described above, since the thin film transistor 1 in the above embodiment is used for the TFT substrate 110 in the present embodiment, an organic EL display device excellent in display performance can be realized.

(Modification)
Hereinafter, the thin film transistor according to Modification 1 and Modification 2 will be described.

(Modification 1)
FIG. 17 is a cross-sectional view of the thin film transistor 2 according to the first modification.

  As shown in FIG. 17, the thin film transistor 2 according to this modification is a bottom gate type and channel etch type TFT, and includes a substrate 10, a gate electrode 20, a gate insulating layer 30, and an oxide semiconductor layer. 40, a source electrode 60S and a drain electrode 60D, and an insulating layer 70.

  In the present modification, the source electrode 60 </ b> S and the drain electrode 60 </ b> D are formed on the oxide semiconductor layer 40 and the gate insulating layer 30 so as to cover both ends of the oxide semiconductor layer 40. Specifically, the source electrode 60 </ b> S is formed from the oxide semiconductor layer 40 to the gate insulating layer 30 so as to cover the upper surface and the side surface of one end of the oxide semiconductor layer 40. On the other hand, the drain electrode 60 </ b> D is formed from the oxide semiconductor layer 40 to the gate insulating layer 30 so as to cover the upper surface and the side surface of the other end portion of the oxide semiconductor layer 40.

  The insulating layer 70 is a passivation layer, and is formed on the gate insulating layer 30 so as to cover the oxide semiconductor layer 40, the source electrode 60S, and the drain electrode 60D.

  As described above, in the above-described embodiment, the channel protection type TFT is used. However, a channel etch type TFT may be used as in this modification.

  In this modification, a side contact structure in which both end portions of the oxide semiconductor layer 40 are directly covered with the source electrode 60S and the drain electrode 60D is employed.

  As described above, according to the thin film transistor of this modification, the same effect as the thin film transistor 1 in the above embodiment can be obtained.

(Modification 2)
FIG. 18 is a cross-sectional view of the thin film transistor 3 according to the second modification.

  As shown in FIG. 18, the thin film transistor 3 according to this modification is a top gate type TFT, and includes a substrate 10, a gate electrode 20, a gate insulating layer 30, an oxide semiconductor layer 40, and a source electrode 60S. And a drain electrode 60 </ b> D and an insulating layer 80.

  The oxide semiconductor layer 40 in this modification is formed at a position facing the gate electrode 20 as in the above embodiment, but unlike the above embodiment, it is not on the gate insulating layer 30 but on the substrate 10. Is formed on top.

  As in the embodiment, the gate insulating layer 30 is formed between the gate electrode 20 and the oxide semiconductor layer 40. In this modification, the gate insulating layer 30 is formed on the substrate 10 so as to cover the oxide semiconductor layer 40. It is formed into a film. The gate electrode 20 is formed on the gate insulating layer 30.

  The insulating layer 80 is an interlayer insulating layer, and is formed on the gate insulating layer 30 so as to cover the gate electrode 20.

  In part of the insulating layer 80 and the gate insulating layer 30, contact holes for connecting the oxide semiconductor layer 40 to the source electrode 60S and the drain electrode 60D are formed.

  The source electrode 60S and the drain electrode 60D are formed in a predetermined shape on the insulating layer 80. The source electrode 60S and the drain electrode 60D are connected to the oxide semiconductor layer 40 through contact holes formed in the insulating layer 80 and the gate insulating layer 30.

  As described above, the bottom gate type TFT is used in the above-described embodiment, but a top gate type TFT may be used as in this modification.

  As described above, according to the thin film transistor of this modification, the same effect as the thin film transistor 1 in the above embodiment can be obtained.

(Other variations)
As described above, the thin film transistor and the manufacturing method thereof have been described based on the embodiment and the modification. However, the present disclosure is not limited to the embodiment and the modification.

  For example, the thin film transistors in the above embodiments and modifications have been described as examples applied to an organic EL display device, but the thin film transistors in the above embodiments and modifications are also applied to other display devices such as a liquid crystal display device. You can also.

  In this case, a display device such as an organic EL display device (organic EL panel) or a liquid crystal display device can be used as a flat panel display. For example, the organic EL display device can be used as a display panel of any electronic device such as a television set, a personal computer, or a mobile phone.

  In addition, the form obtained by making various modifications conceived by those skilled in the art with respect to each embodiment and modification, and the components and functions in each embodiment and modification are arbitrarily set within the scope of the present disclosure. A form realized by combination is also included in the present disclosure.

  The technology disclosed herein is useful as a thin film transistor and a method for manufacturing the thin film transistor, and can be widely used in a display device such as an organic EL display device using the thin film transistor, or various other electronic devices using the thin film transistor.

1, 2, 3 Thin film transistor 10 Substrate 20, G1, G2 Gate electrode 30 Gate insulating layer 40 Oxide semiconductor layer 40a Oxide semiconductor film 50, 70, 80 Insulating layer 60S, S1, S2 Source electrode 60D, D1, D2 Drain electrode DESCRIPTION OF SYMBOLS 100 Organic EL display device 110 TFT substrate 120 Pixel 130 Organic EL element 131 Anode 132 EL layer 133 Cathode 140 Gate wiring 150 Source wiring 160 Power supply wiring

Claims (10)

A gate electrode;
An oxide semiconductor layer made of an oxide semiconductor containing at least indium and tungsten;
A gate insulating layer disposed between the gate electrode and the oxide semiconductor layer,
The addition amount of tungsten oxide in the oxide semiconductor layer is 0.1 wt% or more and 10 wt% or less,
The band gap of the oxide semiconductor layer is 2.3 eV or more and 3.3 eV or less. The thin film transistor according to claim 1, wherein the added amount of tungsten oxide is 0.5 wt% or more and 7 wt% or less. The thin film transistor according to claim 1, wherein a band gap of the oxide semiconductor layer is greater than or equal to 2.67 eV and less than or equal to 3.1 eV. 4. The thin film transistor according to claim 1, wherein the oxide semiconductor layer has a film density of 6.5 g / cm ³ or more and 7.1 g / cm ³ or less. The impurity concentration of argon contained in the oxide semiconductor layer is 0.8 at. The thin film transistor according to any one of claims 1 to 4. The thin film transistor according to claim 1, wherein an impurity concentration of hydrogen contained in the oxide semiconductor layer is 1 × 10 ²² / cm ³ or less. The thin film transistor according to claim 1, wherein a refractive index of the oxide semiconductor layer is 2.013 or more and 2.057 or less. The thin film transistor according to claim 1, wherein an extinction coefficient of the oxide semiconductor layer is 0.037 or less. The thin film transistor according to any one of claims 1 to 8, wherein an X-ray photoelectron intensity ratio due to oxygen deficiency in the oxide semiconductor layer is 0.48 or less. The thin film transistor according to claim 1, wherein the oxide semiconductor further contains zinc.

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