CN113161423B - Thin film transistor, manufacturing method of thin film transistor and display panel - Google Patents
Thin film transistor, manufacturing method of thin film transistor and display panel Download PDFInfo
- Publication number
- CN113161423B CN113161423B CN202110452733.9A CN202110452733A CN113161423B CN 113161423 B CN113161423 B CN 113161423B CN 202110452733 A CN202110452733 A CN 202110452733A CN 113161423 B CN113161423 B CN 113161423B
- Authority
- CN
- China
- Prior art keywords
- region
- channel region
- thin film
- film transistor
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical group 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 7
- 239000011787 zinc oxide Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention discloses a thin film transistor, a manufacturing method of the thin film transistor and a display panel. The thin film transistor comprises a substrate; an active layer, an insulating layer, and a gate electrode layer which are sequentially stacked on one side of a substrate; the active layer comprises a channel region, a source region and a drain region which are arranged on two sides of the channel region; the thickness of a first region of the source region, which is adjacent to the channel region, is smaller than that of the channel region; and/or the thickness of the second region of the drain region adjacent to the channel region is smaller than that of the channel region. The technical scheme provided by the embodiment of the invention ensures that the area of the cross section of the first region adjacent to the channel region and the area of the cross section of the second region adjacent to the channel region are smaller, so that the area of a path for ions to diffuse to the channel region is reduced, the effective length of the channel region arranged between the source region and the drain region is longer, the reliability and the stability of the thin film transistor are improved, and the problem that the length of a channel of the thin film transistor is reduced after the ions are injected into the thin film transistor in the prior art is solved.
Description
Technical Field
The embodiment of the invention relates to the technical field of thin film transistors, in particular to a thin film transistor, a manufacturing method of the thin film transistor and a display panel.
Background
With the development of display technology and the improvement of living standard of people, display devices are widely used. In the conventional display device, the thin film transistor is generally used as a switching element or a driving element to control a pixel, and the reliability and stability of the conventional thin film transistor are low.
Disclosure of Invention
The embodiment of the invention provides a thin film transistor, a manufacturing method of the thin film transistor and a display panel, and aims to solve the problem that the existing thin film transistor is low in reliability and stability.
In order to realize the technical problem, the invention adopts the following technical scheme:
in a first aspect, an embodiment of the present invention provides a thin film transistor, including:
a substrate;
an active layer, an insulating layer, and a gate electrode layer which are stacked in this order on one side of a substrate;
the active layer comprises a channel region, a source region and a drain region which are arranged on two sides of the channel region;
the thickness of a first area of the source area, which is adjacent to the channel area, is smaller than that of the channel area; and/or the thickness of the second region of the drain region adjacent to the channel region is smaller than that of the channel region.
Further, the first region includes a first boundary adjacent to the channel region and a second boundary remote from the channel region;
the thickness of the first area gradually increases along the direction from the first boundary to the second boundary;
the second region comprises a third boundary adjacent to the channel region and a fourth boundary far away from the channel region;
the thickness of the second region gradually increases in a direction in which the third boundary points to the fourth boundary.
Further, the first region comprises at least two sub-source regions, and the thickness of the sub-source regions is gradually increased along the direction far away from the channel region;
the second region includes at least two sub-drain regions, and the thickness of the sub-drain regions gradually increases along a direction away from the channel region.
Further, the insulating layer covers only the channel region or the entire active layer.
Further, the thickness of the first region is 40% -80% of the thickness of the channel region;
the thickness of the second region is 40% -80% of the thickness of the channel region.
Further, the first region is a source region;
the second region is a drain region.
Further, the material of the active layer is a metal oxide.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a thin film transistor, including:
providing a substrate;
forming a semiconductor layer on a substrate; wherein the semiconductor layer comprises a source region, a channel region and a drain region; the thickness of a first area of the source area, which is adjacent to the channel area, is smaller than that of the channel area; and/or the thickness of the second region of the drain region adjacent to the channel region is smaller than that of the channel region;
forming an insulating layer on one side of the semiconductor layer far away from the substrate;
forming a gate electrode layer on a side of the insulating layer away from the substrate;
and implanting ions into the semiconductor layer by taking the gate electrode layer as a mask to form an active layer which is provided with a channel region and a source region and a drain region which are arranged at two sides of the channel region.
Further, forming a semiconductor layer on the substrate includes:
forming a semiconductor material layer on a substrate;
forming a photoresist layer on one side of the semiconductor material layer away from the substrate;
patterning the photoresist layer;
and etching the semiconductor material layer to form a semiconductor layer.
In a third aspect, an embodiment of the present invention provides a display panel, including any of the thin film transistors in the first aspect.
According to the thin film transistor provided by the embodiment of the invention, the thickness of the first region adjacent to the channel region and the source region is smaller than that of the channel region; and/or the thickness of the drain region and the second region adjacent to the channel region is smaller than that of the channel region, so that the area of the cross section of the first region adjacent to the channel region and the area of the cross section of the second region adjacent to the channel region are smaller, the area of a path for ions to diffuse to the channel region is reduced, the effective length of the channel region arranged between the source region and the drain region is longer, and the reliability and the stability of the thin film transistor are improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
fig. 6 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;
FIG. 7 is a flow chart of another method for fabricating a TFT according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background art, the existing thin film transistor has the problem of low reliability and stability, and the inventor researches and discovers that the active layer of the existing thin film transistor is generally manufactured by forming a semiconductor layer and then implanting ions into the semiconductor layer to form a source region or a drain region, wherein the region between the source region and the drain region of the active layer is a channel region, and due to the ion diffusion effect, the ions of the source region or the drain region can diffuse into the channel region after being implanted, so that the length of the channel of the thin film transistor is reduced, and the reliability and stability of the thin film transistor are low.
Based on the above technical problem, the present embodiment proposes the following solutions:
fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention. Referring to fig. 1, a thin film transistor provided by an embodiment of the present invention includes a substrate 100; an active layer 200, an insulating layer 300, and a gate electrode layer 400 which are stacked in this order on one side of a substrate 100; the active layer 200 includes a channel region 201 and source and drain regions 202 and 203 disposed at both sides of the channel region 201; thickness d of first region 1 of source region 202 adjacent to channel region 1 Less than the thickness D of the channel region 201; and/or the thickness d of the second region 2 of the drain region 203 adjacent to the channel region 201 2 Less than the thickness D of the channel region 201.
Specifically, the substrate 100 may be transparent glass, the material may be silicon dioxide, the substrate 100 may also be an opaque material or a component of plastic, and the material of the substrate 100 may be selected according to the requirement of the display device. The material of the insulating layer 300 is an insulating material, the insulating layer 300 insulates the active layer 200 and the gate electrode layer 400, the gate electrode layer 400 is a metal layer, and the material of the gate electrode layer 400 may be one or more conductive materials of Ag, mg, al, pt, au, ni, li, ca, mo, ti, cu, and the like. The active layer 200 may be formed by patterning a semiconductor material layer into a semiconductor layer, the material of the semiconductor layer may include polysilicon or zinc oxide material, and may also include metal, and implanting ions into the semiconductor layer to form a source region 202 and a drain region 203 having ions and a channel region 201 between the source region 202 and the drain region 203, and the semiconductor layer may form a doped source region 202 or drain region 203 by low dose implantation, so as to improve mobility of electrons or holes. Alternatively, the semiconductor layer may be formed by implanting an element such as phosphorus, arsenic, or antimony to form the N-type doped active layer 200, so as to further improve the mobility of electrons.
The source region 202 includes a first region 1 adjacent to the channel region 201, and a thickness d of the first region 1 may be set 1 Is smaller than the thickness D of the channel region 201 due to the thickness D of the first region 1 1 The first region 1 is thin, on one hand, the area of the cross section of the first region 1 perpendicular to the substrate direction is small, when the source region 202 is formed by ion implantation, the area of a path for ions to diffuse to the channel region 201 close to one end of the first region 1 is reduced, and the diffusion of the ions to the channel region 201 is reduced, on the other hand, when the source region 202 is formed by ion implantation, the ions implanted into the thin first region 1 partially diffuse to the substrate 100, so that the ions of the first region 1 adjacent to the channel region 201 are few, the diffusion of the ions to the channel region 201 is reduced, the effective length of the channel region 201 is long, and the reliability and stability of the thin film transistor are improved.
The drain region 203 includes a second region 2 adjacent to the channel region 201, and a thickness d of the second region 2 may be set 2 Is smaller than the thickness D of the channel region 201 due to the thickness D of the second region 2 2 The second region 2 is thin, on one hand, the area of the cross section of the second region 2 perpendicular to the substrate direction is small, when the drain region 203 is formed by ion implantation, the area of a path for ions to diffuse to the channel region 201 close to one end of the second region 2 is reduced, and the diffusion of the ions to the channel region 201 is reduced, on the other hand, when the drain region 203 is formed by ion implantation, the ions implanted to the thin second region 2 partially diffuse to the substrate 100, so that the ions of the second region 2 adjacent to the channel region 201 are few, the effective length of the channel region 201 is long, and the reliability and stability of the thin film transistor are improved.
Furthermore, the thickness d of the first region 1 can also be set 1 Is smaller than the thickness D of the channel region 201, and the thickness D of the second region 2 2 The thickness of the thin film transistor is smaller than the thickness D of the channel region 201, so that the area of a cross section, perpendicular to the substrate direction, of a first region 1 adjacent to the channel region 201 and the area of a cross section, perpendicular to the substrate direction, of a second region 2 adjacent to the channel region 201 are both smaller, the area of a path through which ions diffuse to the channel region 201 close to one end of the first region 1 and the channel region 201 close to one end of the second region 2 is reduced, and the diffusion of the ions to the channel region 201 is reduced, and on the other hand, when the source region 202 and the drain region 203 are formed by ion implantation, ions implanted into the thinner first region 1 and the thinner second region 2 partially diffuse onto the substrate 100, so that the ions of the first region 1 and the second region 2 adjacent to the channel region 201 are fewer, the diffusion of the ions to the channel region 201 is reduced, the effective length of the channel region 201 arranged between the source region 202 and the drain region 203 is longer, and the reliability and stability of the thin film transistor are further improved.
In the thin film transistor provided by the embodiment, the thickness of the first region, adjacent to the channel region, of the source region is smaller than that of the channel region; and/or the thickness of the second region adjacent to the channel region of the drain region is smaller than that of the channel region, so that the area of the cross section of the first region adjacent to the channel region and the area of the cross section of the second region adjacent to the channel region are smaller, the area of a path for ions to diffuse to the channel region is reduced, the effective length of the channel region arranged between the source region and the drain region is longer, and the reliability and the stability of the thin film transistor are improved.
Optionally, fig. 2 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 2, a first region 1 of the thin film transistor provided by the embodiment of the invention includes a first boundary 3 adjacent to the channel region 201 and a second boundary 4 far away from the channel region 201, and a thickness d of the first region 1 is along a direction from the first boundary 3 to the second boundary 4 1 Gradually increasing; the second region 2 comprises a third boundary 5 adjacent to the channel region 201 and a fourth boundary 6 remote from the channel region 201, the thickness d of the second region 2 being in a direction from the third boundary 5 to the fourth boundary 6 2 And gradually increased.
In particular, it may be provided that the second boundary is directed along the first boundary 34, thickness d of the first region 1 1 Gradually increasing, on one hand, the area of the cross section of the first region 1 in the first boundary 3, which is in contact with the channel region 201, is smaller, the diffusion of ions to the channel region 201 is reduced, and the effective length of the channel region 201 is ensured to be longer, and on the other hand, the thickness d of the source region 202 in the first region 1 is larger 1 The gradient distribution is adopted, and the transition is uniform, so that the gradient angle at the second boundary 4 of the source region 202 is small, and the subsequent deposition of the insulating layer 300 is facilitated.
Furthermore, it is possible to provide the thickness d of the second area 2 in a direction pointing along the third boundary 5 towards the fourth boundary 6 2 Gradually increasing, on the one hand, the area of the contact section of the second region 2 at the third boundary 5 and the channel region 201 is smaller, the diffusion of ions to the channel region 201 is reduced, and the effective length of the channel region 201 is ensured to be longer, on the other hand, the transition of the source region 202 in the second region 2 is more uniform, so that the slope angle at the fourth boundary 6 of the source region 202 is smaller, the subsequent deposition of the insulating layer 300 is facilitated, the formed insulating layer 300 is flatter, the formation of gaps or the warping of the insulating layer 300 at the second boundary 4 or the fourth boundary 6 is avoided, and the insulating layer 300 is ensured to have a better insulating effect.
Optionally, fig. 3 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention. On the basis of the above embodiments, referring to fig. 3, a first region 1 of a thin film transistor provided by an embodiment of the present invention includes at least two sub-source regions 11, and a thickness d of the sub-source regions 11 along a direction away from a channel region 201 1 Gradually increasing; the second region 2 comprises at least two sub-drain regions 22, the sub-drain regions 22 having a thickness d in a direction away from the channel region 201 2 Gradually increasing.
In particular, the thickness d of sub-source region 11 in a direction away from channel region 201 1 The thickness d of the sub-source region 11 increases in a gradient manner along the direction of the source region 202 pointing to the channel region 201 1 The diffusion of ions to the channel region 201 can be reduced gradually, and the area of the diffusion path of ions to the channel region 201 can be reduced in a gradient manner, thereby preventing the diffusion of ions to the channel region 201. Thickness d of sub-drain region 22 2 The thickness d of the sub-drain region 22 increases in a gradient manner along the direction from the drain region 203 to the channel region 201 2 The diffusion area of the ions diffusing to the channel region 201 can be reduced in a gradient manner, so that the diffusion of the ions to the channel region 201 can be better prevented, and the effective length of the channel region 201 arranged between the source region 202 and the drain region 203 is longer. The active layer 200 may be formed by a Half tone mask (Half tone mask) such that the thickness d of the sub-source region 11 of the first region 1 of the active layer 200 1 There are a plurality of thicknesses d of the sub-drain regions 22 of the second region 2 2 Has multiple types, simple process and easy manufacture.
Optionally, fig. 4 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention. On the basis of the above embodiments, with reference to fig. 3 and 4, the insulating layer 300 of the thin film transistor provided by the embodiment of the present invention covers only the channel region 201 or the entire active layer 200.
Specifically, with continued reference to fig. 3, the insulating layer 300 of the thin film transistor covers the active layer 200, and ions may be implanted into the semiconductor layer through the insulating layer 300 with the gate electrode layer 400 as a mask to form the active layer 200. Referring to fig. 4, the insulating layer 300 of the thin film transistor only covers the channel region 201, and before ion implantation, the gate electrode layer 400 is used as a mask, and the insulating layer 300 is etched by an etching process, such as a dry etching process, so that the insulating layer 300 only covers the channel layer, and then the gate electrode layer 400 is used as a mask to directly implant ions into the semiconductor layer to form the active layer 200, which can improve ion implantation efficiency.
Optionally, with continued reference to fig. 4, the thickness d of the first region 1 1 May be 40% to 80% of the thickness D of the channel region 201; thickness d of the second region 2 2 May be 40% to 80% of the thickness D of the channel region 201.
Specifically, the too thin thicknesses of the first region 1 and the second region 2 may affect the continuity of the active layer 200, and further affect the conduction stability of the thin film transistor, and the too thick thicknesses of the first region 1 and the second region 2 may increase the area of the cross section of the first region 1 and the second region 2 in contact with the channel layer, so that the blocking effect on the diffusion of ions to the channel region 201 is weak, the length of the channel region 201 is insufficient, and the reliability of the thin film transistor may be affectedImproving effect of stability. The thickness d of the first region 1 is set 1 40% -80% of the thickness D of the channel region 201, and the thickness D of the second region 2 2 The thickness of the channel region 201 is 40% -80%, the diffusion path area of the first region 1 and the second region 2 to the channel region 201 can be reduced to a large extent, the effective length of the channel layer 201 is well ensured, the continuity of the active layer 200 is not affected, and the reliability and the stability of the thin film transistor are improved. Alternatively, the thicknesses of the first region 1 and the second region 2 may be set to be the same as needed.
Optionally, fig. 5 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention. On the basis of the above embodiments, referring to fig. 5, the first region 1 of the thin film transistor provided in the embodiment of the present invention may be a source region 202, and the second region 2 may be a drain region 203.
Specifically, by setting thickness D of channel region 201 larger than thickness D of drain region 203 2 The thickness D of the channel layer is greater than the thickness D of the source region 202 1 The contact cross-sectional area of the source region 202 or the drain region 203 and the channel region 201 is smaller, the shortening of the effective length of the channel region 201 caused by ion diffusion is reduced, in addition, the concentration of carriers such as doped ions of the source region 202 or the drain region 203 is more uniform, the process is simple, and the realization is easy.
Alternatively, the material of the active layer may be a metal oxide.
Specifically, the active layer may be, for example, indium Gallium Zinc Oxide (IGZO), IGZO is an amorphous oxide containing indium, gallium, and zinc, and the carrier mobility is 20 to 30 times that of amorphous silicon, so that the charge and discharge rates of the thin film transistor to the pixel electrode can be greatly increased, the response speed of the pixel can be increased, a faster refresh rate can be realized, the line scanning rate of the pixel can be greatly increased due to faster response, and the efficiency is higher.
Optionally, fig. 6 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention. On the basis of the foregoing embodiment, referring to fig. 6, a method for manufacturing a thin film transistor according to an embodiment of the present invention includes:
s101, providing a substrate.
S102, forming a semiconductor layer on a substrate; wherein the semiconductor layer comprises a source region, a channel region and a drain region; the thickness of a first region of the source region, which is adjacent to the channel region, is smaller than that of the channel region; and/or the thickness of the second region of the drain region adjacent to the channel region is less than the thickness of the channel region.
And S103, forming an insulating layer on one side of the semiconductor layer far away from the substrate.
And S104, forming a gate electrode layer on the side, away from the substrate, of the insulating layer.
And S105, implanting ions into the semiconductor layer by taking the gate electrode layer as a mask to form an active layer which is provided with a channel region, and a source region and a drain region which are arranged at two sides of the channel region.
Specifically, the thickness of the first region of the thin film transistor, which is adjacent to the source region and the channel region, manufactured by using the manufacturing method of the thin film transistor provided by the embodiment is smaller than the thickness of the channel region; and/or the thickness of the second region adjacent to the channel region of the drain region is smaller than that of the channel region, so that the area of the cross section of the boundary of the first region adjacent to the channel region and the area of the cross section of the boundary of the second region adjacent to the channel region are smaller, the diffusion strength of ions to the channel region is reduced, the effective length of the channel region arranged between the source region and the drain region is longer, and the reliability and the stability of the thin film transistor can be improved.
Optionally, fig. 7 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention. On the basis of the foregoing embodiment, referring to fig. 7, a method for manufacturing a thin film transistor according to an embodiment of the present invention includes:
s101, providing a substrate.
S201, forming a semiconductor material layer on the substrate.
Specifically, the semiconductor material layer may include a ZnO material such as ZnO, in-ZnO, ga-In-ZnO, or the like. The semiconductor material layer may be an In-Ga-ZnO (IGZO) semiconductor containing a metal (e.g., znO with In and Ga added).
And S202, forming a photoresist layer on one side of the semiconductor material layer away from the substrate.
And S203, patterning the photoresist layer.
In particular, the patterning of the photoresist layer may be achieved by photolithography.
And S204, etching the semiconductor material layer to form a semiconductor layer.
And S103, forming an insulating layer on one side of the semiconductor layer far away from the substrate.
And S104, forming a gate electrode layer on the side, away from the substrate, of the insulating layer.
And S105, implanting ions into the semiconductor layer by taking the gate electrode layer as a mask to form an active layer which is provided with a channel region, and a source region and a drain region which are arranged at two sides of the channel region.
Specifically, the source region and the drain region may be formed by a conductive process, for example, by adjusting an ion concentration of an oxide semiconductor. For example, the source region and the drain region may be formed by increasing the ion concentration of the oxide semiconductor by plasma treatment using, for example, a hydrogen-based gas, a fluorine-based gas, or a combination thereof. The active layer can be formed through a Half tone mask (Half tone mask), so that the thicknesses of the sub-source regions of the first region and the thicknesses of the sub-drain regions of the second region of the active layer are various, the process is simple, and the manufacturing is easy. The first region of the active layer may be made to include at least two sub-source regions, the sub-source regions having thicknesses that gradually increase in a direction away from the channel region; the second region comprises at least two sub-drain regions, and the thicknesses of the sub-drain regions are gradually increased along the direction far away from the channel region.
Optionally, fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention. On the basis of the above embodiments, referring to fig. 8, a display panel 100 provided by an embodiment of the present invention includes the thin film transistor 200 according to any of the above embodiments. The beneficial effects of the thin film transistor provided by the above embodiments are not described herein. The display panel can be used for mobile terminals such as mobile phones, tablet computers and wearable devices.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.
Claims (8)
1. A thin film transistor, comprising:
a substrate;
an active layer, an insulating layer, and a gate electrode layer which are sequentially stacked on one side of the substrate;
the active layer comprises a channel region, a source region and a drain region which are arranged on two sides of the channel region;
the thickness of a first region of the source region adjacent to the channel region is smaller than that of the channel region; and/or the thickness of a second region of the drain region, which is adjacent to the channel region, is smaller than that of the channel region;
the first region comprises a first boundary adjacent to the channel region and a second boundary remote from the channel region;
the thickness of the first area gradually increases along the direction in which the first boundary points to the second boundary;
the second region comprises a third boundary adjacent to the channel region and a fourth boundary distal from the channel region;
the thickness of the second region gradually increases in a direction in which the third boundary points to the fourth boundary.
2. The thin film transistor according to claim 1,
the first region comprises at least two sub-source regions, and the thickness of each sub-source region is gradually increased along the direction far away from the channel region;
the second region comprises at least two sub-drain regions, and the thicknesses of the sub-drain regions are gradually increased along the direction far away from the channel region.
3. The thin film transistor according to claim 1,
the insulating layer covers only the channel region or the entire active layer.
4. The thin film transistor according to claim 1,
the thickness of the first region is 40% -80% of that of the channel region;
the thickness of the second region is 40% -80% of the thickness of the channel region.
5. The thin film transistor according to claim 1,
the material of the active layer is metal oxide.
6. A method for manufacturing a thin film transistor is characterized by comprising the following steps:
providing a substrate;
forming a semiconductor layer on the substrate; wherein the semiconductor layer includes a source region, a channel region, and a drain region; the thickness of a first area of the source region adjacent to the channel region is smaller than that of the channel region; and/or the thickness of a second region of the drain region, which is adjacent to the channel region, is smaller than that of the channel region;
the first region comprises a first boundary adjacent to the channel region and a second boundary remote from the channel region;
the thickness of the first area gradually increases along the direction from the first boundary to the second boundary;
the second region comprises a third boundary adjacent to the channel region and a fourth boundary remote from the channel region;
the thickness of the second area gradually increases along the direction from the third boundary to the fourth boundary;
forming an insulating layer on one side of the semiconductor layer far away from the substrate;
forming a gate electrode layer on a side of the insulating layer away from the substrate;
and implanting ions into the semiconductor layer by taking the gate electrode layer as a mask to form an active layer which is provided with a channel region and a source region and a drain region which are arranged at two sides of the channel region.
7. The method of manufacturing the thin film transistor according to claim 6, wherein the forming a semiconductor layer over the substrate includes:
forming a semiconductor material layer on the substrate;
forming a photoresist layer on one side of the semiconductor material layer far away from the substrate;
patterning the photoresist layer;
and etching the semiconductor material layer to form a semiconductor layer.
8. A display panel comprising the thin film transistor according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110452733.9A CN113161423B (en) | 2021-04-26 | 2021-04-26 | Thin film transistor, manufacturing method of thin film transistor and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110452733.9A CN113161423B (en) | 2021-04-26 | 2021-04-26 | Thin film transistor, manufacturing method of thin film transistor and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113161423A CN113161423A (en) | 2021-07-23 |
| CN113161423B true CN113161423B (en) | 2022-10-28 |
Family
ID=76870745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110452733.9A Active CN113161423B (en) | 2021-04-26 | 2021-04-26 | Thin film transistor, manufacturing method of thin film transistor and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113161423B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102483A (en) * | 1991-10-09 | 1993-04-23 | Sharp Corp | Film transistor and its manufacturing method |
| WO2016038823A1 (en) * | 2014-09-10 | 2016-03-17 | 株式会社Ｊｏｌｅｄ | Thin film transistor and thin film transistor manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4831850B2 (en) * | 1997-07-08 | 2011-12-07 | 株式会社半導体エネルギー研究所 | Method for manufacturing thin film transistor |
-
2021
- 2021-04-26 CN CN202110452733.9A patent/CN113161423B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102483A (en) * | 1991-10-09 | 1993-04-23 | Sharp Corp | Film transistor and its manufacturing method |
| WO2016038823A1 (en) * | 2014-09-10 | 2016-03-17 | 株式会社Ｊｏｌｅｄ | Thin film transistor and thin film transistor manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113161423A (en) | 2021-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2012151443A (en) | Thin film transistor display panel and method for manufacturing the same | |
| CN112397573B (en) | Array substrate, preparation method thereof and display panel | |
| WO2015096298A1 (en) | Thin film transistor, preparation method therefor, array substrate, and display device | |
| JPH09232448A (en) | Thin film transistor and its manufacture | |
| WO2020173187A1 (en) | Thin film transistor and fabrication method therefor, array substrate and display apparatus | |
| JP4995577B2 (en) | Method for manufacturing transistor | |
| CN113140637A (en) | Display device, array substrate, thin film transistor and manufacturing method thereof | |
| CN109119427B (en) | Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate | |
| CN113161423B (en) | Thin film transistor, manufacturing method of thin film transistor and display panel | |
| CN108122991B (en) | Thin film transistor and manufacturing method thereof | |
| US10205026B2 (en) | Thin film transistor having a composite metal gate layer | |
| CN112259553A (en) | Array substrate, preparation method thereof and display panel | |
| CN104347639A (en) | Thin film transistor substrate and manufacturing method thereof | |
| US9076677B2 (en) | Method for fabricating semiconductor device with super junction structure | |
| CN115588696A (en) | Thin film transistor, array substrate and preparation method of thin film transistor | |
| CN114156285B (en) | Array substrate, preparation method thereof and display panel | |
| US20030197207A1 (en) | Method of fabricating CMOS thin film transistor | |
| WO2023015637A1 (en) | Array substrate and manufacturing method therefor, and display apparatus | |
| CN111223877A (en) | Array substrate, manufacturing method of array substrate and display panel | |
| US8426271B1 (en) | Method for manufacturing a gate-control diode semiconductor memory device | |
| CN207517701U (en) | A kind of thin film transistor (TFT) and display pannel | |
| CN111554579A (en) | Switch LDMOS device and manufacturing method thereof | |
| CN106711155B (en) | Array substrate, display panel and display device | |
| CN114530413B (en) | Array substrate and manufacturing method thereof | |
| CN109103103B (en) | Thin film transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |