CN109103103B - Thin film transistor and preparation method thereof - Google Patents
Thin film transistor and preparation method thereof Download PDFInfo
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- CN109103103B CN109103103B CN201810780067.XA CN201810780067A CN109103103B CN 109103103 B CN109103103 B CN 109103103B CN 201810780067 A CN201810780067 A CN 201810780067A CN 109103103 B CN109103103 B CN 109103103B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Abstract
The invention relates to a preparation method of a thin film transistor, which comprises the following steps: sequentially forming a grid electrode and a grid electrode insulating layer positioned on the grid electrode on a substrate; depositing a first hydrogenated amorphous silicon layer on the gate insulating layer at a first rate, wherein the Si-H bond content in the first hydrogenated amorphous silicon layer is 25-97%; and depositing a second hydrogenated amorphous silicon layer on the first hydrogenated amorphous silicon layer at a second rate, wherein the Si-H bond content in the second hydrogenated amorphous silicon layer is 45-99%, the second rate is greater than the first rate, and the thickness of the second hydrogenated amorphous silicon layer is less than that of the first hydrogenated amorphous silicon layer. According to the production method, the first hydrogenated amorphous silicon layer and the second hydrogenated amorphous silicon layer are adopted at the same time, so that the total content of Si-H bonds can be reduced, the production efficiency is guaranteed, the performance is improved, and the productivity can be considered.
Description
Technical Field
The invention relates to the field of display, in particular to a thin film transistor and a preparation method thereof.
Background
With the development of technology in recent years, a thin film transistor display has gradually taken the lead in the display field because of its low power consumption and excellent display quality. In general, a thin film transistor display employs amorphous silicon thin film transistors as switches. The amorphous silicon thin film transistor generally has the performance of large area uniformity, large capacity and high display quality, and is a key device of a large-size active liquid crystal display device.
However, the hydrogenated amorphous silicon layer in the amorphous silicon thin film transistor is unstable, absorbs a large amount of energy in the case of light irradiation, generates a larger number of electron-hole pairs than in the case of non-light irradiation, and causes a shift in threshold voltage, resulting in a failure of the transistor.
Disclosure of Invention
In view of the above, it is necessary to provide a thin film transistor and a method for manufacturing the same, which can solve the problem of instability of a hydrogenated amorphous silicon layer in an amorphous silicon thin film transistor.
A method of fabricating a thin film transistor, the method comprising:
sequentially forming a grid electrode and a grid electrode insulating layer positioned on the grid electrode on a substrate;
depositing a first hydrogenated amorphous silicon layer on the gate insulating layer at a first rate, wherein the Si-H bond content in the first hydrogenated amorphous silicon layer is 25-97%;
and depositing a second hydrogenated amorphous silicon layer on the first hydrogenated amorphous silicon layer at a second rate, wherein the Si-H bond content in the second hydrogenated amorphous silicon layer is 45-99%, the second rate is greater than the first rate, and the thickness of the second hydrogenated amorphous silicon layer is less than that of the first hydrogenated amorphous silicon layer.
In the above method of manufacturing a thin film transistor, the first hydrogenated amorphous silicon layer is deposited at a first rate, and the second hydrogenated amorphous silicon layer is deposited at a second rate less than the first rate. Because the first speed is slow, the first hydrogenated amorphous silicon layer film formed by deposition is compact, the Si-H bond content is low, and the light stability is good. And the second rate is faster, the second hydrogenated amorphous silicon layer film formed by deposition is looser, the Si-H bond content is high, but the deposition rate is fast and the productivity is high. In the embodiment of the application, the thickness of the first hydrogenated amorphous silicon layer is larger than that of the second hydrogenated amorphous silicon layer, so that the total content of Si-H bonds in the hydrogenated amorphous silicon layer is reduced, and meanwhile, the deposition of part of the second hydrogenated amorphous silicon layer can improve the production efficiency, improve the performance and also take into account the productivity.
In one embodiment, the first rate is
The second rate is
In one embodiment, the first hydrogenated amorphous silicon layer has a thickness of
The second hydrogenated amorphous silicon layer has a thickness of
In one embodiment, the method further comprises:
forming a doped amorphous silicon layer, an electrode layer and a photoresist layer on the second hydrogenated amorphous silicon layer in sequence;
patterning the photoresist layer, and etching the electrode layer according to the pattern of the photoresist layer to form a source electrode and a drain electrode, and an opening located between the source electrode and the drain electrode;
etching the doped amorphous silicon layer below the opening, and continuing to etch downwards after the doped amorphous silicon layer is etched through until the total thickness of the second hydrogenated amorphous silicon layer and the first hydrogenated amorphous silicon layer below the opening reaches a target thickness, and forming a channel groove;
and forming a protective layer in the channel groove and on the surface of the electrode layer to form a thin film transistor structure.
In one embodiment, the target thickness is
In one embodiment, the etching the doped amorphous silicon layer under the opening and continuing to etch downward after etching through the doped amorphous silicon layer includes: etching the doped amorphous silicon layer below the opening by using etching gas, and continuously etching downwards after the doped amorphous silicon layer is etched through;
the etching gas comprises a mixed gas of one of SF6, CF4 and C2HF5, Cl2 and He; the gas ratio of one of SF6, CF4 and C2HF5 to Cl2 is 1: 20-1: 50.
In one embodiment, the target thicknesses of the second hydrogenated amorphous silicon layer and the first hydrogenated amorphous silicon layer are inversely related to the etching time.
In one embodiment, before patterning the photoresist layer and etching the electrode layer according to the pattern of the photoresist layer to form a source electrode and a drain electrode, and an opening between the source electrode and the drain electrode, the method further comprises:
and etching two ends of the electrode layer according to the pattern of the photoresist layer to expose two ends of the doped amorphous silicon layer, and continuously etching two ends of the doped amorphous silicon layer, the second hydrogenated amorphous silicon layer and the first hydrogenated amorphous silicon layer.
In one embodiment, the distance from the edge of the projection of the second hydrogenated amorphous silicon layer corresponding to the channel trench on the gate to the edge of the gate is 5um to 10 um.
A thin film transistor prepared according to the foregoing method, the thin film transistor comprising:
a substrate;
a gate on the substrate;
a gate insulating layer on the substrate and covering the gate;
the hydrogenated amorphous silicon layer is positioned on the grid electrode insulating layer and is divided into a channel region and non-channel regions positioned at two sides of the channel region, and the thickness of each non-channel region is larger than that of the channel region; the hydrogenated amorphous silicon layer comprises a first hydrogenated amorphous silicon layer and a second hydrogenated amorphous silicon layer positioned on the first hydrogenated amorphous silicon layer, wherein the Si-H bond content in the first hydrogenated amorphous silicon layer is 25-97%, and the Si-H bond content in the second hydrogenated amorphous silicon layer is 45-99%;
the doped amorphous silicon layer is positioned on the second amorphous silicon layer corresponding to the non-channel region;
the electrode layer is positioned on the doped amorphous silicon layer;
and the protective layer is positioned on the electrode layer and the hydrogenated amorphous silicon layer.
The thin film transistor comprises a first hydrogenated amorphous silicon layer and a second hydrogenated amorphous silicon layer, wherein the thickness of the first hydrogenated amorphous silicon layer is larger than that of the second hydrogenated amorphous silicon layer, and the content of Si-H bonds in the first hydrogenated amorphous silicon layer is lower than that of the second hydrogenated amorphous silicon layer, so that the total content of Si-H bonds in the hydrogenated amorphous silicon layer is reduced, and the stability of the thin film transistor can be improved. Meanwhile, the deposition of part of the second hydrogenated amorphous silicon layer can improve the production efficiency, improve the performance and also consider the productivity.
Drawings
Fig. 1 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure;
FIGS. 2a to 2c are cross-sectional views of a thin film transistor fabricated by the method shown in FIG. 1;
fig. 3 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present application;
FIGS. 4a to 4d are cross-sectional views of a thin film transistor fabricated by the method shown in FIG. 3;
fig. 5 is a top view structural diagram of a thin film transistor according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Referring to fig. 1, an embodiment of the present application provides a method for manufacturing a thin film transistor, including the following steps:
s100: a gate electrode and a gate insulating layer on the gate electrode are sequentially formed on a substrate.
Specifically, referring to fig. 2a, a gate electrode 120 is formed on a substrate 110 through a patterning process. After the gate electrode 120 is formed, a gate insulating layer 130 is formed on the gate electrode 120 by a furnace oxidation or chemical vapor deposition process.
S200: a first hydrogenated amorphous silicon layer is deposited on the gate insulation layer at a first rate.
Referring to fig. 2b, in the present embodiment, a first hydrogenated amorphous silicon layer 141 is deposited on the gate insulating layer 130 by a chemical vapor deposition process at a first rate. Wherein, the first speed is slower, and the deposited first hydrogenated amorphous silicon layer 141 film is denser.
S300: a second hydrogenated amorphous silicon layer is deposited at a second rate on the first hydrogenated amorphous silicon layer. The second rate is greater than the first rate, and the thickness of the second hydrogenated amorphous silicon layer is less than the thickness of the first hydrogenated amorphous silicon layer.
Referring to fig. 2c, in the present embodiment, a second hydrogenated amorphous silicon layer 142 is deposited on the first hydrogenated amorphous silicon layer 141 at a second rate by using a chemical vapor deposition process. Wherein, the second rate is faster, and the deposited second hydrogenated amorphous silicon layer 142 film is relatively loose.
The second rate is greater than the first rate, so the second hydrogenated amorphous silicon layer 142 deposited at the second rate has a lower densification than the first hydrogenated amorphous silicon layer 141 deposited at the first rate. And hydrogenated amorphous silicon mainly includes Si-Si bonds and Si-H bonds. Wherein the bond length of the Si-Si bond is relatively short and the bond length of the Si-H bond is relatively long. The more bonds per unit area of the hydrogenated amorphous silicon layer contain the bond length, the less dense the film. The second hydrogenated amorphous silicon layer 142 includes more Si-H bond content than the first hydrogenated amorphous silicon layer 141. Therefore, the second hydrogenated amorphous silicon layer 142 has lower light stability than the first hydrogenated amorphous silicon layer 141. The thickness of the second hydrogenated amorphous silicon layer 142 is smaller than that of the first hydrogenated amorphous silicon layer 141, which can improve the light stability of the thin film transistor.
In the method for manufacturing a thin film transistor provided in the above embodiment, the first hydrogenated amorphous silicon layer is deposited on the gate insulating layer at a first rate, and the second hydrogenated amorphous silicon layer is deposited on the first hydrogenated amorphous silicon layer at a second rate. The first rate is less than the second rate, so the first hydrogenated amorphous silicon layer has a higher densification than the second hydrogenated amorphous silicon layer. The first hydrogenated amorphous silicon layer has a lower content of Si-H bonds and is more stable to light than the second hydrogenated amorphous silicon layer. In this embodiment, the first hydrogenated amorphous silicon layer has a thicker thickness, and the second hydrogenated amorphous silicon layer having a poorer light stability is reduced by increasing the thickness of the first hydrogenated amorphous silicon layer having a better light stability, so that the light stability of the amorphous silicon thin film transistor can be improved. And the second speed is faster than the first speed, the productivity is high, and the production time is saved. Therefore, the above embodiments can improve the performance of the thin film transistor while maintaining the productivity.
In one embodiment, the Si-H bond content of the first hydrogenated amorphous silicon layer 141 deposited at the first rate is 75% to 97%. The Si-H bond content in the second hydrogenated amorphous silicon layer 142 deposited at the second rate is 80% to 99%. Wherein the first rate is
The second rate is
The first hydrogenated amorphous silicon layer 141 has a thickness of
The second hydrogenated amorphous silicon layer 142 has a thickness of
In the present embodiment, the first hydrogenated amorphous silicon layer 141 and the second hydrogenated amorphous silicon layer 142 together form a hydrogenated amorphous silicon layer of the thin film transistor, which can generate electron-hole pairs to form a current. The first hydrogenated amorphous silicon layer 141 has a small content of Si — H bonds and has higher stability. In this embodiment, the first hydrogenated amorphous silicon layer 141 is thicker than the second hydrogenated amorphous silicon layer 142, which can improve the stability of the thin film transistor. The deposition rate of the second hydrogenated amorphous silicon layer 142 is faster than that of the first hydrogenated amorphous silicon layer 141, which can save production time and improve productivity. Therefore, the method for manufacturing the thin film transistor provided by the embodiment can not only improve the performance, but also give consideration to the productivity.
Referring to fig. 3, in one embodiment, the method for manufacturing a thin film transistor further includes the following steps:
s400: a doped amorphous silicon layer 150, an electrode layer 160 and a photoresist layer 161 are sequentially formed on the second hydrogenated amorphous silicon layer 142.
Referring to fig. 4a, a doped amorphous silicon layer 150 is formed on the second hydrogenated amorphous silicon layer 142 by chemical vapor deposition. An electrode layer 160 is formed on the doped amorphous silicon layer 150 by a sputtering method, and then a photoresist layer 161 is coated on the electrode layer 160. Wherein the photoresist layer 161 is used to define the pattern of the source and drain electrodes and the position of the trench.
The doped amorphous silicon layer 150 may be an n-type amorphous silicon layer or a p-type amorphous silicon layer. The n-type amorphous silicon layer may be doped with high-concentration phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb), or the like, and the P-type amorphous silicon layer may be doped with high-concentration boron (B), gallium (Ga), indium (Zn), or the like. The doping method can be high temperature diffusion or ion implantation.
The electrode layer 160 may form a source and a drain of a transistor, and the electrode layer 160 may be formed on the doped amorphous silicon layer 150 by sputtering. The electrode layer 160 is generally made of a metal material, such as Cr, W, Ti, Ta, Mo, Al, Cu, etc., but the present invention is not limited thereto, and other conductive materials may be used.
S500: the photoresist layer 161 is patterned, and the electrode layer 160 is etched according to the pattern of the photoresist layer 161 to form a source electrode and a drain electrode, and an opening 162 between the source electrode and the drain electrode.
Referring to fig. 4b, in the present embodiment, a half-tone mask method is used to pattern the photoresist layer 161. That is, the photoresist layer 161 is subjected to processes such as half exposure and development according to the pattern of the mask, so that the pattern of the mask is transferred to the photoresist layer 161. The electrode layer 160 is then etched using a wet etching process according to the pattern of the photoresist layer 161, and source and drain electrodes of the thin film transistor and an opening 162 between the source and drain electrodes are formed. The location of the opening 162 defines the location of the trench.
S600: the doped amorphous silicon layer 150 under the opening 162 is etched, and the etching continues until the total thickness of the second hydrogenated amorphous silicon layer 142 and the first hydrogenated amorphous silicon layer 141 under the opening 162 reaches a target thickness after the doped amorphous silicon layer 150 is etched through, and a channel groove 163 is formed.
Referring to fig. 4c, the doped amorphous silicon layer 150 under the opening 142 is etched by a dry etching process to form an ohmic contact layer under the source/drain electrode and expose the surface of the second hydrogenated amorphous silicon layer 142. And continues to be etched downward from the opening 162 by the dry etching process until the total thickness of the second hydrogenated amorphous silicon layer 142 and the first hydrogenated amorphous silicon layer 141 under the opening 162 reaches a target thickness, and a channel groove 163 is formed. In the present embodiment, the first hydrogenated amorphous silicon layer 141 and the second hydrogenated amorphous silicon layer 142 together form a hydrogenated amorphous silicon layer. The hydrogenated amorphous silicon layer corresponding to the channel trench 163 is a channel region. The target thickness is the thickness of the channel region of the hydrogenated amorphous silicon layer. Etching a portion of the hydrogenated amorphous silicon layer can reduce the total content of Si-H bonds in the hydrogenated amorphous silicon layer. When the thickness of the channel region reaches the target thickness, the content of Si-H bonds in the hydrogenated amorphous silicon layer corresponding to the channel region can be reduced to the target value, and the light stability of the thin film transistor can be further improved. In this embodiment, the target thickness is
Specifically, in the present embodiment, an etching gas may be introduced into the reaction chamber to etch the second hydrogenated amorphous silicon layer 142 to form the channel groove 163. The reaction gas may be a mixed gas of Cl2 and He, and at least one of SF6, CF4 and C2HF 5. He is an inert gas, does not participate in the reaction, and can be used for providing a stable reaction environment. In this embodiment, SF6 is mixed with Cl2 and He to etch the channel region of the hydrogenated amorphous silicon layer. Wherein the gas ratio of SF6 to Cl2 is 1: 20-1: 50. In this embodiment, the target thickness of the channel region is controlled by controlling the gas ratio introduced into the reaction chamber, the power of the reaction chamber, the etching time, and the like. The target thicknesses of the second hydrogenated amorphous silicon layer and the first hydrogenated amorphous silicon layer are inversely related to the etching time.
After the etching is completed, the photoresist layer 161 may be cleaned to remove the photoresist layer 161 on the surface of the electrode layer 160.
S700: and forming a protective layer in the channel groove and on the surface of the electrode layer to form a thin film transistor structure.
Referring to fig. 4d, in particular, a protective layer 170 is deposited in the trench 163, on the surface of the electrode layer 160, and on the exposed surfaces of the other layers to isolate water and oxygen and protect the tft. Then, a hole is punched in the protective layer corresponding to the drain electrode, and a conductive medium is deposited to form the basic structure of the thin film transistor.
In the method for manufacturing the thin film transistor adopted in the above embodiment, the channel region of the hydrogenated amorphous silicon layer is partially etched to reduce the content of Si — H bonds in the channel region, thereby improving the light stability of the thin film transistor.
In one embodiment, before the step of patterning the photoresist layer 161 and etching the electrode layer 160 according to the pattern of the photoresist layer 161, the method further comprises: both ends of the electrode layer 160, the doped amorphous silicon layer 150, the second hydrogenated amorphous silicon layer 142, and the first hydrogenated amorphous silicon layer 141 are etched according to the pattern of the photoresist layer 161.
Specifically, both ends of the electrode layer 160 are etched using a wet etching process to expose the surface of the doped amorphous silicon layer 150. Then, the doped amorphous silicon layer 150 is etched by a dry etching process, and after the doped amorphous silicon layer 150 is etched, the doped amorphous silicon layer is continuously etched until the two ends of the second hydrogenated amorphous silicon layer 142 and the first hydrogenated amorphous silicon layer 141 are completely etched from top to bottom. By etching both ends of the second hydrogenated amorphous silicon layer 142 and the first hydrogenated amorphous silicon layer 141, the content of Si — H bonds in the hydrogenated amorphous silicon layer can be reduced, and the light stability of the thin film transistor can be further improved.
In one embodiment, when the gate electrode 120 is fabricated on the substrate 110, a metal layer is first formed on the substrate 110, and then a photoresist is coated on the metal layer and exposed and developed to form a gate electrode pattern. The metal layer is then etched to form the gate electrode 120. As shown in fig. 5, the exposure amount can be reduced to increase the line width d of the gate electrode 120, so as to increase the distance d1 from the edge of the gate electrode 120 to the edge of the channel region 143 of the hydrogenated amorphous silicon layer. Or the etching time may be reduced during the etching, thereby increasing the line width d of the gate electrode 120. In the present embodiment, the distance from the edge of the gate electrode 120 to the edge of the channel region 143 of the hydrogenated amorphous silicon layer may be 5um to 10 um. Wherein the distance is a projection of the channel region 143 onto the plane of the gate 120 to the edge of the gate 120. When the thin film transistor adopting amorphous silicon is applied to a display panel, light is scattered upwards from the bottom surface of the substrate, the distance from the edge of the gate 120 to the edge of the hydrogenated amorphous silicon layer channel region 143 can be increased by increasing the line width d of the gate 120, the influence of illumination on the hydrogenated amorphous silicon layer is further reduced, the light leakage is reduced, and the stability of the thin film transistor is improved.
Another embodiment of the present application provides a thin film transistor 100, as shown in fig. 4d, including: the substrate 110, the gate electrode 120, the gate insulating layer 130, the first hydrogenated amorphous silicon layer 141, the second hydrogenated amorphous silicon layer 142, the doped amorphous silicon layer 150, the electrode layer 160, and the protective layer 170. The substrate 110 may be a flexible substrate or a rigid substrate, and in this embodiment, the substrate 110 is a rigid substrate, such as a glass substrate. The gate electrode 120 is located on the substrate 110. The gate insulating layer 130 is on the gate electrode 120 and covers the substrate 110. In this embodiment, the material of the gate insulating layer 130 may be silicon nitride, silicon oxide, or silicon oxynitride.
The first hydrogenated amorphous silicon layer 141 and the second hydrogenated amorphous silicon layer 142 together form a hydrogenated amorphous silicon layer, which is an active layer of the thin film transistor and can be divided into a channel region and a non-channel region. The channel region corresponds to the upper portion of the gate 120, the non-channel region is located at two sides of the channel region, and the thickness of the non-channel region is greater than that of the channel region. In this embodiment, the thickness of the first hydrogenated amorphous silicon layer 141 is greater than that of the second hydrogenated amorphous silicon layer 142, and the Si-H bond content in the first hydrogenated amorphous silicon layer 141 is less than that in the second hydrogenated amorphous silicon layer 142. Specifically, the Si-H bond content in the first hydrogenated amorphous silicon layer is 25% -97%, and the Si-H bond content in the second hydrogenated amorphous silicon layer is 45% -99%. Si-H bond is weak, easily decomposed under light, and unstable. Therefore, the less Si-H bonds, the better the light stability of the film. In the present embodiment, the first hydrogenated amorphous silicon layer 141 has better light stability than the second hydrogenated amorphous silicon layer 142.
The doped amorphous silicon layer 150 is disposed on the second hydrogenated amorphous silicon layer 142 and above the non-channel region of the hydrogenated amorphous silicon layer 140. The doped amorphous silicon layer 150 is provided with an electrode layer 160, and the electrode layer 160 is a source electrode and a drain electrode of the thin film transistor 100. The electrode layer 160 is provided with a protective layer 170 for protecting the device from water and oxygen.
The thin film transistor of the above embodiment includes the first hydrogenated amorphous silicon layer and the second hydrogenated amorphous silicon layer, and the Si-H bond content of the first hydrogenated amorphous silicon layer is smaller than the Si-H bond content of the second hydrogenated amorphous silicon layer, so that the light stability of the first hydrogenated amorphous silicon layer is better than the light stability of the second hydrogenated amorphous silicon layer. And the thickness of the first hydrogenated amorphous silicon layer is greater than that of the second hydrogenated amorphous silicon layer, so that the first hydrogenated amorphous silicon layer with less Si-H bond content is adopted in more hydrogenated amorphous silicon layers, the total Si-H bond content of the hydrogenated amorphous silicon layers is less, and the light stability is improved. The second hydrogenated amorphous silicon layer is deposited at a high speed, and the production time is saved, so that the first amorphous silicon layer and the second amorphous silicon layer are adopted simultaneously, the performance of the thin film transistor is improved, and the productivity is also considered.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for preparing a thin film transistor is characterized by comprising the following steps:
sequentially forming a grid electrode and a grid electrode insulating layer positioned on the grid electrode on a substrate;
depositing a first hydrogenated amorphous silicon layer on the gate insulating layer at a first rate, wherein the Si-H bond content in the first hydrogenated amorphous silicon layer is 25-97%;
depositing a second hydrogenated amorphous silicon layer on the first hydrogenated amorphous silicon layer at a second rate, wherein the Si-H bond content in the second hydrogenated amorphous silicon layer is 45-99%, the second rate is greater than the first rate, and the thickness of the second hydrogenated amorphous silicon layer is less than that of the first hydrogenated amorphous silicon layer;
wherein the Si-H bond content in the first hydrogenated amorphous silicon layer is less than the Si-H bond content in the second hydrogenated amorphous silicon layer.
2. The method for manufacturing a thin film transistor according to claim 1, wherein the first rate is
The second rate is
3. The method for manufacturing a thin film transistor according to claim 1, wherein the first hydrogenated amorphous silicon layer has a thickness of
The second hydrogenated amorphous silicon layer has a thickness of
4. The method for manufacturing a thin film transistor according to claim 1, further comprising:
forming a doped amorphous silicon layer, an electrode layer and a photoresist layer on the second hydrogenated amorphous silicon layer in sequence;
patterning the photoresist layer, and etching the electrode layer according to the pattern of the photoresist layer to form a source electrode and a drain electrode, and an opening located between the source electrode and the drain electrode;
etching the doped amorphous silicon layer below the opening, and continuing to etch downwards after the doped amorphous silicon layer is etched through until the total thickness of the second hydrogenated amorphous silicon layer and the first hydrogenated amorphous silicon layer below the opening reaches a target thickness, and forming a channel groove;
and forming a protective layer in the channel groove and on the surface of the electrode layer to form a thin film transistor structure.
5. The method for manufacturing a thin film transistor according to claim 4, wherein the target thickness is
6. The method for preparing the thin film transistor according to claim 4, wherein the etching the doped amorphous silicon layer under the opening and continuing to etch downwards after etching through the doped amorphous silicon layer comprises: etching the doped amorphous silicon layer below the opening by using etching gas, and continuously etching downwards after the doped amorphous silicon layer is etched through;
the etching gas comprises a mixed gas of one of SF6, CF4 and C2HF5, Cl2 and He; the gas ratio of one of SF6, CF4 and C2HF5 to Cl2 is 1: 20-1: 50.
7. The method of claim 6, wherein the target thickness of the second hydrogenated amorphous silicon layer and the first hydrogenated amorphous silicon layer is inversely related to the etching time.
8. The method for manufacturing a thin film transistor according to claim 4, wherein the step of patterning the photoresist layer and etching the electrode layer according to the pattern of the photoresist layer to form a source electrode and a drain electrode and before the opening between the source electrode and the drain electrode further comprises the steps of:
and etching two ends of the electrode layer according to the pattern of the photoresist layer to expose two ends of the doped amorphous silicon layer, and continuously etching two ends of the doped amorphous silicon layer, the second hydrogenated amorphous silicon layer and the first hydrogenated amorphous silicon layer.
9. The method of claim 4, wherein the distance from the edge of the projection of the second hydrogenated amorphous silicon layer corresponding to the channel trench on the gate to the edge of the gate is 5-10 um.
10. A thin film transistor prepared according to the method of any one of claims 1-9, the thin film transistor comprising:
a substrate;
a gate on the substrate;
a gate insulating layer on the substrate and covering the gate;
the hydrogenated amorphous silicon layer is positioned on the grid electrode insulating layer and is divided into a channel region and non-channel regions positioned at two sides of the channel region, and the thickness of each non-channel region is larger than that of the channel region; the hydrogenated amorphous silicon layer comprises a first hydrogenated amorphous silicon layer and a second hydrogenated amorphous silicon layer positioned on the first hydrogenated amorphous silicon layer, wherein the Si-H bond content in the first hydrogenated amorphous silicon layer is 25-97%, and the Si-H bond content in the second hydrogenated amorphous silicon layer is 45-99%;
the doped amorphous silicon layer is positioned on the second hydrogenated amorphous silicon layer corresponding to the non-channel region;
the electrode layer is positioned on the doped amorphous silicon layer;
and the protective layer is positioned on the electrode layer and the hydrogenated amorphous silicon layer.
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| CN102007597A (en) * | 2008-04-17 | 2011-04-06 | 应用材料股份有限公司 | Low temperature thin film transistor process, device property, and device stability improvement |
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