KR100900125B1 - Method for manufacturing vertical transistor - Google Patents

Abstract

Since the vertical transistor according to the present invention forms a pocket doped region by using a thermal oxidation layer as a diffusion barrier between the source and drain junction regions, a short channel effect and a channel leakage current between the source and drain junction regions can be reduced. Can be.

Vertical transistor, thermal oxide, ion implantation, pocket doped region, short channel effect

Description

Method for manufacturing vertical transistor

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a vertical transistor having a vertical channel.

As the degree of integration of semiconductor devices increases, the planar area occupied by electronic devices constituting the semiconductor devices shrinks.

In particular, in the case of a planar transistor, a method of reducing the channel width of the transistor is used to increase the degree of integration of the semiconductor device. Since the channel width is proportional to the drain current, reducing the channel width causes the transistor to transmit current. Reduced ability

Therefore, the planar transistor has a structure that cannot satisfy both the improvement of the characteristics of the transistor and the increase in the degree of integration.

In order to solve this problem, a vertical transistor has been proposed. The vertical transistor is configured by forming a vertical gate on the side of a poly silicon pillar, forming a source under the cylinder, and forming a drain on the top of the cylinder.

Since the channel length of the vertical transistor is not limited by the limitations that can be formed by the current lithographic equipment and the exposure method, the vertical transistor can be adjusted by adjusting the height of the cylinder so that the vertical transistor is larger than the planar transistor. It has a shorter channel length and forms a vertical gate on the side of the cylinder, which has a larger channel width than a planar transistor, thus providing faster switching capability as well as greater power drive capability.

However, such a vertical transistor has a short channel effect due to a short channel length, so that a short channel effect occurs and a channel leakage current occurs.

The present invention provides a vertical transistor forming method capable of reducing short channel effects and channel leakage current between the source and drain electrodes because a pocket doped region is formed using a thermal oxidation layer between the source and drain electrodes. For the purpose of

The vertical transistor forming method according to the present invention

Forming an isolation layer defining an active region on the semiconductor substrate;

Forming a thermal oxide film on an upper surface of the front surface;

Depositing an undopped first polysilicon layer over the thermal oxide film;

Etching the first polysilicon layer and the thermal oxide film using a gate mask to form a vertical gate pattern;

Forming a spacer on sidewalls of the vertical gate pattern using a second undoped second polysilicon layer;

Forming a gate electrode on a sidewall of the vertical gate pattern including the spacer using a doped third polysilicon layer;

Doping the first polysilicon layer and the spacer to form a drain region through an ion implantation process, and doping the active region to form a source region; And

And diffusing ions implanted into the first polysilicon layer and the spacer through the thermal process onto the semiconductor substrate to form a pocket junction region.

The method may further include depositing a low temperature oxide (LTO) on the first polysilicon layer.

Forming the vertical gate pattern

Applying a photoresist film on the first polysilicon layer;

Forming a photoresist pattern by performing an exposure and development process on the photoresist using the gate mask; And

Etching the first polysilicon layer and the thermal oxide film by using the photoresist pattern as an etching mask,

Forming the spacer

Depositing the undoped second poly silicon on top of a front surface; And

Front etching the second polysilicon;

A portion of the active region exposed in the forming of the spacer is etched,

Forming a gate oxide film on an upper surface of the front surface;

And forming a gate contact plug connected to the gate electrode, a drain contact plug connected to the drain region, and a source contact plug connected to the source region,

Removing the gate oxide layer in a region where the drain contact plug and the source contact plug are formed using a contact mask,

In the forming of the pocket junction region, the thermal oxide film may serve as a diffusion barrier.

As described above, the vertical transistor according to the present invention forms a pocket doped region using a thermal oxide layer between the source and drain electrodes, thereby reducing the short channel effect and the channel leakage current between the source and drain electrodes. Can be.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

1A to 1F are cross-sectional views illustrating a method of forming a vertical transistor according to the present invention.

Referring to FIG. 1A, an isolation layer 14 defining an active region 12 is formed on a silicon substrate 10, a thermal oxide layer 16 is formed on an upper surface of the silicon substrate 10, and an undopped polysilicon is formed. The layer 18 is deposited and a Low Temperature Oxide (LTO) 20 is deposited by a Low Temperature Chemical Vapor Deposition (LTCVD) method.

Referring to FIG. 1B, the low-temperature oxide film 20, the polysilicon layer 18, and the thermal oxide film 16 are etched using the photoresist pattern formed through the exposure and development process using the gate mask as an etch mask. Form a pattern.

1C and 1D, an undopped polysilicon layer 22 is deposited on the front surface and then etched to form a spacer 23. At this time, a part of the exposed active region 12 is also etched.

Referring to FIG. 1E, the low temperature oxide layer 20 is removed, a gate oxide layer 24 is formed on the front surface, a doped polysilicon layer is deposited on the gate oxide layer 24, and a photo and etching process is performed. The gate electrode 26 is formed on the sidewall of the vertical gate pattern. In addition, the undoped polysilicon layers 18 and 23 are doped using arsenic As to form the drain junction region 27, and the doped region of the active region 12 is doped. The source junction region 28 is formed.

Referring to FIG. 1F, a pocket junction 30 is formed by diffusing arsenic As injected into the drain junction region 27 into a lower active region through a thermal process. At this time, the thermal oxide film 16 serves as a diffusion barrier.

Then, the source contact plug 32 and the drain junction region electrically connected to the source junction region 28 are removed by removing the gate oxide layer 24 on the drain junction region 27 and the source junction region 28 using a contact mask. A drain contact plug 34 electrically connected to the 27 is formed, respectively. In addition, a gate contact plug 36 electrically connected to the gate electrode 26 is formed.

As described above, the vertical transistor according to the present invention forms a pocket doped region by using a thermal oxide film as a diffusion barrier between the source and drain junction regions, so that a short channel effect and a channel leakage between the source and drain junction regions are formed. Can reduce the current.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A to 1Q are views illustrating a method of forming a vertical transistor according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: semiconductor substrate 12: active region

14: device isolation layer 16: thermal oxide film

18: polysilicon layer 20: low temperature oxide film

22: polysilicon layer 23: spacer

24: gate oxide film 26: polysilicon layer

28: bonding area 30: pocket bonding area

32: source contact plug 34: drain contact plug

36: gate contact plug

Claims (9)

Forming an isolation layer defining an active region on the semiconductor substrate; Forming a thermal oxide film on an upper surface of the front surface; Depositing an undopped first polysilicon layer over the thermal oxide film; Etching the first polysilicon layer and the thermal oxide film using a gate mask to form a vertical gate pattern; Forming a spacer on sidewalls of the vertical gate pattern using a second undoped second polysilicon layer; Forming a gate electrode on a sidewall of the vertical gate pattern including the spacer using a doped third polysilicon layer; Forming a drain region by doping the first polysilicon layer and the spacer through an ion implantation process, and forming a source region by doping the active region; And And forming a pocket junction region by diffusing ions implanted into the first polysilicon layer and the spacer into the semiconductor substrate through a thermal process. The method of claim 1, And depositing a low temperature oxide (LTO) on the first polysilicon layer. The method of claim 1, wherein the forming of the vertical gate pattern is performed. Applying a photoresist film on the first polysilicon layer; Forming a photoresist pattern by performing an exposure and development process on the photoresist using the gate mask; And And etching the first polysilicon layer and the thermal oxide layer by using the photoresist pattern as an etching mask. The method of claim 1, wherein forming the spacer Depositing the undoped second poly silicon on top of a front surface; And And etching the entire surface of the second polysilicon. The method of claim 1, A portion of the active region exposed in the forming of the spacers is etched. The method of claim 1, And forming a gate oxide layer over the entire surface. The method of claim 1, And forming a gate contact plug connected to the gate electrode, a drain contact plug connected to the drain region, and a source contact plug connected to the source region. The method of claim 7, wherein And removing the gate oxide layer in a region where the drain contact plug and the source contact plug are formed by using a contact mask. The method of claim 1, And forming the pocket junction region, wherein the thermal oxide layer serves as a diffusion barrier.

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