JP3941787B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, can reduce fluctuations in characteristics when the source and drain of a MIS transistor used in an SRAM circuit are switched in order to suppress malfunction of an SRAM cell.

  In recent LSI development, with the miniaturization of MIS transistors, a thin film called an offset spacer was formed on the side surface of the gate electrode for the purpose of reducing the capacitance between the gate electrode and the drain region and suppressing the short channel effect. Thereafter, ion implantation is performed through an offset spacer to form extension regions that become part of the source region and the drain region (see, for example, Patent Document 1).

  3 (a) to 3 (c) are cross-sectional views showing a manufacturing process of a conventional semiconductor device. In the figure, the left half shows the SRAM portion formation area AreaS, and the right half shows the logic portion formation area AreaL.

  First, in the step shown in FIG. 3A, a trench type element isolation region 102 is selectively formed in the p type semiconductor substrate 101. Thereafter, the gate insulating film 103 and the SRAM gate electrode 104a are formed on the active region made of the semiconductor substrate 101 in the SRAM portion forming area AreaS surrounded by the element isolation region. At the same time, the gate insulating film 103 and the logic gate electrode 104b are formed on the active region made of the semiconductor substrate 101 in the logic portion forming area AreaL.

  Next, in the step shown in FIG. 3B, offset spacers 105a and 105b are formed on the side surfaces of the SRAM gate electrode 104a and the logic gate electrode 104b. Thereafter, using the SRAM gate electrode 104b and the offset spacer 105a as a mask, an n-type impurity is ion-implanted into the active region of the SRAM portion formation area AreaS to form the SRAM n-type extension region 106a. At the same time, using the logic gate electrode 104b and the offset spacer 105b as a mask, n-type impurities are ion-implanted into the active region of the logic part formation area AreaL to form the logic n-type extension region 106b.

  Next, in the step shown in FIG. 3C, sidewalls 107a and 107b are formed on the side surfaces of the SRAM gate electrode 104a and the logic gate electrode 104b with the offset spacers 105a and 105b interposed therebetween. Thereafter, n-type impurities are ion-implanted using the gate electrodes 104a and 104b, the offset spacers 105a and 105b, and the sidewalls 107a and 107b as masks to form source / drain regions 108a and 108b.

According to this configuration, the amount of overlap between the SRAM gate electrode 104a and the SRAM n-type extension region 106a and the amount of overlap between the logic gate electrode 104b and the logic n-type extension region 106b can be reduced. Therefore, the capacity can be reduced and the short channel effect can be suppressed.
JP 2000-216373 A

  However, the conventional method for manufacturing a semiconductor device as described above has the following problems.

  That is, when forming the n-type extension regions 106a and 106b in the step shown in FIG. 3B, the thickness variation of the offset spacers 105a and 105b in the wafer surface and the variation of the implantation angle in the wafer surface at the time of ion implantation. In addition, due to variations in device setting, there may be a difference in the overlap amount between the n-type extension regions 106a and 106b and the gate electrodes 104a and 104b on one side and the other side of the source / drain regions. For this reason, when the overlap amount is reduced with the miniaturization of the MIS transistor, the amount of current when the one side of the source / drain region is exchanged is different from that of the one side of the source / drain region. Asymmetry in transistor operation when the other side is replaced is a problem. That is, transistor characteristics when one region of the source / drain region is a source and the other region is a drain, and when one region of the source / drain region is a drain and the other region is a source ( Hereinafter, a difference occurs in transistor characteristics of “switching the source and drain”.

  Particularly in an SRAM cell, the asymmetry of the transistor operation when the source and the drain are switched may cause a malfunction at the time of reading, and the amount of change in transistor characteristics when the source and the drain are switched should be minimized. Is a very important problem in a semiconductor device having an SRAM cell.

  An object of the present invention is to provide a semiconductor device including a MIS transistor having symmetry in transistor operation when the source and the drain are switched, a MIS transistor in which the capacitance reduction and the short channel effect are suppressed, and a manufacturing method thereof. It is.

  A semiconductor device according to the present invention includes a first MIS transistor formed in a first region of a first conductivity type semiconductor substrate and a second MIS transistor formed in a second region of the semiconductor substrate. In the semiconductor device, the first MIS transistor includes: a first gate insulating film formed on the first region; a first gate electrode formed on the first gate insulating film; A first extension region of a second conductivity type formed in the first region located below both sides of the first gate electrode, and the second MIS transistor is formed on the second region. A second gate insulating film formed; a second gate electrode formed on the second gate insulating film; and formed in the second region located on both sides of the second gate electrode. Second conductivity type second conductivity And an overlap width in the gate length direction between the first gate electrode and the first extension region is an overlap in the gate length direction between the second gate electrode and the second extension region. It is formed wider than the wrap width.

  In the semiconductor device, the first MIS transistor is used for an SRAM circuit, and the second MIS transistor is used for a logic circuit.

  In the semiconductor device, the first extension region is formed with a shallower diffusion depth than the second extension region.

  In the semiconductor device, the first MIS transistor includes a first offset spacer formed on a side surface of the first gate electrode, and the first MIS transistor formed on a side surface of the first gate electrode. A first sidewall formed by sandwiching one offset spacer, and a first source / drain of the second conductivity type formed in the first region located laterally below the first sidewall. A second offset spacer formed on the side surface of the second gate electrode, and the second MIS transistor formed on the side surface of the second gate electrode. A second side wall formed by sandwiching the offset spacer and a second source of the second conductivity type formed in the second region located on the lower side of the second side wall. Further comprising a rain region.

  The method for manufacturing a semiconductor device of the present invention includes a first MIS transistor formed in a first region of a first conductivity type semiconductor substrate and a second MIS transistor formed in a second region of the semiconductor substrate. A step (a) of forming a first gate insulating film on the first region and forming a second gate insulating film on the second region; (B) forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film; and masking the first gate electrode (C) forming a first extension region by selectively ion-implanting a second conductivity type first impurity only in the first region, and masking the second gate electrode. In the second area, the second area A step (d) of forming a second extension region by ion-implanting a second impurity of the electric type, and an overlap width in the gate length direction of the first gate electrode and the first extension region Is formed wider than the overlap width in the gate length direction between the second gate electrode and the second extension region.

  In the semiconductor device manufacturing method, the first MIS transistor is used in an SRAM circuit, and the second MIS transistor is used in a logic circuit.

  In the method for manufacturing a semiconductor device, the first extension region is formed with a diffusion depth shallower than that of the second extension region.

  In the method for manufacturing a semiconductor device, after the step (c) and before the step (d), offset spacers are formed on the side surfaces of the first gate electrode and the second gate electrode, respectively. In the step (d), the second extension region is formed by ion-implanting the second impurity using the second gate electrode and the offset spacer as a mask.

  Furthermore, in the method for manufacturing a semiconductor device, after the step (d), a first sidewall is formed on the side surface of the first gate electrode, and a second side is formed on the side surface of the second gate electrode. Step (e) of forming a second sidewall, and ion implantation of a third impurity of the second conductivity type into the first region using the first gate electrode and the first sidewall as a mask. The first source / drain region is formed, and the second impurity is ion-implanted into the second region by using the second gate electrode and the second sidewall as a mask. (F) forming a source / drain region.

  In the method for manufacturing a semiconductor device, in the step (c), the first impurity is ion-implanted with an implantation energy of 1 keV or less to form the first extension region.

  In the method for manufacturing a semiconductor device, a tilt angle when the first impurity is ion-implanted is larger than a tilt angle when the second impurity is ion-implanted.

  As described above, according to the present invention, the overlap width in the gate length direction of the first gate electrode and the first extension region in the first MIS transistor is the same as that of the second gate electrode in the second MIS transistor. Since it is formed wider than the overlap width in the gate length direction with the second extension region, the symmetry of the transistor operation when the source and drain of the first MIS transistor are switched can be improved. In addition, the second MIS transistor can suppress the capacitance reduction and the short channel effect. Therefore, by configuring the SRAM circuit using the first MIS transistor, it is possible to suppress a malfunction that occurs when the source and the drain are switched, and by using the second MIS transistor in the logic circuit, the logic circuit can be operated at high speed. Can be achieved.

  In order to improve the symmetry of transistor operation when the source and drain are switched, it is ideal to form the source / drain regions and extension regions formed symmetrically at both sides of the gate electrode. . However, in the current LSI manufacturing process, there is always a slight difference (asymmetric) depending on the wafer surface and the type of apparatus. The object of the present invention is to minimize the difference in transistor characteristics when the source and drain are interchanged, and does not mention only the difference in formation of the source / drain region and the extension region.

  The asymmetry of the transistor operation when the source and the drain are exchanged remarkably occurs when the extension region on either one of the extension regions formed on both sides of the gate electrode is offset with respect to the gate electrode. Therefore, the best method for forming a MIS transistor in which both of the extension regions formed below both sides of the gate electrode are not offset with respect to the gate electrode is proposed below.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described using n-type MIS transistors.

  FIGS. 1A to 1D and FIGS. 2A to 2C are cross-sectional views showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. In the figure, the left half shows the SRAM portion formation area AreaS, and the right half shows the logic portion formation area AreaL.

First, in the step shown in FIG. 1A, after a trench type element isolation region 2 is selectively formed in a p type semiconductor substrate 1, a protective film 3 is formed on the entire surface of the substrate. Thereafter, boron ions, which are p-type impurities, are ion-implanted through the protective film 3 under the implantation conditions of a dose amount of 5 × 10 ¹² / cm ² and an implantation energy of 20 keV, so that the p-type threshold voltage control region 4 is formed. Form.

  Next, after removing the protective film 3 in the step shown in FIG. 1B, thermal oxidation is performed at 800 ° C. for about 5 minutes, for example, to form the SRAM portion forming area AreaS surrounded by the element isolation region 2, and A gate insulating film 5 having a thickness of 2 nm is formed on the active region made of the semiconductor substrate 1 in the logic part forming region AreaL. After that, after forming a polysilicon film on the gate insulating film 5, the polysilicon film is patterned, and the SRAM gate electrode 6a and the logic gate electrode 6b are respectively formed in the SRAM portion forming area AreaS and the logic portion forming area AreaL. Form.

Next, in a step shown in FIG. 1C, a resist 7 having an opening in the SRAM part formation area AreaS and covering the logic part formation area AreaL is formed on the substrate. Thereafter, using resist 7 and SRAM gate electrode 6a as a mask, arsenic ions as n-type impurities are implanted into the active region of SRAM portion formation area AreaS at a dose of 8 × 10 ¹⁴ / cm ² and an implantation energy of 5 keV. The n-type extension region 8 for SRAM which becomes a part of the source region and the drain region is formed by ion implantation. The implantation angle (inclination angle from the direction perpendicular to the substrate surface) at the time of this ion implantation is either 0 ° to 7 ° gyro implantation or 2 ° to 45 ° wafer takeout four rotation implantation. Good.

  Next, after removing the resist 7 in the step shown in FIG. 1D, a thin insulating film for offset spacer such as an HTO film having a thickness of 15 nm is formed on the entire surface of the substrate. Thereafter, the offset spacer insulating film is etched back by anisotropic etching to form offset spacers 9a and 9b on the side surfaces of the SRAM gate electrode 6a and the logic gate electrode 6b.

Next, in the step shown in FIG. 2A, a resist 10 having an opening in the logic part formation area AreaL and covering the SRAM part formation area AreaS is formed on the substrate. Thereafter, using the resist 10, the logic gate electrode 6b, and the offset spacer 9b as a mask, arsenic ions, which are n-type impurities, are implanted into the active region of the logic part formation area AreaL at a dose of 8 × 10 ¹⁴ / cm ² and implantation energy. Ions are implanted under an implantation condition of 5 keV to form a logic n-type extension region 11 that becomes part of the source and drain regions.

  Next, in the step shown in FIG. 2B, after removing the resist 10, a sidewall insulating film such as a silicon nitride film is formed on the entire surface of the substrate. Thereafter, the sidewall insulating film is etched back by anisotropic etching to form sidewalls 12a and 12b on the side surfaces of the SRAM gate electrode 6a and the logic gate electrode 6b with the offset spacers 9a and 9b interposed therebetween. . Thereafter, using the gate electrodes 6a and 6b, the offset spacers 9a and 9b, and the sidewalls 12a and 12b as masks, arsenic ions, phosphorus ions, or both, which are n-type impurities, are ion-implanted to form source / drain regions 13a and 13b. Form.

  Next, in the step shown in FIG. 2C, an interlayer insulating film 14 is formed on the entire surface of the substrate. Thereafter, contact holes reaching the source / drain regions 13a and 13b are formed in the interlayer insulating film 14, and then a metal film such as tungsten is buried in the contact holes to form contact plugs 15.

  Thereafter, wiring layers are sequentially formed on the interlayer insulating film 14 by an ordinary multilayer wiring manufacturing process.

  According to this configuration, the overlap amount between the SRAM gate electrode 6 a and the SRAM n-type extension region 8 is formed larger than the overlap amount between the logic gate electrode 6 b and the logic n-type extension region 11. The Therefore, the SRAM gate electrode 6a and the SRAM n-type extension region 8 can be reliably overlapped on both the source region side and the drain region side. As a result, in the SRAM cell, the amount of change in transistor characteristics when the source and drain are interchanged can be suppressed, so that malfunction due to asymmetry in operation when the source and drain are interchanged can be reduced.

  In this embodiment, the SRAM n-type extension region 8 is formed by ion implantation of n-type impurities using the SRAM gate electrode 6a as a mask before forming the offset spacer 9a. You may form after forming. In this case, ion implantation is performed from all directions at an implantation angle that is surely larger than the implantation angle (tilt angle) of the n-type impurity for forming the logic n-type extension region 11 and overlaps with the SRAM gate electrode 6a. (4 rotation injection) is performed.

  In this embodiment, when the logic n-type extension region 11 is formed, the SRAM portion formation area AreaS is covered with the resist 10 and ion implantation is performed. However, the SRAM portion formation region AreaS is not necessarily covered with the resist. In this case, it is necessary to set the impurity profile of the n-type extension region 8 for SRAM so that the short channel effect of the MIS transistor in the SRAM portion does not deteriorate.

  In the present embodiment, the gate electrodes 6a and 6b have been described using a single-layer structure. However, a stacked structure including a lower electrode made of a polysilicon film and an upper electrode made of a metal film may be used. In this case, there is a concern that the upper electrode is likely to be formed wider in the gate length direction than the lower electrode, and that an SRAM extension region formed by 0 ° implantation tends to be offset. Therefore, in the case of the gate electrode having such a laminated structure, it is important to form the SRAM extension region by angle injection from four directions so as to surely overlap the SRAM gate electrode. .

(Modification of the first embodiment)
In the first embodiment, in the step shown in FIG. 1C, arsenic ions, which are n-type impurities, are dosed into the active region of the SRAM portion formation area AreaS using the resist 7 and the SRAM gate electrode 6a as a mask. Ions are implanted under the conditions of an amount of 8 × 10 ¹⁴ / cm ² and an implantation energy of 5 keV to form an n-type extension region 8 for SRAM that becomes a part of the source region and the drain region.

On the other hand, in this modification, the resist 7 and the SRAM gate electrode 6a are used as a mask, and arsenic ions, which are n-type impurities, are dosed to the active region of the SRAM portion formation area AreaS at a dose of 1 × 10 ¹⁵ / cm. ^2. Ion implantation is performed under an implantation condition of an implantation energy of 0.5 keV to form an n-type extension region 8 for SRAM that becomes a part of the source region and the drain region. Processes other than the above are formed by the same processes as in the first embodiment.

  Thus, by setting the ion implantation energy for forming the n-type extension region 8 for SRAM to 1 keV or less (preferably 0.5 keV or less), the implantation angle is equal to or larger than the tilt angle set by the apparatus. Can be injected. This is because, in ion implantation, if the implantation energy is set to 1 kev or less, the beam diffuses, so that the implantation naturally has an angle.

  According to this manufacturing method, the SRAM n-type extension region 8 is implanted with a low energy of 1 keV or less, so that the SRAM gate electrode 6a and the SRAM n-type extension region 8 can be more reliably overlapped. As a result, in the SRAM cell, the amount of change in transistor characteristics when the source and drain are interchanged can be suppressed, so that malfunction due to asymmetry in operation when the source and drain are interchanged can be reduced. In addition, the diffusion depth can be made shallower than that of the logic n-type extension region 11.

  As described above, the present invention is useful as a semiconductor device capable of suppressing malfunction of SRAM and a manufacturing method thereof.

(A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing process of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Protective film 4 Threshold voltage control region 5 Gate insulating film 6a SRAM gate electrode 6b Logic gate electrode 7 Resist 8 SRAM n-type extension region 9a Offset spacer 9b Offset spacer 10 Resist 11 Logic N-type extension region 12a Side wall 12b Side wall 13a Source / drain region 13b Source / drain region 14 Interlayer insulating film 15 Contact plug

Claims (10)

In a semiconductor device having a first MIS transistor formed in a first region of a first conductivity type semiconductor substrate and a second MIS transistor formed in a second region of the semiconductor substrate,
The first MIS transistor is
A first gate insulating film formed on the first region;
A first gate electrode formed on the first gate insulating film;
A first extension region of a second conductivity type formed in the first region located below both sides of the first gate electrode,
The second MIS transistor is
A second gate insulating film formed on the second region;
A second gate electrode formed on the second gate insulating film;
A second extension region of a second conductivity type formed in the second region located below both sides of the second gate electrode,
The overlap width in the gate length direction between the first gate electrode and the first extension region is wider than the overlap width in the gate length direction between the second gate electrode and the second extension region. Formed ,
The first MIS transistor is used in an SRAM circuit,
The semiconductor device, wherein the second MIS transistor is used in a logic circuit . The semiconductor device according to claim 1 ,
The semiconductor device according to claim 1, wherein the first extension region is formed with a shallower diffusion depth than the second extension region. The semiconductor device according to claim 1 or 2 ,
The first MIS transistor is
A first offset spacer formed on a side surface of the first gate electrode;
A first sidewall formed on both sides of the first offset spacer formed on the side surface of the first gate electrode;
A first source / drain region of a second conductivity type formed in the first region located below the side of the first sidewall;
The second MIS transistor is
A second offset spacer formed on the side surface of the second gate electrode;
A second sidewall formed by sandwiching the second offset spacer formed on the side surface of the second gate electrode;
A semiconductor device, further comprising: a second source / drain region of a second conductivity type formed in the second region located laterally below the second sidewall. In a method for manufacturing a semiconductor device, comprising: a first MIS transistor formed in a first region of a first conductivity type semiconductor substrate; and a second MIS transistor formed in a second region of the semiconductor substrate.
Forming a first gate insulating film on the first region and forming a second gate insulating film on the second region;
(B) forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film;
(C) forming a first extension region by selectively ion-implanting a second conductivity type first impurity only in the first region, using the first gate electrode as a mask;
A step (d) of forming a second extension region by ion-implanting a second impurity of the second conductivity type into the second region using the second gate electrode as a mask;
The overlap width in the gate length direction between the first gate electrode and the first extension region is wider than the overlap width in the gate length direction between the second gate electrode and the second extension region. Formed ,
The first MIS transistor is used in an SRAM circuit,
The method of manufacturing a semiconductor device, wherein the second MIS transistor is used in a logic circuit . In the manufacturing method of the semiconductor device according to claim 4 ,
In the step (c), the first extension region is formed by ion implantation of the first impurity at an implantation energy of 1 keV or less. In a method for manufacturing a semiconductor device, comprising: a first MIS transistor formed in a first region of a first conductivity type semiconductor substrate; and a second MIS transistor formed in a second region of the semiconductor substrate.
Forming a first gate insulating film on the first region and forming a second gate insulating film on the second region;
(B) forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film;
(C) forming a first extension region by selectively ion-implanting a second conductivity type first impurity only in the first region, using the first gate electrode as a mask;
A step (d) of forming a second extension region by ion-implanting a second impurity of the second conductivity type into the second region using the second gate electrode as a mask;
The overlap width in the gate length direction between the first gate electrode and the first extension region is wider than the overlap width in the gate length direction between the second gate electrode and the second extension region. Formed,
In the step (c), the first extension region is formed by ion implantation of the first impurity at an implantation energy of 1 keV or less. In the manufacturing method of the semiconductor device according to any one of claims 4 to 6 ,
The method of manufacturing a semiconductor device, wherein the first extension region is formed with a diffusion depth shallower than that of the second extension region. In the manufacturing method of the semiconductor device of any one of Claims 4-7,
After the step (c) and before the step (d), there is a step of forming offset spacers on the side surfaces of the first gate electrode and the second gate electrode, respectively.
In the step (d), the second extension region is formed by ion-implanting the second impurity using the second gate electrode and the offset spacer as a mask. Method. In the manufacturing method of the semiconductor device according to any one of claims 4 to 8 ,
After the step (d), a step of forming a first sidewall on the side surface of the first gate electrode and a second sidewall on the side surface of the second gate electrode (e) When,
Using the first gate electrode and the first sidewall as a mask, a first impurity of the second conductivity type is ion-implanted into the first region to form a first source / drain region. And (f) forming a second source / drain region by ion-implanting the third impurity into the second region using the second gate electrode and the second sidewall as a mask. And a method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device of any one of Claims 4-9 ,
A manufacturing method of a semiconductor device, wherein a tilt angle when ion-implanting the first impurity is larger than a tilt angle when ion-implanting the second impurity.

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