CN207517701U - A kind of thin film transistor (TFT) and display pannel - Google Patents

A kind of thin film transistor (TFT) and display pannel Download PDF

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Publication number
CN207517701U
CN207517701U CN201721522557.7U CN201721522557U CN207517701U CN 207517701 U CN207517701 U CN 207517701U CN 201721522557 U CN201721522557 U CN 201721522557U CN 207517701 U CN207517701 U CN 207517701U
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electrode
film transistor
region
tft
thin film
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李佳鹏
王文
郭海成
陆磊
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Yan Mao Technology Co Ltd
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Yan Mao Technology Co Ltd
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Abstract

A kind of thin film transistor (TFT), including：Substrate, setting gate stack over the substrate and the active island being made of metal oxide being arranged on the gate stack, covered with electrode on the active island portion subregion, also there is insulating layer between the electrode and the active island, the vertical guide on the boundary on the active island is self-aligned to the vertical guide on the boundary of the total projection area by the electrode and the insulation layer building, region of the active island under electrode covering is respectively source region, drain region, and the region under non-electrode covering is channel region.The utility model further relates to the display pannel with above-mentioned thin film transistor (TFT).Above-mentioned thin film transistor (TFT) and the display pannel with above-mentioned thin film transistor (TFT) had both reduced the mask lithography step prepared needed for transistor, thus greatly reduce manufacturing cost, there is smaller device size again, lower source and drain dead resistance, more excellent ON state, OFF state performance and stronger device reliability more meets the development trend of display pannel.

Description

A kind of thin film transistor (TFT) and display pannel
Technical field
The utility model is related to a kind of metal oxide thin-film transistor structure, in particular for thin in display pannel Film transistor structure.
Background technology
Carry on the back channel etching (back-channel etched:BCE) structure and etching barrier layer (etch-stop:ES) structure It is two kinds of mainstream structures of backgate metal oxide thin-film transistor.In the thin film transistor (TFT) of tradition back of the body channel etching structure, Exposed back of the body channel interface can be damaged, and then influence the performance and stability of device during electrode is etched.Though So such damage can be effectively prevented from by adding one layer of etching barrier layer above active layer channel region, but the quarter added Erosion barrier layer can not only increase by one additional mask lithography step, the manufacturing cost so as to increase device, but also prior It is that etching barrier layer structure considerably increases the length of channel region and required gate electrode length, film crystal can be increased in this way The area of pipe and corresponding parasitic capacitance and then the further promotion for greatly limiting monitor resolution, have deviated from display The trend developed to high-resolution.For conclusion, the advantage for carrying on the back the device architecture of channel etching is the provision of simple technique Flow, relatively low manufacturing cost and smaller device size, but poor device performance and stability；And etching barrier layer Device architecture provides more preferably device performance and stability, but increases the area and parasitic capacitance of device, increases manufacture Cost.For this purpose, metal oxide thin-film transistor manufacturing industry is badly in need of a kind of novel thin-film transistor structure, can meet simultaneously The multiple requestings such as low cost, small size, high-performance.
On the other hand, traditional metal oxide thin-film transistor forms source by depositing metal on intrinsic active layer Drain electrode.Due to unmatched electronic work function, Schottky barrier would generally be formed at the contact interface of electrode and active layer, So as to increase the contact resistance at interface, i.e., higher thin film transistor (TFT) parasitic contact resistance.The metal oxide of eigenstate simultaneously The problem of semiconductor is typically high resistivity, this can bring higher source ohmic leakage to inhibit transistor on-state characteristic.Existing solution Certainly method is usually doped resistivity to reduce source region, drain region by source region to active layer, drain region, but this can sacrifice work Skill stability and greatly increase required manufacturing cost.For example, source and drain areas can be mixed hydrogen ion by plasma treatment It is miscellaneous in source region, drain region so as to reduce the resistivity of source region, drain region, but entire technique and unstable.Other dopants, such as boron And phosphorus, then need prohibitively expensive ion implantation device and additional activation identical to achieve the effect that.For this purpose, thin Film transistor manufacturing is badly in need of a kind of of low cost, simple method of manufacturing process to reduce source in active layer of metal oxide Area, the resistivity in drain region.
Fig. 1 is the sectional view of tradition back of the body channel etching structure backgate thin film transistor (TFT).Wherein, thin film transistor (TFT) includes：Lining Bottom 1a；Gate stack 2a is provided on substrate 1a, gate stack 2a includes patterned gate electrode 21a and is arranged on grid Gate insulating layer 22a on electrode 21a；Active layer is provided on gate stack 2a, utilizes one of independent mask lithography Graphically the active layer forms active island 3a to step；Covered with patterned electrode 4a on active island 3a；Active island 3a with The region that electrode 4a is in contact is respectively formed source region 31a, drain region 33a, and active island 3a is formed with the non-regions being in contact of electrode 4a Channel region 32a；Wherein, source region 31a, drain region 33a are located at the both ends of channel region 32a respectively, and are connected with channel region 32a. In the thin film transistor (TFT) course of work, by the voltage certain to gate electrode application, the carrier number of channel region can be modulated, into And the electric current by channel region is controlled, the final switch for realizing thin film transistor (TFT).The off-state current of thin film transistor (TFT) is largely Upper resistivity and defect concentration depending on channel region, higher resistivity and it is less the defects of band of density carry out lower OFF state electricity Stream and better device performance.The ON state current of thin film transistor (TFT) is limited to source region, the resistivity in drain region, lower source region, leakage Area's resistivity advantageously reduces dead resistance, improves ON state current.For carrying on the back channel etching structure backgate thin film transistor (TFT), ditch Road area 32a can be damaged during graphically etching electrode 4a, generate the defects of a large amount of, can substantially reduce device in this way Performance.The defects of generation, includes conductive-type defect, the resistivity of channel region 32a can be reduced, so as to increase thin film transistor (TFT) Off-state current.On the other hand, the source region 31a of intrinsic high resistivity, drain region 33a can also limit the ON state electricity of thin film transistor (TFT) Stream.
Fig. 2 is the sectional view of conventional etch barrier layer structure backgate thin film transistor (TFT).Wherein, thin film transistor (TFT) includes：Lining Bottom 1b；Gate stack 2b is provided on substrate 1b, gate stack 2b includes patterned gate electrode 21b and is arranged on grid Gate insulating layer 22b on electrode 21b；Active layer is provided on gate stack 2b, utilizes one of independent mask lithography Graphically the active layer forms active island 3b to step；Patterned etching barrier layer 5 is provided on active island 3b；Etching resistance Covered with patterned electrode 4b on barrier 5 and active island 3b；Active island 3b is respectively formed with the electrode 4b regions being in contact Source region 31b, drain region 33b, active island 3b form channel region 32b with the non-regions being in contact of electrode 4b；Wherein, source region 31b, drain region 33b is located at the both ends of channel region 32b respectively, and is connected with channel region 32b.Channel region 32b is protected by etching barrier layer 5 From damage caused by the graphical etching processes of electrode 4b, avoid and introduce defect in channel region 32b.But because etching resistance The introducing of barrier 5, channel region 32b and gate electrode 21b are correspondingly extended, and this greatly increases thin film transistor (TFT)s Area has deviated from the development trend of thin film transistor (TFT) miniaturization.Meanwhile because one additional of mask lithography step is needed to carry out figure Change etching barrier layer 5, manufacturing cost can also increase.Similarly, the intrinsic height in etching barrier layer structure backgate thin film transistor (TFT) Source region 31b, the drain region 33b of resistivity can also inhibit the ON state current of thin film transistor (TFT), influence device performance.
Utility model content
The technical problem to be solved by the utility model is to overcome the deficiency of the above-mentioned prior art, a kind of low source is provided Area, drain region resistivity, and manufacturing cost is cheap, small size, high performance metal oxide thin-film transistor structure.
A kind of thin film transistor (TFT) provided by the utility model, including：
Substrate；
Gate stack is set to the substrate, exhausted including gate electrode and the grid being covered on the gate electrode Edge layer；
Active island, is made of metal oxide, and is formed by graphical active layer, be set to the gate stack it On, it is divided into source region, drain region and channel region；
Electrode, is covered in the active island portion subregion, and the thickness of the electrode is more than the substance containing oxygen element in the electricity Diffusion length in extremely；
Insulating layer, between the electrode and the active island, part of the insulating layer under the non-electrode covering For the first insulating layer, the thickness of first insulating layer is less than the diffusion of the substance containing oxygen element in first insulating layer Length；
The active island is formed by the graphical active layer, positioned at by the electrode and the insulating layer structure Within the total projection area built, and the vertical guide on the boundary on the active island is self-aligned to by the electrode and the insulating layer structure The vertical guide on the boundary of total projection area built；Region of the active island under electrode covering is the source region and institute The drain region stated, the region under the non-electrode covering is the channel region；The source region, the drain region and the channel region phase It connects, and is located at the both ends of the channel region respectively；Joint face, the drain region between the source region and the channel region with Joint face between the channel region, two joint faces are self-aligned to the electrode within the active island projected area The vertical guide on boundary；The resistivity of the channel region is more than the source region, the resistivity in the drain region.
As the preferred mode of above-mentioned transistor arrangement：
The vertical guide on the boundary on the active island is self-aligned to the total projection face by the electrode and the insulation layer building The vertical guide on long-pending boundary, and with 100 times that are smaller than the active island thickness of corresponding vertical guide.
The joint face between joint face, the drain region and the channel region between the source region and the channel region, should Two joint faces are self-aligned to the vertical guide on boundary of the electrode within the active island projected area, and with corresponding vertical 100 times that are smaller than the active island thickness of face.
The channel region and the resistivity ratio in the source region, the drain region are more than 1000 times.
The thickness of first insulating layer is 10 to 3000 nanometers.
The thickness of the electrode is the substance containing oxygen element in the electrode between 2 to 100 times of diffusion length. The thickness of the electrode is 10 to 3000 nanometers.
The utility model additionally provides a kind of display pannel, and including multigroup display module, the display module includes upper The thin film transistor (TFT) stated.
Relative to traditional thin-film transistor structure, the utility model eliminates tradition back of the body channel etching and etching barrier layer Graphical active layer in configuration thin film transistor preparation process forms one of separate mask lithography step on active island.It takes and generation It, after patterned electrodes, active island is by being self-aligned to by total throwing of insulating layer and the source-drain electrode structure of protection raceway groove The boundary of shadow area etches active layer and is formed.The film transistor device structure prepared by the utility model is both as tradition is carved Erosion barrier layer structure equally remains the insulating layer protected to channel region, so as to improve the performance of thin film transistor (TFT) and stabilization Property, and few mask lithography step as back of the body channel etching structure is only used, thus greatly reduce being prepared into for device This.
Another aspect the utility model forms low-resistivity by making annealing treatment in the active island under electrode covering Source region, drain region so that the channel region of backgate modulation more efficiently can be connected to source and drain electricity by the high source region that lead, drain region Pole, so as to reach the device size as back of the body channel etching structure on the basis of etching barrier layer (insulating layer) is possessed. Secondly, make annealing treatment the source region of reduction, the resistivity in drain region can reduce between source-drain electrode and active island parasitic contact electricity Resistance, so as to significantly promote the ON state performance of thin film transistor (TFT).Furthermore also keep the height for even improving channel region due to annealing Resistivity, so as to significantly reduce the off-state current of thin film transistor (TFT).Annealing can also largely eliminate raceway groove The defects of area greatly promotes the reliability of device.The annealing treating process for forming high stem drain region in this way is simple and effective, It is of low cost.
The utility model is by combining the autoregistration formation process on the active island without mask lithography step and with electrode The active island region of covering part forms high stem drain region by making annealing treatment to reduce the resistivity on the active island under electrode covering The method in domain realizes all advantages of back of the body channel etching device architecture and etching barrier layer device architecture.Tradition is being omitted Source and drain doping and independent active island lithography step in semiconductor technology, while substantially reducing manufacturing cost, pass through insulation Layer has protected the channel region in active island, ensure that the performance and stability of thin film transistor (TFT).Therefore, the utility model has both The advantages that low cost, small size, high-performance, high reliability.
Description of the drawings
Fig. 1 is the sectional view of tradition back of the body channel etching structure backgate thin film transistor (TFT).
Fig. 2 is the sectional view of conventional etch barrier layer structure backgate thin film transistor (TFT).
Fig. 3 A-3E are the sectional view for preparing the first embodiment flow of backgate thin-film transistor structure in the utility model.
Fig. 4 A-4D are the vertical view of the first embodiment of backgate thin-film transistor structure and corresponding section in the utility model Sectional view.
Fig. 5 is the sectional view of second of embodiment of backgate thin-film transistor structure in the utility model.
Fig. 6 is the sectional view of the third embodiment of backgate thin-film transistor structure in the utility model.
Fig. 7 is a kind of schematic diagram of display module structure in display panel in the utility model.
Specific embodiment
In the utility model, the projected area is specially the throwing of the vertical direction along embodiment shown in sectional view Shadow area.
The utility model is described in detail with reference to the accompanying drawings and embodiments.It should be appreciated that specific implementation described herein Example for non-limiting example embodiment, and the feature shown in attached drawing be not required it is drawn to scale.Given example is only intended to Be conducive to explain the utility model, be understood not to the restriction to the utility model.
Embodiment one：
It is to prepare the first embodiment flow of thin-film transistor structure in the utility model with reference to Fig. 3 A-3E, Fig. 3 A-3E Sectional view.Thin film transistor (TFT) uses back grid structure in the present embodiment.Wherein, thin film transistor (TFT) includes：Substrate 1；It sets on substrate 1 Gate stack 2 is equipped with, gate stack 2 includes patterned gate electrode 21 and the gate insulator being arranged on gate electrode 21 Layer 22；Active layer 6 is provided on gate stack 2 (with reference to Fig. 3 A).
With reference to Fig. 3 A-3E, substrate 1 includes but not limited to following material：Glass, polymer substrate, flexible material etc..
With reference to Fig. 3 A-3E, active layer 6 includes one or more combinations in following material：Zinc oxide, nitrogen oxidation zinc, Tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc-tin oxide, aluminium oxide tin, tin indium oxide, indium oxide Gallium zinc, indium tin zinc oxide, aluminum oxide indium tin zinc, zinc sulphide, barium titanate, strontium titanates or lithium niobate.
With reference to Fig. 3 A-3E, covered with patterned insulating layer 7 on part active layer 6；On active layer 6 and insulating layer 7 Patterned electrode 4 is provided with, electrode 4 is electrically connected (with reference to Fig. 3 B) with the subregion of active layer 6；Make insulating layer 7 in non-electrical Part under pole 4 covers is the first insulating layer 71, and part of the insulating layer 7 under the covering of electrode 4 is second insulating layer 72；Second absolutely Edge layer 72 is within the projected area of electrode 4, and the first insulating layer 71 is except the projected area of electrode 4 (with reference to Fig. 3 C).
In the utility model, when an insulating layer or the thickness of conductor layer are less than the substance containing oxygen element in the insulating layer Or during diffusion length in conductor layer, the substance containing oxygen element can enter gold in annealing through the insulating layer or conductor layer Belong to oxide active layer, so as to keep, even improve metal oxide resistivity, the insulating layer or conductor layer are oxygen flows at this time Layer；When an insulating layer or the thickness of conductor layer are more than diffusion length of the substance containing oxygen element in the insulating layer or conductor layer When, the insulating layer or conductor layer can stop the substance containing oxygen element, so as to reduce the resistivity of metal oxide, the insulation at this time Layer or conductor layer are impermeable oxygen layer.
The substance containing oxygen element includes：Oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide and above-mentioned The plasma of substance.
With reference to Fig. 3 A-3E, the thickness of the first insulating layer 71 is less than the substance containing oxygen element in the first insulating layer 71 Diffusion length, the substance containing oxygen element in annealing can penetrate the first insulating layer 71 enter active layer 6, thus First insulating layer 71 is oxygen permeable layer.First insulating layer 71 includes one or more combinations in following material：Silica, nitrogen oxygen SiClx, wherein, the ratio of silicon nitride is less than 20% in the silicon oxynitride.The thickness of first insulating layer 71 is received for 10 to 3000 Rice.Preferably, the thickness of the first insulating layer 71 is between 200 nanometers to 500 nanometers.
With reference to Fig. 3 A-3E, the thickness of electrode 4 is more than the diffusion length of the substance containing oxygen element in electrode 4, electrode 4 can stop the substance containing oxygen element, thus electrode 4 is impermeable oxygen layer.Preferably, the thickness of electrode 4 is the oxygen-containing member The substance of element is in electrode 4 between 2 to 100 times of diffusion length.Electrode 4 includes one or more groups in following material It closes：Titanium, molybdenum, aluminium, copper, silver, gold, nickel, tungsten, chromium, hafnium, platinum, iron, titanium-tungsten, molybdenum aluminium alloy, molybdenum-copper or albronze. The thickness of electrode 4 is 10 to 3000 nanometers.Preferably, the thickness of electrode 4 is between 200 nanometers to 500 nanometers.
With reference to Fig. 3 A-3E, the boundary I of the total projection area built by electrode 4 and insulating layer 7 is self-aligned to, is graphically had Active layer 6 is formed in the active island 3 within the total projection area built by electrode 4 and insulating layer 7, the boundary II on active island 3 and by The boundary I autoregistrations for the total projection area that electrode 4 and insulating layer 7 are built (with reference to Fig. 3 D).
With reference to Fig. 3 A-3E, in the utility model, active 3 self aligned formation process of island is without any mask lithography Alignment Process, relative to active in tradition back of the body channel etching structure and etching barrier layer structure backgate thin film transistor (TFT) preparation process The formation on island needs one independent of mask lithography step, manufacturing cost is greatly saved, and remaining protection raceway groove Etching barrier layer (insulating layer) on the basis of have and prepare few mask lithography step as back of the body channel etching structure devices Rapid advantage.Usually all there are certain deviation ranges for this autoregistration.In the utility model, the vertical guide on the boundary on active island The vertical guide on the boundary of the total projection area by electrode and the layer building that insulate is self-aligned to, the deviation of alignment is less than active island thickness 100 times of degree.
With reference to Fig. 3 A-3E, made annealing treatment by continuing, electrode 4 and second insulating layer 72 block the oxygen-containing member jointly The substance of element, the resistivity in region of the active island 3 in the case where electrode 4 and second insulating layer 72 cover are minimized, formation source region 31, Drain region 33.The source region 31 of reduction, the resistivity in drain region 33 are conducive to further reduce between source region 31, drain region 33 and electrode 4 Contact resistance, so as to promote the ON state performance of thin film transistor (TFT).With the characteristic of electrode 4 on the contrary, in annealing, the oxygen-containing member The substance of element can penetrate the first insulating layer 71 and enter active island 3, therefore the electricity in region of the active island 3 under non-electrode 4 coverings Resistance rate is maintained and even improves, and forms channel region 32 (with reference to Fig. 3 E).Therefore, the first insulation can also be penetrated by annealing Layer 71 improves the resistivity of channel regions 32, reduces the defects of channel region 32 density, so as to improve the OFF state characteristic of thin film transistor (TFT), And the first insulating layer 71 can also protect the influence that channel region 32 is brought from 4 etching process of electrode and external environment, Jin Erti The stability and reliability of high thin film transistor (TFT).
In the utility model, the annealing is heated including the use of heat, light, laser, microwave.At the annealing Reason is carried out under oxidizing atmosphere, and for 10 seconds to 10 hours, temperature was between 100 DEG C and 600 DEG C.The oxidizing atmosphere packet It includes：Oxygen, ozone, nitrous oxide, water, carbon dioxide and above-mentioned substance plasma.
With reference to Fig. 3 A-3E, the utility model is self-aligned to electrode 4 within active 3 projected area of island by annealing Boundary III, region of the active island 3 under the covering of electrode 4 be respectively formed source region 31 and drain region 33, the area under non-electrode 4 covering Domain forms channel region 32；Source region 31, drain region 33 are connected with each other with channel region 32 and are located at the both ends of channel region 32 respectively.It is moved back Fire formed joint face IV without any lithography alignment technique, and be self aligned to electrode 4 active 3 projected area of island it Interior boundary III (with reference to Fig. 3 E).It is similarly in existing silicon-based field-effect transistors technique, adulterates source region, the drain region of formation Gate electrode boundary is self aligned to the joint face of channel region.Usually all there are certain deviation ranges for this autoregistration.This In utility model, the joint face between joint face, drain region and channel region between source region and channel region, two joint faces are from right The vertical guide on boundary of the standard in electrode within active island projected area, and it is smaller than active island thickness with corresponding vertical guide 100 times.
Relative to traditional the resistivity of source region, drain region is reduced by way of being doped to source region and drain region, this The resistivity of the resistivity ratio doping gained of source region, drain region in utility model obtained by annealing is lower, and the source under electrode protection Area, the low-resistivity in drain region are more stable.Relative to Traditional dopant mode, the technique of the utility model is simpler, cost is also lower. But the utility model does not limit doping, and one or more of impurity can be mixed in active layer：Hydrogen, nitrogen, fluorine, boron, phosphorus, arsenic, Silicon, indium, aluminium or antimony.This does not interfere the source region of device, channel region and the formation in drain region.Also therefore, the utility model and existing mix General labourer's skill is completely compatible, has high scalability.Contributed in active island by the source region of the low-resistivity formed of annealing, drain region Reduce the length of channel region in etching barrier layer structure so that source region, drain region and the source that the channel region of backgate modulation is led by height Drain electrode is electrically connected, and is the high-resolution development service of display so as to achieve the purpose that reduce film crystal pipe size.
Relative to the preparation method of conventional thin film transistor, annealing is also assured, is even improved in the utility model The high resistivity of channel region, so as to significantly reduce the off-state current of thin film transistor (TFT), far below the 10 of current mainstream-13 Pacify every micron or even be reduced to extremely low 10-18Pacify every micron.Importantly, annealing also largely eliminates raceway groove The defects of area, for example, Lacking oxygen defect, metal interstitial defect etc., these defects are universally present in metal oxide, quilt An important factor for being considered to reduce the Performance And Reliability of thin film transistor (TFT), but it is difficult thorough in traditional device architecture It eliminates on ground.Because effectively eliminating these defects, thin-film transistor structure disclosed in the utility model significantly enhances gold Belong to the performance and long-term reliability of oxide thin film transistor.For example, the metal-oxide film prepared based on the utility model The current on/off ratio of transistor is greatly improved, is even higher than 1011；Threshold voltage shift caused by common echo effect It is suppressed within 0.15V；The shift degradation of generated threshold voltage at any time subtracts when gate electrode applies certain voltage It is small to arrive 0V or so.Secondly, the insulating layer covered above channel region can not only protect channel region completely as etching barrier layer The damage brought from electrode etch, additionally it is possible to influence of the protective film transistor from external environment, enhanced film well The environmental stability of transistor.For example, the threshold voltage caused by 10 hours is preserved under 80 degrees Celsius, 80% relative humidity It the problem of performance degradations such as drift, is substantially improved in the thin film transistor (TFT) prepared based on the utility model.
The vertical view that reference Fig. 4 A-4D, Fig. 4 A are thin-film transistor structure the first embodiment Fig. 3 E in the utility model, Fig. 4 B-D are the sectional view of tangential direction shown in respective top；Specially：Fig. 4 B are the sectional view of the a-a tangent lines of Fig. 4 A, are schemed 4C is the sectional view of the b-b tangent lines of Fig. 4 A, and Fig. 4 D are the sectional view of the c-c tangent lines of Fig. 4 A.
In summary, the utility model possesses plurality of advantages simultaneously compared to conventional thin film transistor structure, including：It is simpler Single manufacturing process, lower manufacturing cost, higher process spread, smaller device size, more preferably device performance can By property and environmental stability.
Embodiment two：
With reference to Fig. 5, Fig. 5 is the sectional view of second of embodiment of thin-film transistor structure in the utility model.The present embodiment Middle thin film transistor (TFT) uses back grid structure.Wherein, thin film transistor (TFT) includes：Substrate 1；It is provided with gate stack 2 on substrate 1, Gate stack 2 includes patterned gate electrode 21 and the gate insulating layer 22 being arranged on gate electrode 21；In the grid Active layer is provided on the lamination of pole；It is partially covered with patterned insulating layer 8 on the active layer；In the active layer and Patterned electrode 4 is provided on insulating layer 8, electrode 4 is electrically connected with the subregion of the active layer；Autoregistration is by electrode 4 And the boundary I of total projection area that insulating layer 7 is built, the graphical active layer are formed in what is built by electrode 4 and insulating layer 8 Active island 3 within total projection area, the boundary II on active island 3 and the side of total projection area built by electrode 4 and insulating layer 8 Boundary's I autoregistrations.
With reference to Fig. 5, the thickness of insulating layer 8 is less than the diffusion length of the substance containing oxygen element in insulating layer 8, described Substance containing oxygen element can penetrate insulating layer 8 in annealing, thus insulating layer 8 is oxygen permeable layer.Insulating layer 8 includes following material One or more combinations in material：Silica, silicon oxynitride, wherein, the ratio of silicon nitride is less than in the silicon oxynitride 20%.The thickness of insulating layer 8 is 10 to 3000 nanometers.Preferably, the thickness of insulating layer 8 is between 200 nanometers to 500 nanometers.
With reference to Fig. 5, in annealing, electrode 4 stops the substance containing oxygen element, and active island 3 is under the covering of electrode 4 The resistivity in region be minimized, form source region 31, drain region 33；It is described with the characteristic of electrode 4 on the contrary, in annealing Substance containing oxygen element can penetrate insulating layer 8 and enter active island 3, therefore the electricity in region of the active island 3 under the covering of insulating layer 8 Resistance rate is maintained and even improves, and forms channel region 32.Source region 31, drain region 33 are connected with each other with channel region 32 and are located at respectively The both ends of channel region 32.Between joint face, drain region 33 and channel region 32 between source region 31 and channel region 32 that its annealing is formed Joint face IV without any lithography alignment technique, and be self aligned to side of the electrode 4 within active 3 projected area of island Boundary III.
Embodiment three：
With reference to Fig. 6, Fig. 6 is the sectional view of thin-film transistor structure the third embodiment in the utility model.This implementation Thin film transistor (TFT) uses back grid structure in example.Wherein, thin film transistor (TFT) includes：Substrate 1；It is provided with gate stack on substrate 1 2, gate stack 2 includes patterned gate electrode 21 and the gate insulating layer 22 being arranged on gate electrode 21；Described Active layer is provided on gate stack；It is partially covered with patterned insulating layer 7 on the active layer；In the active layer With electrode 4 is provided on insulating layer 7, electrode 4 is electrically connected with the subregion of the active layer；Electrode 4 is also covered with figure above The third insulating layer 9 of shape, is self-aligned to the boundary V of third insulating layer 9, patterned electrodes 4, make electrode 4 projected area and The projected area of third insulating layer 9 is completely overlapped；It is the first insulating layer 71 to make part of the insulating layer 7 under non-electrode 4 coverings, absolutely Part of the edge layer 7 under the covering of electrode 4 is second insulating layer 72；Second insulating layer 72 is within the projected area of electrode 4, and first Insulating layer 71 is except the projected area of electrode 4；The boundary I for the total projection area that autoregistration is built by electrode 4 and insulating layer 7, The graphical active layer is formed in the active island 3 within the total projection area built by electrode 4 and insulating layer 7, active island 3 The boundary I autoregistrations of boundary II and the total projection area built by electrode 4 and insulating layer 7；
With reference to Fig. 6, in annealing, third insulating layer 9, electrode 4 and second insulating layer 72 stop described oxygen-containing jointly The substance of element, the resistivity in region of the active island 3 under the covering of third insulating layer 9, electrode 4 and second insulating layer 72 are dropped It is low, form source region 31, drain region 33；On the contrary, in annealing, the substance containing oxygen element can be penetrated characteristic with electrode 4 First insulating layer 71 enters active island 3, thus the resistivity in region of the active island 3 under the covering of the first insulating layer 71 is maintained It even improves, forms channel region 32.Source region 31, drain region 33 are connected with each other with channel region 32 and respectively positioned at the two of channel region 32 End.Its joint face between the source region 31 formed and channel region 32 of annealing, the joint face IV between drain region 33 and channel region 32 without Need to be by any lithography alignment technique, and it is self aligned to boundary III of the electrode 4 within active 3 projected area of island.
With reference to Fig. 7, Fig. 7 is a kind of schematic diagram of display module structure, display surface in display panel in the utility model Plate is made of multiple display modules.Display module includes thin film transistor (TFT), intermediate insulating layer 10, pixel electrode 11, photoelectricity material Material 12 and public electrode 13.Pixel electrode 11 and the electrode 4 of the thin film transistor (TFT) pass through the through-hole phase on intermediate insulating layer 10 Electrical connection.Intermediate insulating layer 10 also acts as the entire thin film transistor (TFT) of protection and exempts from effect affected by environment.Photoelectric material 11 includes But it is not limited to：Liquid crystal, light emitting diode, Organic Light Emitting Diode, light emitting diode with quantum dots.In the display panel of the present embodiment In, the thin film transistor (TFT) is thin film transistor (TFT) described in Fig. 5.The thin film transistor (TFT) can be also used for forming circuit, such as aobvious Show the driving circuit in panel.
Finally it should be noted that above example is only the preferred embodiment of the utility model rather than new to this practicality The limitation of type protection domain, it will be understood by those of ordinary skill in the art that, within the spirit and principle of the utility model Any modification, equivalent replacement or improvement for being made etc., should be included within the scope of protection of this utility model.

Claims (8)

1. a kind of thin film transistor (TFT), it is characterised in that including：
Substrate；
Gate stack is set to the substrate, including gate electrode and the gate insulating layer being covered on the gate electrode；
Active island, is made of metal oxide, and is formed by graphical active layer, is set on the gate stack, It is divided into source region, drain region and channel region；
Electrode, is covered in the active island portion subregion, and the thickness of the electrode is more than the substance containing oxygen element in the electrode Diffusion length；
Insulating layer, between the electrode and the active island, part of the insulating layer under non-electrode covering is the One insulating layer, the thickness of first insulating layer are less than the diffusion of the substance containing oxygen element in first insulating layer and grow Degree；
The active island is formed by the graphical active layer, positioned at by the electrode and the insulation layer building Within total projection area, and the vertical guide on the boundary on the active island is self-aligned to by the electrode and the insulation layer building The vertical guide on the boundary of total projection area；Region of the active island under electrode covering is the source region and described Drain region, the region under the non-electrode covering is the channel region；The source region, the drain region and the channel region mutually interconnect It connects, and is located at the both ends of the channel region respectively；Joint face, the drain region between the source region and the channel region with it is described Joint face between channel region, two joint faces are self-aligned to boundary of the electrode within the active island projected area Vertical guide；The resistivity of the channel region is more than the source region, the resistivity in the drain region.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the vertical guide autoregistration on the boundary on the active island It is and small with the spacing of corresponding vertical guide in the vertical guide by the electrode and the boundary of the total projection area of the insulation layer building In 100 times of the active island thickness.
3. thin film transistor (TFT) according to claim 1, which is characterized in that the connection between the source region and the channel region Joint face between face, the drain region and the channel region, two joint faces are self-aligned to the electrode on the active island The vertical guide on the boundary within projected area, and with 100 times that are smaller than the active island thickness of corresponding vertical guide.
4. thin film transistor (TFT) according to claim 1, which is characterized in that the channel region and the source region, the drain region Resistivity ratio be more than 1000 times.
5. thin film transistor (TFT) according to claim 1, which is characterized in that the thickness of first insulating layer is 10 to 3000 Nanometer.
6. thin film transistor (TFT) according to claim 1, which is characterized in that the thickness of the electrode is to be described containing oxygen element Substance is in the electrode between 2 to 100 times of diffusion length.
7. thin film transistor (TFT) according to claim 1, which is characterized in that the thickness of the electrode is 10 to 3000 nanometers.
8. a kind of display pannel, including multigroup display module, which is characterized in that the display module includes claim 1 to 7 Any one thin film transistor (TFT).
CN201721522557.7U 2017-11-15 2017-11-15 A kind of thin film transistor (TFT) and display pannel Expired - Fee Related CN207517701U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020113858A1 (en) * 2018-12-06 2020-06-11 Boe Technology Group Co., Ltd. Display substrate, manufacturing method thereof, and display apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020113858A1 (en) * 2018-12-06 2020-06-11 Boe Technology Group Co., Ltd. Display substrate, manufacturing method thereof, and display apparatus
US11329115B2 (en) * 2018-12-06 2022-05-10 Hefei Xinsheng Optoelectronics Technology Co., Ltd Display substrate, manufacturing method thereof, and display apparatus

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