CN112397573B - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
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- CN112397573B CN112397573B CN202011286002.3A CN202011286002A CN112397573B CN 112397573 B CN112397573 B CN 112397573B CN 202011286002 A CN202011286002 A CN 202011286002A CN 112397573 B CN112397573 B CN 112397573B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 21
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- 238000000151 deposition Methods 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 6
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 14
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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Abstract
The application provides an array substrate, a preparation method thereof and a display panel, wherein the array substrate comprises a substrate; an active layer including a first active layer and a second active layer stacked; a source electrode and a drain electrode disposed over two opposite edge regions of the first active layer; wherein the second active layer is spaced apart from and between the source electrode and the drain electrode; the oxygen content of the second active layer is greater than the oxygen content of the first active layer. According to the preparation method, the second active layer is prepared on the first active layer, and the oxygen content of the second active layer is larger than that of the first active layer, so that the grid insulation layer of the array substrate is prevented from being damaged due to direct contact between plasma and the first active layer in the deposition process, and the performance of a device is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display panel.
Background
With the continuous development of display technology, the requirements of resolution, power consumption and image quality of display products are increasing. To meet these requirements, low temperature poly oxide (Low Temperature Polycrystalline Oxide, LTPO) technology is often used to fabricate the pixel driving circuits in the driving back plane of the display product. This LTPO technique is: meanwhile, the low-temperature polycrystalline silicon thin film transistor and the metal oxide thin film transistor are used as functional tubes in the pixel driving circuit, the low-temperature polycrystalline silicon thin film transistor has high mobility, so that the charging speed of a pixel capacitor can be increased, the metal oxide thin film transistor has lower leakage current, the advantages of the low-temperature polycrystalline silicon thin film transistor and the metal oxide thin film transistor are combined, and the development of display products with high resolution, low power consumption and high image quality is facilitated.
Currently, in the manufacture of a substrate of a pixel driving circuit by LTPO technology, a top packaging film is manufactured by low-temperature CVD (chemical vapor deposition) technology, and when an insulating layer is manufactured by CVD, a large amount of hydrogen is required, so that the hydrogen is easy to diffuse into an active layer in a metal oxide thin film transistor, and in the process of depositing the insulating layer, the active layer is damaged by bombardment of plasma on an IGZO (indium gallium zinc oxide) layer, which causes the influence on the electrical performance of the IGZO layer.
Disclosure of Invention
The application provides an array substrate, a preparation method thereof and a display panel, which are used for preventing the problem that hydrogen introduced in the process of manufacturing a low-temperature polycrystalline silicon thin film transistor is easy to influence an active layer in a metal oxide thin film transistor, so that the performance of a device is reduced.
In order to achieve the above effects, the technical scheme provided by the application is as follows:
an array substrate, comprising:
a substrate;
an active layer including a first active layer and a second active layer stacked;
a source electrode and a drain electrode disposed over two opposite edge regions of the first active layer; wherein,,
the second active layer is arranged at intervals from the source electrode and the drain electrode and is positioned between the source electrode and the drain electrode; the oxygen content of the second active layer is greater than the oxygen content of the first active layer.
In the array substrate of the application, the first active layer comprises a channel region, and the second active layer is arranged corresponding to the channel region of the first active layer.
In the array substrate, the projection of the channel region of the first active layer on the substrate is positioned in the projection of the second active layer on the substrate.
In the array substrate, the array substrate further comprises a grid electrode and a grid electrode insulating layer; the first active layer, the second active layer, the gate insulating layer and the gate are sequentially stacked.
In the array substrate, the array substrate further comprises a grid electrode and a grid electrode insulating layer; the grid electrode, the grid electrode insulating layer, the first active layer and the second active layer are sequentially stacked.
In the array substrate, the thickness of the second active layer is smaller than that of the first active layer.
In the array substrate, the thickness of the first active layer is 20nm-100nm, and the thickness of the second active layer is 20nm-200nm.
The application also provides a preparation method of the array substrate, which comprises the following steps:
step S10: sequentially preparing a first active layer film and a second active layer film on a substrate, wherein the oxygen content of the second active layer film is larger than that of the first active layer film;
step S20: patterning the first active layer film and the second active layer film to form an active layer, wherein the active layer comprises a first active layer and a second active layer;
step S30: and patterning the second active layer to enable the thickness of the second active layer to be smaller than that of the first active layer.
In the preparation method of the present application, the step S10 includes depositing a second active layer film on the first active layer film, and simultaneously introducing argon and oxygen; the ratio of argon to oxygen is 8:1 to 10:1.
the application also provides a display panel, which comprises any one of the array substrates.
The beneficial effects are that: according to the method, the second active layer is prepared on the first active layer, and the oxygen content of the second active layer is larger than that of the first active layer, so that the first active layer is prevented from being damaged by plasma in the deposition process of the gate insulating layer of the array substrate, and the performance of a device is improved; and the passivation layer and the packaging layer are blocked by diffusion of hydrogen in the preparation process, so that the stability of the performances such as threshold voltage, switching current ratio and the like of the active layer is maintained.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an array substrate provided in the present application;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a second structure of the array substrate according to the embodiment of the present application;
fig. 4 is a flowchart of steps of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 5A to 5F are schematic structural diagrams of the array substrate in the preparation process according to the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the prior art, in the manufacturing of a substrate of a pixel driving circuit by LTPO (low temperature polycrystalline oxide) technology, a top packaging film is manufactured by adopting a low temperature CVD (chemical vapor deposition) technology, and when an insulating layer manufactured by CVD is adopted, a large amount of hydrogen is required, so that the hydrogen is easy to diffuse into an active layer in a metal oxide thin film transistor, and in the process of depositing the insulating layer, the active layer is damaged by bombardment of an IGZO (indium gallium zinc oxide) layer by plasma, and the above factors all cause the influence on the electrical performance of the IGZO layer. Based on the above, the application provides an array substrate, a preparation method thereof and a display panel, which can solve the defects.
Referring to fig. 1, a schematic structure of an array substrate provided in the present application is shown.
In this application, the array substrate includes a substrate 10; an active layer 20 disposed on the substrate 10, the active layer 20 including a first active layer 21 and a second active layer 22 which are stacked; a gate insulating layer 30 disposed on the active layer 20; a gate electrode 40 disposed on the gate insulating layer 30; and a source electrode 51 and a drain electrode 52 disposed on the gate insulating layer 30, the source electrode 51 and the drain electrode 52 being disposed over two opposite edge regions of the first active layer 21.
Wherein the second active layer 22 is spaced apart from the source electrode 51 and the drain electrode 52 and is located between the source electrode 51 and the drain electrode 52; the oxygen content of the second active layer 22 is greater than the oxygen content of the first active layer 21.
It should be noted that, the structure of the array substrate is not limited by the present application, and the array substrate is a top-gate array substrate, a bottom-gate array substrate or a dual-gate array substrate, and the array substrate is only used as an example; meanwhile, in the present application, the array substrate includes the substrate 10, the active layer 20, the gate insulating layer 30, the gate electrode 40, the source electrode 51 and the drain electrode 52, which are only used for illustration, and the present application does not limit the film structure of the array substrate.
The second active layer 22 is prepared on the first active layer 21, and the oxygen content of the second active layer 22 is larger than that of the first active layer 21, so that the first active layer 21 is prevented from being damaged due to the fact that plasma is directly contacted with the first active layer 21 in the deposition process of the gate insulating layer 30 of the array substrate.
The technical solutions of the present application will now be described with reference to specific embodiments.
Example 1
Referring to fig. 2, a first structural schematic diagram of an array substrate according to an embodiment of the present disclosure is shown.
In this embodiment, the array substrate is a top gate array substrate.
In this embodiment, the array substrate includes a substrate 10; an active layer 20 disposed on the substrate 10, the active layer 20 including a first active layer 21 and a second active layer 22 which are stacked; a gate insulating layer 30 disposed on the active layer 20; a gate electrode 40 disposed on the gate insulating layer 30; and a source electrode 51 and a drain electrode 52 disposed on the gate insulating layer 30, the source electrode 51 and the drain electrode 52 being disposed over two opposite edge regions of the first active layer 21.
The array substrate further includes a passivation layer 60 and an encapsulation layer 70 over the source and drain electrodes 51 and 52.
In this embodiment, the substrate 10 is a PI substrate, mainly polyimide, and the PI material can effectively improve the light transmittance.
In this embodiment, the material of the active layer 20 includes, but is not limited to, indium gallium zinc oxide, the first active layer 21 and the second active layer 22 are both indium zinc oxide thin film layers after oxygen-containing plasma treatment, and the oxygen content of the second active layer 22 is greater than that of the first active layer 21.
In the present embodiment, the first active layer 21 includes a channel region 210, a source contact region 211 contacting the source electrode 51, and a drain contact region 212 contacting the drain electrode 52; the source contact region 211 and the drain contact region 212 are separated by the channel region 210.
The second active layer 22 is disposed corresponding to the channel region of the first active layer 21; the projection of the channel region 210 of the first active layer 21 onto the substrate 10 is located within the projection of the second active layer 22 onto the substrate.
In the present embodiment, the thickness of the second active layer 22 is smaller than the thickness of the first active layer 21; the thickness of the first active layer is 20nm-100nm, and the thickness of the second active layer is 20nm-200nm, which is not limited in this embodiment.
In the present embodiment, the gate insulating layer 30 entirely covers the first active layer 21 and the second active layer 22; the thickness of the gate insulating layer 30 is 50nm to 300nm, which is not limited in this embodiment.
The gate insulating layer 30 has strong water-oxygen barrier capability and insulating capability, and its materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., or a stack thereof; the preparation method of the gate insulating layer 30 includes, but is not limited to, chemical vapor deposition.
In this embodiment, the second active layer 22 with high oxygen content completely covers the channel region 210 of the first active layer 21, so as to prevent the first active layer 21 from being damaged due to direct contact between plasma and the first active layer 21 during the deposition of the gate insulating layer 30 of the array substrate.
In this embodiment, the gate electrode 40 is disposed corresponding to the channel region 210 of the first active layer 40, and the first active layer 21, the second active layer 22, the gate insulating layer 30, and the gate electrode 40 are sequentially stacked; the channel region 210 of the first active layer 21, the second active layer 22, and the gate electrode 40 are in one-to-one correspondence.
In the present embodiment, the source electrode 51 and the drain electrode 52 are disposed over two opposite edge regions of the first active layer 21, the second active layer 22 is disposed at a distance from the source electrode 51 and the drain electrode 52, and the second active layer 22 is located between the source electrode 51 and the drain electrode 52.
In this embodiment, the gate insulating layer 30 is provided with an opening that exposes a portion of the first active layer 21, and the opening is located above the source contact region 211 and the drain contact region 212 of the first active layer 21; wherein the source electrode 51 is in contact with the source contact region 211 of the active layer 21 through the opening, and the drain electrode 52 is in contact with the drain contact region 212 of the active layer 21 through the opening.
In the present embodiment, the materials of the gate electrode 40, the source electrode 51 and the drain electrode 52 include, but are not limited to, metals such as molybdenum, silver, aluminum, or a stack thereof.
In this embodiment, the passivation layer 60 is made of a material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc. or a laminate thereof, and the passivation layer 60 and the encapsulation layer 70 are prepared by a method including, but not limited to, vapor deposition.
In this embodiment, the second active layer 22 with high oxygen content is prepared on the first active layer 21, the second active layer 22 completely covers the channel region 210 of the first active layer 21, and the second active layer 22 is an indium zinc oxide thin film layer after oxygen-containing plasma treatment, so that diffusion of hydrogen gas in the passivation layer 60 and the encapsulation layer 70 in the preparation process is blocked, and the performance of the device is improved.
It should be noted that, in the present embodiment, the array substrate includes the substrate 10, the active layer 20, the gate insulating layer 30, the gate electrode 40, the source electrode 51, the drain electrode 52, the passivation layer 60, and the encapsulation layer 70, which are only used for illustration, and the present embodiment does not limit the film structure of the array substrate.
Referring to fig. 3, a second structure of the array substrate provided in the embodiment of the present application is shown.
In this embodiment, the structure of the array substrate is similar to/the first structure of the array substrate provided in the foregoing embodiment, and reference is made to the description of the array substrate in the foregoing embodiment, which is not repeated herein, and the difference between the two structures is only that:
in this embodiment, the array substrate is a bottom gate array substrate.
In this embodiment, the array substrate includes a substrate 10; a gate electrode 40 disposed on the substrate 10; a gate insulating layer 30 disposed over the gate electrode 40; an active layer 20 disposed over the gate insulating layer 30, the active layer 20 including a first active layer 21 and a second active layer 22 stacked; a source electrode 51 and a drain electrode 52 disposed over the active layer 20 and covering two opposite edge regions of the first active layer 21; a passivation layer 60 and an encapsulation layer 70 disposed over the active layer 20, the source electrode 51, and the drain electrode 52.
In this embodiment, the material of the active layer 20 includes, but is not limited to, indium gallium zinc oxide, the first active layer 21 and the second active layer 22 are both indium zinc oxide thin film layers after oxygen-containing plasma treatment, and the oxygen content of the second active layer 22 is greater than that of the first active layer 21.
In this embodiment, the first active layer 21 includes a channel region 210, a source contact region 211 contacting the source electrode 51, and a drain contact region 212 contacting the drain electrode 52, and the source contact region 211 and the drain contact region 212 are separated by the channel region 210; the source electrode 51 and the drain electrode 52 are in direct contact with the first active layer 21.
Example two
Referring to fig. 4, a flowchart of steps of a method for manufacturing an array substrate is provided in an embodiment of the present application.
In this embodiment, the preparation method of the array substrate includes:
step S10: a first active layer thin film and a second active layer thin film are sequentially prepared on the substrate 10, wherein the oxygen content of the second active layer thin film is greater than that of the first active layer thin film, as shown in fig. 5A.
In this embodiment, the step S10 includes the steps of:
step S11: a substrate 10 is provided, the substrate 10 including, but not limited to, a glass substrate and a flexible substrate.
Further, in this embodiment, the substrate 10 is a flexible and transparent PI substrate, mainly polyimide, and the PI material can effectively improve the light transmittance.
Step S12: a first active layer film is deposited on the substrate 10, wherein the material of the first active layer film comprises but is not limited to indium gallium zinc oxide, and the deposition method of the first active layer film comprises but is not limited to a physical vapor deposition method.
Step S13: depositing a second active layer film on the first active layer film, and introducing argon and oxygen during deposition; the ratio of argon to oxygen is 8:1 to 10:1, thereby preparing a second active layer film with higher oxygen content.
In step S13, the material of the second active layer film includes, but is not limited to, indium gallium zinc oxide, and the deposition method of the second active layer film includes, but is not limited to, physical vapor deposition method, which is not limited in this embodiment.
Step S20: the first active layer film and the second active layer film are patterned to form an active layer 20 including a first active layer 21 and a second active layer 22, as shown in fig. 5B.
In the step S20, the first active layer 21 includes a channel region 210, a source contact region 211, and a drain contact region 212, and the source contact region 211 and the drain contact region 212 are separated by the channel region 210; the thickness of the first active layer is 20nm-100nm.
Step S30: the second active layer 22 is patterned so that the thickness of the second active layer 22 is smaller than the thickness of the first active layer 21, as shown in fig. 5C.
In step S30, the method of patterning the second active layer 40 includes, but is not limited to, etching, and the thickness of the second active layer is 20nm-200nm, which is not limited in this embodiment.
In this embodiment, the second active layer 22 is disposed corresponding to the channel region of the first active layer 21; the projection of the channel region 210 of the first active layer 21 onto the substrate 10 is located within the projection of the second active layer 22 onto the substrate.
In this embodiment, the method for manufacturing an array substrate further includes:
step S40: a gate insulating layer 30 and a gate electrode 40 are prepared over the active layer 20 as shown in fig. 5D.
In this embodiment, the step S40 includes the steps of:
step S41: a gate insulating layer 30 is prepared on the active layer 20, the gate insulating layer 30 completely covers the first active layer 21 and the second active layer 22, and the thickness of the gate insulating layer 30 is 50nm to 300nm, which is not limited in this embodiment.
The gate insulating layer 30 has strong water-oxygen barrier capability and insulating capability, and its materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., or a stack thereof; the preparation method of the gate insulating layer 30 includes, but is not limited to, chemical vapor deposition, and the second active layer 22 completely covers the channel region 410 of the first active layer 21, so as to prevent the gate insulating layer 30 of the array substrate from being damaged by direct contact of plasma with the first active layer 21 during deposition.
Step S42: the gate insulating layer 30 is patterned to form a via on the source contact region 211 of the first active layer 21 and a via on the drain contact region 212 of the first active layer 21.
Step S43: a gate electrode 40 is formed on the gate insulating layer 30, and a material of the gate electrode 40 includes, but is not limited to, molybdenum, silver, aluminum, or other metals or a stack thereof, and the gate electrode 40 is disposed corresponding to the channel region 410 of the first active layer 40, and the channel region 410 of the first active layer 21, the second active layer 22, and the gate electrode 40 are in one-to-one correspondence.
Step S50: a source electrode 51 and a drain electrode 52 are formed on the gate insulating layer 30, the source electrode 51 and the drain electrode 52 being disposed over two opposite edge regions of the first active layer 21, as shown in fig. 5E.
The source electrode 51 contacts the source contact region 211 of the active layer 21 through the opening, and the drain electrode 52 contacts the drain contact region 212 of the active layer 21 through the opening; the source 51 and drain 52 materials include, but are not limited to, metals such as molybdenum, silver, aluminum, or a stack thereof.
It should be noted that, in the present embodiment, the gate electrode 40, the source electrode 51 and the drain electrode 52 may be prepared at the same time, and the step S43 and the step 60 in the present embodiment are only used for illustration, which is not limited in this embodiment.
Step S60: a passivation layer 60 and an encapsulation layer 70 are formed on the source electrode 51, the drain electrode 52, and the gate electrode 40, as shown in fig. 5F.
In this embodiment, the passivation layer 60 is made of a material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc. or a laminate thereof, and the passivation layer 60 and the encapsulation layer 70 are prepared by a method including, but not limited to, vapor deposition.
In this embodiment, the second active layer 22 with high oxygen content is prepared on the first active layer 21, the second active layer 22 completely covers the channel region 210 of the first active layer 21, and the second active layer 22 is an indium zinc oxide thin film layer treated by oxygen-containing plasma, so as to prevent the gate insulating layer 30 of the array substrate from being directly contacted with the first active layer 21 in the deposition process to cause damage to the first active layer 21, and meanwhile, the diffusion of hydrogen in the preparation process of the passivation layer 60 and the encapsulation layer 70 plays a role in blocking, so that the stability of the threshold voltage, the switching current ratio and other performances of the active layer is maintained.
The application provides an array substrate, a preparation method thereof and a display panel, wherein the array substrate comprises a substrate; the active layer is made of indium gallium zinc oxide and comprises a first active layer and a second active layer which are stacked; a source electrode and a drain electrode disposed over two opposite edge regions of the first active layer; wherein the second active layer is spaced apart from and between the source electrode and the drain electrode; the oxygen content of the second active layer is greater than the oxygen content of the first active layer.
According to the preparation method, the second active layer is prepared on the first active layer, and the oxygen content of the second active layer is larger than that of the first active layer, so that the damage caused by direct contact of plasma and the first active layer in the deposition process of the grid insulating layer of the array substrate is prevented, the diffusion of hydrogen in the preparation process of the passivation layer and the packaging layer is blocked, and the performance of a device is improved.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The above describes in detail an array substrate, a preparation method thereof and a display panel provided in the embodiments of the present application, and specific examples are applied to describe the principles and embodiments of the present application, where the description of the above embodiments is only for helping to understand the technical solution and core ideas of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (7)
1. An array substrate, characterized by comprising:
a substrate;
the active layer comprises a first active layer positioned on the substrate and a second active layer positioned on one side of the first active layer away from the substrate;
a gate insulating layer located at a side of the active layer away from the substrate, the gate insulating layer covering the active layer;
a gate electrode located on the gate insulating layer and far from the substrateThe saidOne side of the active layer;
a source electrode and a drain electrode disposed over two opposite edge regions of the first active layer; wherein,,
the first active layer and the second active layer are both indium zinc oxide thin film layers subjected to oxygen-containing plasma treatment, and the second active layer is arranged at intervals with the source electrode and the drain electrode and is positioned between the source electrode and the drain electrode; the oxygen content of the second active layer is larger than that of the first active layer, the first active layer comprises a channel region, the second active layer is arranged corresponding to the channel region of the first active layer, and the second active layer completely covers the channel region of the first active layer.
2. The array substrate of claim 1, wherein a projection of the first active layer channel region onto the substrate is within a projection of the second active layer onto the substrate.
3. The array substrate of claim 1, wherein a thickness of the second active layer is less than a thickness of the first active layer.
4. The array substrate of claim 3, wherein the first active layer has a thickness of 20nm to 100nm and the second active layer has a thickness of 20nm to 200nm.
5. The preparation method of the array substrate is characterized by comprising the following steps:
step S10: sequentially preparing a first active layer film and a second active layer film on a substrate, wherein the oxygen content of the second active layer film is larger than that of the first active layer film;
step S20: patterning the first active layer film and the second active layer film to form an active layer, wherein the active layer comprises a first active layer and a second active layer, and the first active layer and the second active layer are both indium zinc oxide film layers subjected to oxygen-containing plasma treatment;
step S30: patterning the second active layer to enable the thickness of the second active layer to be smaller than that of the first active layer, wherein the first active layer comprises a channel region, the second active layer is arranged corresponding to the channel region of the first active layer, and the second active layer completely covers the channel region of the first active layer;
step S40: and preparing a gate insulating layer and a gate electrode in sequence on one side of the second active layer far away from the first active layer, wherein the gate insulating layer completely covers the first active layer and the second active layer.
6. The method of claim 5, wherein step S10 includes depositing a second active layer film on the first active layer film while introducing argon and oxygen; the ratio of argon to oxygen is 8:1 to 10:1.
7. a display panel comprising the array substrate according to any one of claims 1 to 4.
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