CN115588696A - Thin film transistor, array substrate and preparation method of thin film transistor - Google Patents
Thin film transistor, array substrate and preparation method of thin film transistor Download PDFInfo
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- CN115588696A CN115588696A CN202211205487.8A CN202211205487A CN115588696A CN 115588696 A CN115588696 A CN 115588696A CN 202211205487 A CN202211205487 A CN 202211205487A CN 115588696 A CN115588696 A CN 115588696A
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- 239000010409 thin film Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 4
- 238000002834 transmittance Methods 0.000 claims description 4
- 238000009832 plasma treatment Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000003384 imaging method Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 85
- 239000011241 protective layer Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
The application discloses a thin film transistor, an array substrate and a preparation method of the thin film transistor. The thin film transistor comprises a substrate and an active layer, wherein the active layer is arranged on the substrate and comprises a source contact region, a drain contact region and a channel region; the thickness of the source contact region and the drain contact region is larger than that of the channel region, and the conduction depth of the source contact region is smaller than or equal to the thickness difference of the source contact region and the channel region; the drain contact region has a depth of conductivity less than or equal to the difference in thickness between the source contact region and the channel region. According to the method and the device, the thickness of the source electrode contact region and the thickness of the drain electrode contact region are larger than that of the channel region, and the depth of the conductor is limited, so that the channel region is relatively independent, and the influence of ion transverse diffusion in the source electrode contact region and the drain electrode contact region on the channel region is further reduced.
Description
Technical Field
The present disclosure relates to the field of semiconductor display technologies, and in particular, to a thin film transistor, an array substrate, and a method for manufacturing the thin film transistor.
Background
An active layer of the thin film transistor includes a source contact region, a drain contact region, and a channel region. In the process of forming the source contact region and the drain contact region by conducting a conductor process on the active layer, the channel region is easily affected due to the lateral diffusion of ions, so that the problems of reduction of the effective length of the channel region, performance degradation and the like are caused.
Disclosure of Invention
The application mainly provides a thin film transistor, an array substrate and a preparation method of the thin film transistor, and the influence of ion transverse diffusion in a source electrode contact area and a drain electrode contact area on a channel area can be reduced.
In order to solve the technical problem, the application adopts a technical scheme that: the thin film transistor comprises a substrate and an active layer, wherein the active layer is arranged on the substrate and comprises a source contact region, a drain contact region and a channel region; the thickness of the source electrode contact region and the drain electrode contact region is larger than that of the channel region; the depth of the conductor of the source contact region is less than or equal to the thickness difference between the source contact region and the channel region; the drain contact region has a depth of conductivity less than or equal to the difference in thickness between the source contact region and the channel region.
In some embodiments of the present application, the source contact region and the drain contact region include a first region and a second region that are arranged in a stack. The first region is connected with the channel region, the thickness of the first region is equal to that of the channel region, and the mobility of the first region is smaller than that of the second region.
In some embodiments of the present application, the source contact region and the drain contact region have a thickness of 60 to 80nm, and the channel region has a thickness of 40 to 60nm.
In order to solve the technical problem, the application adopts a technical scheme that: an array substrate is provided, which includes the thin film transistor in any of the above embodiments.
In order to solve the technical problem, the application adopts a technical scheme that: the preparation method of the thin film transistor comprises the steps of forming an active layer on a substrate, wherein the active layer comprises a source contact region, a drain contact region and a channel region, the thickness of the source contact region and the thickness of the drain contact region are larger than that of the channel region, and the conductor depth of the source contact region is smaller than or equal to the thickness difference between the source contact region and the channel region; the drain contact region has a depth of conduction less than or equal to the difference in thickness between the source contact region and the channel region.
In some embodiments of the present application, forming the active layer on the substrate includes: an oxide semiconductor layer is formed over a substrate.
And carrying out graphical processing on the oxide semiconductor layer by using a half-tone mask plate to form a source electrode contact area, a drain electrode contact area and a channel area, wherein the light transmittance of the half-tone mask plate corresponding to the channel area is greater than that of the half-tone mask plate corresponding to the source electrode contact area and the drain electrode contact area, so that the thickness of the source electrode contact area and the drain electrode contact area is greater than that of the channel area.
And conducting the conductor treatment on the source contact area and the drain contact area to form a source contact area and a drain contact area.
In some embodiments of the present application, the conducting the source contact region and the drain contact region comprises: the source contact region and the drain contact region are plasma treated so that the source contact region and the drain contact region are made conductive. Wherein the depth of the electrical conduction is equal to the difference in thickness between the source contact region and the channel region and the drain contact region.
In some embodiments of the present application, the depth of the conductimerization is greater than or equal to 10nm and less than or equal to 20nm.
In some embodiments of the present application, the conducting the source contact region and the drain contact region comprises: and forming a gate insulating layer and a gate electrode on the patterned active layer. And performing plasma treatment on the source contact region and the drain contact region to make the source contact region and the drain contact region conductive to form a source contact region and a drain contact region. Wherein the width of the gate insulating layer is greater than or equal to the width of the channel region.
In some embodiments of the present application, forming the active layer on the substrate includes: a first active layer and a second active layer are sequentially formed on a substrate, and the mobility of the first active layer is smaller than that of the second active layer. And carrying out graphical processing on the second active layer to form a source electrode contact region, a drain electrode contact region and a channel region, wherein the source electrode contact region and the drain electrode contact region are positioned on two opposite sides of the channel region. The source contact region and the drain contact region include a first region and a second region arranged in a stacked manner, the first region includes a first active layer, the second region includes a second active layer, and the channel region includes the first active layer, so that the thickness of the source contact region and the drain contact region is greater than that of the channel region.
Different from the prior art situation, the beneficial effects of this application are: the thin film transistor comprises an active layer, wherein the active layer comprises a source electrode contact region, a drain electrode contact region and a channel region, the thickness of the source electrode contact region and the thickness of the drain electrode contact region are larger than that of the channel region, and the conductor depth of the source electrode contact region is smaller than or equal to the thickness difference between the source electrode contact region and the channel region; the drain contact region has a depth of conductivity less than or equal to the difference in thickness between the source contact region and the channel region. Because the thickness of the source electrode contact region and the drain electrode contact region is larger than that of the channel region, and the limitation on the depth of the conductor is realized, the channel region can be relatively independent, and the influence of the transverse diffusion of ions in the source electrode contact region and the drain electrode contact region on the channel region is further reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;
FIG. 2 is a schematic flow chart illustrating a method of fabricating a thin film transistor according to an embodiment of the present disclosure;
FIG. 3 is a schematic flow chart illustrating a method of fabricating a thin film transistor according to an embodiment of the present disclosure;
FIG. 4 is a schematic flow chart illustrating a method of fabricating a thin film transistor according to another embodiment of the present disclosure;
fig. 5 is a schematic flow chart of another embodiment of a method for manufacturing a thin film transistor according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
In some embodiments, the thin film transistor includes a substrate 10, an active layer 20, a gate insulating layer 31, a gate electrode 32, a protective layer, a source electrode 33, and a drain electrode 34, the active layer 20 being disposed on the substrate 10; the gate insulating layer 31 is disposed on a side of the active layer 20 away from the substrate 10; the gate electrode 32 is arranged on one side of the gate insulating layer 31 away from the active layer; the protective layer is arranged on the side of the gate electrode 32 away from the gate insulating layer 31; a source electrode 33 and a drain electrode 34 are provided on the side of the protective layer away from the gate electrode; the active layer 20 includes a source contact region 21, a drain contact region 22, and a channel region 23, the source contact region 21 and the drain contact region 22 are respectively located at two opposite sides of the channel region 23, and the thickness of the source contact region 21 and the thickness of the drain contact region 22 are greater than the thickness of the channel region 23. The source electrode 33 in the present embodiment is electrically connected to the source contact region 21 through a via, and the drain electrode 34 is electrically connected to the drain contact region 22 through a via. The thin film transistor is an insulated gate field effect transistor and includes a source electrode, a drain electrode, and a gate electrode 32. In this embodiment, the source includes a source electrode 33 and a source contact region 21, and the drain includes a drain electrode 34 and a drain contact region 22. The source contact region 21 and the drain contact region 22 communicate with the channel region 23.
The material of the active layer 20 includes an oxide semiconductor. Illustratively, the oxide semiconductor is IGZO (indium gallium zinc oxide). IGZO is a new semiconductor material having higher electron mobility than amorphous silicon (a-Si). The higher the electron mobility, the larger the information transmission quantity of the device, and the narrower channel can be used for transmitting information, thereby realizing higher resolution. Since the thickness of the source contact region 21 and the drain contact region 22 is greater than the thickness of the channel region 23, the channel region 23 can be relatively independent, thereby reducing the influence of the lateral diffusion of ions in the source contact region 21 and the drain contact region 22 on the channel region 23.
In some embodiments, the source contact region 21 and the drain contact region 22 include a first region 24 and a second region 25 arranged in a stack. Illustratively, the thickness of the first region 24 of the source contact region 21 and the first region 24 of the drain contact region 22 is the same as the thickness of the channel region 23, respectively on opposite sides of the channel region 23. The first region 24 and the channel region 23 may be made of the same material. The second region 25 of the source contact region 21 has the same thickness as the second region 25 of the drain contact region 22. The thickness of the first region 24 and the second region 25 can be set according to actual conditions, and the use requirements can be met. Conduction is achieved by the active area (i.e. the region of conductibility) of the source contact region 21 and the drain contact region 22 being the second region 25, i.e. the source electrode 33 is in contact with the second region 25 of the source contact region 21 and the drain electrode 34 is in contact with the second region 25 of the drain contact region 22.
The first region 24 is connected to the channel region 23, and the mobility of the first region 24 is smaller than that of the second region 25. I.e. the second region 25 is a region of electrical conductivity, the second region 25 having a conductivity greater than the conductivity of the first region 24.
In some embodiments, the thickness of the source contact region 21 and the drain contact region 22 is greater than the thickness of the channel region 23, and in particular, when plasma is implanted along the gate 32 toward the active layer 20 to make the active layer 20 conductive to form the source contact region 21 and the drain contact region 22, since the thickness of the source contact region 21 and the drain contact region 22 is greater than the thickness of the channel region 23, and the gate insulating layer 31 and the gate 32 are located between the two second regions 25, only a portion higher than the thickness of the channel region 23 may be made conductive, for example, only a portion of the upper layer is made conductive, such as the second region 25 in this embodiment, during the conductive process, the gate insulating layer 31 can block lateral diffusion of ions, thereby preventing the plasma from flowing to the channel region 23 and affecting the effective length of the channel region 23, i.e., ensuring performance of the thin film transistor.
In one embodiment, the depth of the conductimerization is less than or equal to the difference in thickness of the source contact region 21 and the drain contact region 22 and the channel region.
Preferably, the thickness of the source contact region 21 and the drain contact region 22 is 60 to 80nm, the thickness of the channel region 23 is 40 to 60nm, and the depth of the electrical conduction is greater than or equal to 10nm and less than or equal to 20nm. In some embodiments, the source contact region 21 and the drain contact region 22 are 60nm thick and the channel region 23 is 40nm thick. In some embodiments the source contact region 21 and the drain contact region 22 are 65nm thick and the channel region 23 is 45nm thick. In some embodiments, the source contact region 21 and the drain contact region 22 are 80nm thick and the channel region 23 is 60nm thick.
In order to solve the above technical problem, an embodiment of the present invention provides an array substrate including the thin film transistor in any of the above embodiments. Illustratively, a plurality of thin film transistors may be included at the same time, such as a switching thin film transistor, a driving thin film transistor, and the like.
The array substrate can also be applied to a display panel, and the display panel can be an OLED display panel, a Micro-LED display panel, a liquid crystal display panel and the like.
The display panel can also be used for any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
To solve the above technical problems, a technical solution adopted in the present application is to provide a method for manufacturing a thin film transistor, please refer to fig. 2, and fig. 2 is a schematic flowchart of an embodiment of the method for manufacturing a thin film transistor according to the present application. The method of the embodiment comprises the following steps:
s101: an active layer 20 is formed on a substrate 10, the active layer 20 includes a source contact region 21, a drain contact region 22 and a channel region 23, the thickness of the source contact region 21 and the drain contact region 22 is greater than the thickness of the channel region 23, the source contact region 21 and the drain contact region 22 are located at opposite sides of the channel region, and the material of the active layer 20 includes an oxide semiconductor.
The material of the substrate 10 may be polyimide, sapphire, glass, or the like.
S102: a gate electrode 32, a source electrode 33, and a drain electrode 34 are formed on the active layer 20.
Specifically, referring to fig. 3 and fig. 4, fig. 3 is a schematic flow chart of an embodiment of a method for manufacturing a thin film transistor of the present application, and fig. 4 is a schematic flow chart of another embodiment of the method for manufacturing a thin film transistor of the present application.
S201: an oxide semiconductor layer is formed on the substrate 10.
Specifically, the material of the active layer 20 includes an oxide semiconductor IGZO (indium gallium zinc oxide). Illustratively, the thickness of the oxide semiconductor layer is 70nm.
S202: the oxide semiconductor layer is subjected to patterning treatment using a halftone mask, and a source contact region, a drain contact region, and a channel region 23 are formed.
The transmittance of the halftone mask corresponding to the channel region 23 is greater than the transmittance of the halftone mask corresponding to the source contact region and the drain contact region, so that the thicknesses of the source contact region and the drain contact region are greater than the thickness of the channel region 23.
Illustratively, a positive photoresist material is coated on the corresponding source and drain contact regions of the oxide semiconductor layer, and then a patterning process is performed using a half-tone mask. After the light etching, the thickness of the etched channel region 23 is larger than the thickness of the source contact region and the drain contact region; for example, the thickness of the channel region 23 may be made 50nm and the thickness of the source and drain contact regions 70nm. The source contact region and the drain contact region are regions patterned by a half-tone mask, and then may be plasma-doped to form a source contact region 21 and a drain contact region 22.
S203: a gate insulating layer 31 and a gate electrode 32 are formed on the patterned active layer 20.
Specifically, a gate insulating layer 31 and a gate electrode 32 are formed on the patterned active layer 20. The gate insulating layer 31 and the gate electrode 32 are stacked on the channel region 23, and the gate insulating layer 31 and the gate electrode 32 have the same width. The gate insulating layer 31 may be made of an insulating material silicon dioxide.
S204: the source contact region and the drain contact region are subjected to a conductor forming process to form a source contact region 21 and a drain contact region 22.
Wherein the source contact region and the drain contact region are plasma treated so that the source contact region and the drain contact region are made conductive. Wherein the depth of the conductivation is less than or equal to the difference in thickness between the source and drain contact regions and the channel region 23.
Specifically, in the process of performing plasma implantation on the active layer 20, plasma treatment may be performed on the source contact region and the drain contact region using the gate electrode 32 or the gate insulating layer above the channel region 23 as a mask, so that the source contact region and the drain contact region are made conductive, and the source contact region 21 and the drain contact region 22 are formed. The width of the gate 32 is greater than or equal to the width of the channel region 23, so that when plasma is implanted from the gate 32 toward the channel region 23, the lateral diffusion of ions can be completely blocked. The gate insulating layer 31 and the gate electrode 32 are formed on the active layer 20, and then the active layer 20 is made conductive, and the gate electrode 32 or the gate insulating layer is used for replacing a mask plate, so that the steps are simplified, and the production efficiency is improved. Meanwhile, by adjusting the plasma implantation process, the depth to which the source and drain contact regions are conducted is made smaller than or equal to the difference in thickness between the source and drain contact regions and the channel region 23. Since the plasma reaches a position not at the same level as the channel region 23 and is further blocked by the gate insulating layer 31, it is possible to prevent the plasma from diffusing laterally into the channel region 23 to shorten the effective length of the channel region 23 and affect the channel region 23.
In some embodiments, the depth of the conductimerization is greater than or equal to 10nm and less than or equal to 20nm. Specifically, the depth of the electrical conduction is only required to meet actual requirements, and the electrical conduction with the drain electrode 34 and the source electrode 33 can be achieved subsequently. Alternatively, the depth of the conductimerization is 10nm, 14nm or 20nm.
S205: a protective layer is formed on the side of the gate electrode 32 remote from the gate insulating layer 31 and a source electrode 33 and a drain electrode 34 are formed on the protective layer, with the source electrode 33 being connected to the source contact region 21 by a via in the protective layer and the drain electrode 34 being connected to the drain contact region 22 by a via in the protective layer.
A protective layer, a source electrode 33 and a drain electrode 34 are formed on the active layer 20 by means of a mask. The source electrode 33 is a part of the source electrode, and the drain electrode 34 is a part of the drain electrode.
Referring to fig. 5, fig. 5 is a schematic flow chart of another embodiment of a method for fabricating a thin film transistor according to the present application.
S301: a first active layer 20a and a second active layer 20b are formed on the substrate 10.
In some embodiments, forming the active layer 20 on the substrate 10 includes: a first active layer 20a and a second active layer 20b are sequentially formed on the substrate 10, and the mobility of the first active layer 20a is less than that of the second active layer 20b.
S302: the second active layer 20b is patterned to form a source contact region 21, a drain contact region 22, and a channel region 23.
The first active layer 20a and the second active layer 20b are both made of an oxide semiconductor. The second active layer 20b is etched through a mask to form a source contact region 21 and a drain contact region 22. The channel region 23 is formed by patterning the first active layer 20a exposed by the second active layer 20b, and the source contact region 21 and the drain contact region 22 are positioned at opposite sides of the channel region 23.
I.e. the source contact region 21 and the drain contact region 22, comprise a first region comprising the first active layer 20a and a second region comprising the second active layer 20b, which are arranged one above the other, so that the source electrode 33 and the drain electrode 34 form a good electrically conductive contact with the source contact region 21 and the drain contact region 22, and therefore the second active layer 20b has a high mobility. By the scheme, the use of a plasma conductor process can be avoided, and the influence on the channel region 23 is avoided.
S303: a gate insulating layer 31 and a gate electrode 32 are formed on the patterned second active layer 20b.
S304: a source electrode 33 and a drain electrode 34 are formed on the protective layer.
A gate insulating layer, a gate electrode 32, a protective layer, a source electrode 33, and a drain electrode 34 are formed on the active layer 20 by means of a mask. The source electrode 33 is a part of the source, and the drain electrode 34 is a part of the drain; specifically, the source electrode 33 is connected to the source contact region 21 through a via hole in the passivation layer to form a source electrode, and similarly, the drain electrode 34 is connected to the drain contact region 22 through a via hole in the passivation layer to form a drain electrode.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A thin film transistor, comprising:
a substrate;
an active layer disposed on the substrate, the active layer including a source contact region, a drain contact region, and a channel region;
the source contact region and the drain contact region are respectively positioned at two opposite sides of the channel region, the thickness of the source contact region and the drain contact region is greater than that of the channel region, and the conduction depth of the source contact region is less than or equal to the thickness difference of the source contact region and the channel region; the drain contact region has a conductor depth less than or equal to the difference in thickness between the source contact region and the channel region.
2. The thin film transistor according to claim 1,
the source electrode contact region and the drain electrode contact region comprise a first region and a second region which are arranged in a stacked mode, the first region is connected with the channel region, the thickness of the first region is equal to that of the channel region, and the mobility of the first region is smaller than that of the second region.
3. The thin film transistor according to claim 1,
the thickness of the source contact region and the drain contact region is 60-80 nm, and the thickness of the channel region is 40-60 nm.
4. An array substrate comprising the thin film transistor according to any one of claims 1 to 3.
5. A method for manufacturing a thin film transistor includes:
forming an active layer on a substrate, wherein the active layer comprises a source contact region, a drain contact region and a channel region, the thickness of the source contact region and the thickness of the drain contact region are greater than that of the channel region, and the conductor depth of the source contact region is less than or equal to the thickness difference between the source contact region and the channel region; the drain contact region has a depth of conduction less than or equal to the difference in thickness between the source contact region and the channel region.
6. The method of manufacturing a thin film transistor according to claim 5, wherein the forming an active layer on a substrate comprises:
forming an oxide semiconductor layer over a substrate;
and carrying out imaging treatment on the oxide semiconductor layer by using a halftone mask plate to form a source electrode contact area, a drain electrode contact area and a channel area, wherein the light transmittance of the halftone mask plate corresponding to the channel area is greater than that of the halftone mask plate corresponding to the source electrode contact area and the drain electrode contact area, so that the thickness of the source electrode contact area and the drain electrode contact area is greater than that of the channel area, and conducting treatment is carried out on the source electrode contact area and the drain electrode contact area to form the source electrode contact area and the drain electrode contact area.
7. The method for manufacturing a thin film transistor according to claim 6, wherein the conducting a conductor treatment to the source contact region and the drain contact region comprises:
plasma treating the source contact region and the drain contact region to render the source contact region and the drain contact region conductive;
wherein the depth of the conductimerization is equal to the difference in thickness of the source and drain contact regions and the channel region.
8. The method for manufacturing a thin film transistor according to claim 7,
the depth of the conductor formation is 10nm or more and 20nm or less.
9. The method for manufacturing a thin film transistor according to claim 6, wherein the conducting a conductor treatment to the source contact region and the drain contact region comprises:
forming a gate insulating layer and a gate electrode on the patterned active layer;
subjecting the source contact region and the drain contact region to plasma treatment so as to render the source contact region and the drain contact region conductive, forming the source contact region and the drain contact region;
wherein a width of the gate insulating layer is greater than or equal to a width of the channel region.
10. The method of manufacturing a thin film transistor according to claim 5, wherein the forming an active layer on a substrate comprises:
sequentially forming a first active layer and a second active layer on the substrate, wherein the mobility of the first active layer is smaller than that of the second active layer;
carrying out patterning treatment on the second active layer to form a source contact region, a drain contact region and a channel region, wherein the source contact region and the drain contact region are positioned on two opposite sides of the channel region; the source contact region and the drain contact region include a first region and a second region which are stacked, the first region includes the first active layer, the second region includes the second active layer, and the channel region includes the first active layer, so that the thickness of the source contact region and the drain contact region is greater than the thickness of the channel region.
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| CN116544245B (en) * | 2023-06-29 | 2023-09-22 | 绵阳惠科光电科技有限公司 | Array substrate, preparation method thereof and display panel |
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