CN114089571B

CN114089571B - Array substrate, manufacturing method and display panel

Info

Publication number: CN114089571B
Application number: CN202111441987.7A
Authority: CN
Inventors: 钟德镇; 苏子芳; 程晓婷
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2024-01-16
Anticipated expiration: 2041-11-30
Also published as: CN114089571A

Abstract

The invention discloses an array substrate, a manufacturing method thereof and a display panel, wherein the array substrate comprises: a substrate; a data line formed on the substrate; the first insulating layer covers the data line and the substrate, and a first via hole is arranged at the position of the first insulating layer corresponding to the data line; the source electrode is electrically connected with the data line through a first via hole, the active layer is connected between the source electrode and the drain electrode, and the drain electrode is electrically connected with the pixel electrode; a gate insulating layer formed on the active layer; the grid electrode and the scanning line are formed on the grid electrode insulating layer, the grid electrode and the active layer are arranged oppositely one by one, and the scanning line is electrically connected with the grid electrode. The array substrate, the manufacturing method and the display panel section provided by the invention have the advantage that the manufacturing cost of the array substrate is reduced.

Description

Array substrate, manufacturing method and display panel

Technical Field

The present invention relates to the field of display devices, and in particular, to an array substrate, a manufacturing method thereof, and a display panel.

Background

Currently, metal oxide TFTs have been receiving attention in a wide range of applications, compared to low temperature polysilicon TFTs and amorphous silicon TFTs, to have advantages of higher electron mobility, high light transmittance, low leakage current, low deposition temperature, low manufacturing cost, and the like. However, in the metal oxide TFT structure, in order to prevent etching damage of the metal oxide back channel, an Etch Stop Layer (ESL) structure is generally used to prevent etching damage of the back channel, but a photomask needs to be added once, and before the S/D (source/drain) electrode of the TFT is fabricated, a conductive process is generally performed to ensure good ohmic contact between the S/D and the semiconductor Layer. In this way, the accumulated alignment deviation of the two-step photolithography process limits the accuracy of the active channel size, which is not beneficial to the "miniaturization" of the TFT device size, and meanwhile, the introduction of an Etch Stop Layer (ESL) structure increases a thin film growth and photolithography process, increases the process complexity and cost, and indirectly reduces the market competitiveness of the metal oxide. In addition, in the conventional in-plane rotation display mode liquid crystal display device, the number of used photomasks is more than 7, which greatly increases the manufacturing cost.

Disclosure of Invention

In view of this, the present invention provides a new array substrate, a manufacturing method and a display panel, wherein the array substrate is manufactured by using 6 masks, so as to save the manufacturing cost of the array substrate.

An array substrate, the array substrate comprising:

a substrate;

a data line formed on the substrate;

the first insulating layer covers the data line and the substrate, and a first via hole is arranged at the position of the first insulating layer corresponding to the data line;

the source electrode is electrically connected with the data line through a first via hole, the active layer is connected between the source electrode and the drain electrode, and the drain electrode is electrically connected with the pixel electrode;

a gate insulating layer formed on the active layer;

the grid electrode and the scanning line are formed on the grid electrode insulating layer, the grid electrode and the active layer are arranged oppositely one by one, and the scanning line is electrically connected with the grid electrode.

In an embodiment of the present invention, the array substrate further includes:

a common signal line formed on the substrate, the common signal line being disposed in the same layer as the data line;

the third insulating layer is provided with a second via hole, and the second via hole penetrates through the third insulating layer to the public signal line;

the public electrode is electrically connected with the public signal line through the second conducting hole.

In an embodiment of the present invention, the data line includes a light blocking portion and a conductive wire portion electrically connected to the light blocking portion, a width of the light blocking portion is greater than a width of the conductive wire portion, and an orthographic projection of the active layer on the substrate is located in an orthographic projection of the light blocking portion on the substrate.

In an embodiment of the present invention, the gate is located directly above the active layer and is electrically connected to the scan line.

The invention also relates to a manufacturing method of the array substrate, which comprises the following steps:

providing a substrate;

forming a first metal layer on a substrate, and etching and patterning the first metal layer to form a data line on the first metal layer;

forming a first insulating layer covering the data line on the substrate, etching and patterning the first insulating layer to form a first via hole on the first insulating layer at a position corresponding to the data line, wherein the data line is exposed through the first via hole;

forming a metal oxide semiconductor layer on the first insulating layer, etching and patterning the metal oxide semiconductor layer to form a source electrode, an active layer, a drain electrode and a pixel electrode on the metal oxide semiconductor layer, wherein the active layer is positioned between the source electrode and the drain electrode, the source electrode is filled in the first conducting hole and is electrically connected with the data line, and the drain electrode is electrically connected with the pixel electrode;

sequentially forming a second insulating layer and a second metal layer which cover a source electrode, an active layer, a drain electrode and a pixel electrode on the first insulating layer, firstly carrying out etching patterning on the second metal layer to enable the second metal layer to form a grid electrode and a scanning line, enabling the grid electrode to be positioned right above the active layer and electrically connected with the scanning line, then carrying out etching patterning on the second insulating layer by taking the grid electrode and the scanning line as masks to enable the second insulating layer at the position covered by the grid electrode and the scanning line to be reserved to form a grid insulating layer, and exposing the source electrode, the drain electrode and the pixel electrode at the moment;

and conducting the exposed source electrode, drain electrode and pixel electrode to convert the source electrode, drain electrode and pixel electrode from semiconductor into conductor.

In an embodiment of the present invention, the above manufacturing method further includes:

forming a third insulating layer covering the gate electrode, the scan line, the source electrode, the drain electrode, and the pixel electrode;

and forming a transparent conductive layer on the third insulating layer, and etching and patterning the transparent conductive layer to form a common electrode on the transparent conductive layer.

when the first metal layer is etched and patterned, the first metal layer also forms a common signal line;

after forming the third insulating layer covering the gate electrode, the scanning line, the source electrode, the drain electrode, and the pixel electrode, etching and patterning the third insulating layer to form a second via hole in a position corresponding to the common signal line, the common signal line being exposed through the second via hole;

and when the transparent conductive layer forms a common electrode, filling part of the common electrode into the second conducting hole to be electrically connected with the common signal line.

In an embodiment of the present invention, the above-described conductive treatment includes a hydrogenation treatment or an ion doping treatment.

The invention also relates to a display panel comprising the array substrate.

The array substrate and the manufacturing method thereof adopt a photomask process to enable the metal oxide semiconductor layer to form a whole surface of source electrode, drain electrode, active layer and pixel electrode at the same time. Wherein the source, drain and pixel electrodes are subjected to a conductor treatment such that the source, drain and pixel electrodes are changed from semiconductor to conductor. Therefore, a mask is not required to be used alone to define the source electrode, the drain electrode, the active layer or the pixel electrode. Meanwhile, the source electrode, the drain electrode and the active layer are in a whole surface shape, so that the contact conduction effect between the source electrode, the drain electrode and the active layer is better. In addition, after the second metal layer forms the grid electrode and the scanning line by adopting a photomask process, the grid electrode and the scanning line are used as masks to form the grid electrode insulating layer, so that a photomask for manufacturing the grid electrode insulating layer is saved. Therefore, the array substrate and the manufacturing method thereof save cost and ensure better contact and conduction effects between the source electrode, the drain electrode and the active layer.

Drawings

FIG. 1 is a schematic cross-sectional view of a method for fabricating an array substrate according to the present invention;

FIG. 2 is a schematic plan view of a method for fabricating an array substrate according to the present invention;

FIG. 3 is a schematic cross-sectional view of the array substrate shown in FIG. 2 along A-A;

fig. 4 to 6 are schematic cross-sectional views of a method for manufacturing an array substrate according to the present invention;

FIG. 7 is a schematic plan view of a method for fabricating an array substrate according to the present invention;

FIG. 8 is a schematic cross-sectional view of the array substrate shown in FIG. 7 along the B-B direction;

fig. 9 to 11 are schematic cross-sectional views of a method for manufacturing an array substrate according to the present invention;

FIG. 12 is a schematic plan view of a method for fabricating an array substrate according to the present invention;

FIG. 13 is a schematic cross-sectional view of the array substrate shown in FIG. 12 along the direction C-C;

fig. 14 to 16 are schematic cross-sectional views of a method for manufacturing an array substrate according to the present invention;

FIG. 17 is a schematic plan view of a method for fabricating an array substrate according to the present invention;

FIG. 18 is a schematic cross-sectional structure of the array substrate shown in FIG. 17 along the D-D direction;

fig. 19 is a schematic cross-sectional view of a manufacturing method of an array substrate according to the present invention.

Detailed Description

For the convenience of understanding of those skilled in the art, the following examples are provided to illustrate specific implementation procedures of the technical solutions provided in the present application.

As shown in fig. 1 to 19, the present invention provides a method for manufacturing an array substrate, which includes:

s1: providing a substrate 11; the substrate 11 may be made of glass, quartz, acrylic, polycarbonate, or the like.

As shown in fig. 1 to 3, a first metal layer 12 is formed on a substrate 11, and the first metal layer 12 is etched and patterned to form a data line 121 on the first metal layer 12. The first metal layer 12 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo). In the present embodiment, after depositing and forming the first metal layer 12 on the substrate 11, etching and patterning the first metal layer 12 includes: coating a photoresist layer on the surface of the first metal layer 12; then, exposing the photoresist on the surface of the first metal layer 12 by using a first mask plate; removing the photoresist at the exposed part by using a developing solution, and leaving the unexposed photoresist; etching the first metal layer 12 not covered by the photoresist to form a data line 121; finally, the unexposed photoresist is removed.

S2: as shown in fig. 4 and 5, a first insulating layer 13 covering the data lines 121 is formed on the substrate 11, and the first insulating layer 13 is etched and patterned such that the first insulating layer 13 forms first via holes 101 at positions corresponding to the data lines 121, and the data lines 121 are exposed through the first via holes 101. The first insulating layer 13 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both, for example. In the present embodiment, etching patterning the first insulating layer 13 includes: coating a photoresist layer on the surface of the first insulating layer 13; then exposing the photoresist on the surface of the first insulating layer 13 by using a second mask plate; removing the photoresist at the exposed part by using a developing solution, and leaving the unexposed photoresist; dry etching is performed on the first insulating layer 13 which is not covered by the photoresist to form a first via hole 101, so that the data line 121 can be exposed from the first via hole 101; finally, the unexposed photoresist is removed to expose the first insulating layer 13 and the data line 121 corresponding to the via hole.

S3: as shown in fig. 6 to 8, a metal oxide semiconductor layer 14 is formed on the first insulating layer 13, the metal oxide semiconductor layer 14 is etched and patterned, so that the metal oxide semiconductor layer 14 forms a source 141, an active layer 142, a drain 143 and a pixel electrode 144, the active layer 142 is located between the source 141 and the drain 143, the source 141 is filled in the first via hole 101 and is electrically connected to the data line 121, and the drain 143 is electrically connected to the pixel electrode 144. In the present embodiment, the metal oxide semiconductor layer 14 is made of an indium gallium zinc oxide material, and etching and patterning the metal oxide semiconductor layer 14 includes: coating a photoresist layer on the surface of the metal oxide semiconductor layer 14; then, exposing the photoresist on the surface of the metal oxide semiconductor layer 14 by using a third mask plate; removing the photoresist at the exposed part by using a developing solution, and leaving the unexposed photoresist; etching the metal oxide semiconductor layer 14 not covered with the photoresist to form a source electrode 141, an active layer 142, a drain electrode 143 and a pixel electrode 144; finally, the unexposed photoresist is removed to expose the source electrode 141, the active layer 142, the drain electrode 143, and the pixel electrode 144. Among them, the source electrode 141, the active layer 142, the drain electrode 143, and the pixel electrode 144, which are formed by etching patterning the metal oxide semiconductor layer 14, are in a whole block shape, and thus contact conduction between the source electrode 141 and the active layer 142 is better.

S4: as shown in fig. 9 to 11, the second insulating layer 15 and the second metal layer 16 covering the source electrode 141, the active layer 142, the drain electrode 143 and the pixel electrode 144 are sequentially formed on the first insulating layer 13, the second metal layer 16 is etched and patterned to form the gate electrode 161 and the scan line 162, the gate electrode 161 is located directly above the active layer 142 and the gate electrode 161 is electrically connected to the scan line 162, and then the second insulating layer 15 is etched and patterned by using the gate electrode 161 and the scan line 162 as a mask, so that the second insulating layer 15 at the position covered by the gate electrode 161 and the scan line 162 is kept to form the gate insulating layer 151, and the second insulating layer 15 at the position in the remaining surface is removed, at this time, the source electrode 141, the drain electrode 143 and the pixel electrode 144 are exposed. The second insulating layer 15 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both, and the second metal layer 16 is made of, for example, copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo). In this embodiment, etching the second metal layer 16 includes: coating a photoresist layer on the surface of the second metal layer 16; then, exposing the photoresist on the surface of the second metal layer 16 by using a fourth mask plate; removing the photoresist at the exposed part by using a developing solution, and leaving the unexposed photoresist; etching the second metal layer 16 not covered by the photoresist to form a gate electrode 161 and a scan line 162; finally, the unexposed photoresist is removed to expose the gate electrode 161 and the scan line 162. In addition, when the second insulating layer 15 is etched and patterned by using the gate electrode 161 and the scanning line 162 as masks, the second insulating layer 15 needs to be etched by dry etching, and other metals can be prevented from being corroded during the etching of the second insulating layer 15.

Further, as shown in fig. 12 and 13, the exposed source 141, drain 143, and pixel electrode 144 are subjected to a conductor treatment, so that the source 141, drain 143, and pixel electrode 144 are converted from semiconductors to conductors. In this embodiment, the conductive treatment includes a hydrogenation treatment or a hydrogen ion doping treatment.

S5: as shown in fig. 14 and 15, the third insulating layer 17 is formed to cover the gate electrode 161, the scan line 162, the source electrode 141, the drain electrode 143, and the pixel electrode 144. The third insulating layer 17 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. In this embodiment, when the first metal layer 12 is etched and patterned, the first metal layer 12 is further formed with a common signal line 122; after forming the third insulating layer 17 covering the gate electrode 161, the scan line 162, the source electrode 141, the drain electrode 143 and the pixel electrode 144, the third insulating layer 17 is etched and patterned by a fifth photomask process, so that the second via hole 102 is formed in the third insulating layer 17 and the first insulating layer 13 at a position corresponding to the common signal line 122, and the common signal line 122 is exposed through the second via hole 102 for electrical connection with the common electrode 181 in a subsequent process. In other embodiments, the common signal line 122 connected to the common electrode 181 may not be formed when the first metal layer 12 is etched and patterned, for example, the common signal line 122 may be disposed on another metal layer.

S6: as shown in fig. 16 to 19, a transparent conductive layer 18 is formed on the third insulating layer 17, and the transparent conductive layer 18 is etched and patterned so that the transparent conductive layer 18 forms a common electrode 181. The transparent conductive layer 18 is made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In this embodiment, the transparent conductive layer 18 is Indium Tin Oxide (ITO), and the sixth photomask process is used to etch and pattern the transparent conductive layer 18, so that when the transparent conductive layer 18 forms the common electrode 181, a portion of the common electrode 181 is filled into the second via hole 102 and electrically connected to the common signal line 122.

The array substrate and the manufacturing method thereof adopt a photomask process to enable the metal oxide semiconductor layer 14 to simultaneously form the whole source electrode 141, the drain electrode 143, the active layer 142 and the pixel electrode 144. Wherein the source electrode 141, the drain electrode 143, and the pixel electrode 144 are subjected to a conductive process such that the source electrode 141, the drain electrode 143, and the pixel electrode 144 are changed from semiconductors to conductors. Therefore, it is not necessary to define the source electrode 141, the drain electrode 143, the active layer 142, or the pixel electrode 144 using a single mask. Meanwhile, the source electrode 141, the drain electrode 143 and the active layer 142 are in a whole plane shape, so that the contact conduction effect between the source electrode 141, the drain electrode 143 and the active layer 142 is better. In addition, after the gate electrode 161 and the scan line 162 are formed on the second metal layer 16 by using a photomask process, the gate insulating layer 151 is formed by using the gate electrode 161 and the scan line 162 as masks, thereby saving a photomask for manufacturing the gate insulating layer 151. Therefore, the array substrate and the manufacturing method thereof save cost and further have better contact and conduction effects between the source electrode 141, the drain electrode 143 and the active layer 142.

The invention also provides an array substrate, which comprises:

the substrate 11, the substrate 11 may be made of glass, quartz, acrylic, polycarbonate, or the like.

As shown in fig. 2 and 3, the data line 121 formed on the substrate 11; the data line 121 may be made of copper and molybdenum niobium (Cu/MoNb) or copper and molybdenum (Cu/Mo).

As shown in fig. 5, a first insulating layer 13 is disposed on the data line 121 and the substrate 11, and a first via hole 101 is disposed on the first insulating layer 13 corresponding to the data line 121, wherein the first insulating layer 13 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two. In this embodiment, the first via hole 101 does not need to correspond to the entire data line 121, and the size of the first via hole 101 only needs to be enough to electrically connect the data line 121 and the source electrode 141, and other portions of the data line 121 are still covered by the first insulating layer 13.

As shown in fig. 7 and 8, the source electrode 141, the active layer 142, the drain electrode 143 and the pixel electrode 144 are formed on the first insulating layer 13, the source electrode 141 is electrically connected to the data line 121 through the first via hole 101, the active layer 142 is connected between the source electrode 141 and the drain electrode 143, and the drain electrode 143 is electrically connected to the pixel electrode 144. The source electrode 141, the active layer 142, the drain electrode 143 and the pixel electrode 144 are made of an indium gallium zinc oxide material and are located on the same layer, wherein the source electrode 141, the active layer 142, the drain electrode 143 and the pixel electrode 144 are of an integrated structure, and the contact effect among the source electrode 141, the active layer 142, the drain electrode 143 and the pixel electrode 144 can be better.

As shown in fig. 11, a gate insulating layer 151 is formed on the active layer 142, and the gate insulating layer 151 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. The orthographic projection of the active layer 142 on the substrate 11 is located in the orthographic projection of the gate insulating layer 151 on the substrate 11, so as to ensure that the gate insulating layer 151 completely covers the active layer 142, and can protect the active layer 142 from being affected by etching in the subsequent process.

The gate electrode 161 and the scan line 162 are formed on the gate insulating layer 151, the gate electrode 161 and the active layer 142 are disposed to face each other, and the scan line 162 is electrically connected to the gate electrode 161. In this embodiment, the scan lines 162 and the data lines 121 are disposed in different layers, so that even though the scan lines 162 and the data lines 121 are disposed to cross each other, the data lines 121 can be continuous data lines 121, i.e. the scan lines 162 and the data lines 121 disposed in the same layer are disposed, and no data line bridging layer is required to cross each scan line 162 to prevent short circuit.

Further, as shown in fig. 14, the array substrate further includes: the third insulating layer 17 covering the source electrode 141, the gate electrode 161, the scan line 162, the drain electrode 143, and the pixel electrode 144 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

As shown in fig. 17 to 19, a common electrode 181 is formed on the third insulating layer 17, and the common electrode 181 is made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In the present embodiment, for a plurality of pixels on an array substrate; a part of the pixels may share one common electrode 181, or all the pixels may share one common electrode 181.

Further, the array substrate further includes:

the common signal line 122 formed on the substrate 11 is disposed on the same layer as the data line 121, so that the common signal line 122 and the data line 121 can be manufactured by the same photomask process, thereby saving cost.

As shown in fig. 15 and 19, the third insulating layer 17 is provided with a second via hole 102, and the second via hole 102 penetrates through the third insulating layer 17 to the common signal line 122. The common electrode 181 is electrically connected to the common signal line 122 through the second via hole 102.

Further, the common electrode 181 may be multiplexed as a touch electrode, and the common signal line 122 may be multiplexed as a touch signal line. Based on this, in the display stage, the common signal line 122 supplies a common signal to the common electrode 181, and supplies a signal required for the common electrode 181 at the time of display; in the touch stage, the common signal line 122 is multiplexed into a touch signal line, a touch signal is provided to the common electrode 181, the common electrode 181 is multiplexed into a touch electrode, a touch driving signal is provided, and a touch feedback signal is received. Therefore, when the common electrode 181 may be multiplexed as a touch electrode and the common signal line 122 may be multiplexed as a touch signal line, the thickness of the array substrate is reduced, and when the array substrate is applied to a touch display panel, the thickness of the touch display panel is reduced.

Further, as shown in fig. 2, the data line 121 includes a light blocking portion 1211 and a conductive line portion 1212 electrically connected to the light blocking portion 1211, wherein a width of the light blocking portion 1211 is larger than a width of the conductive line portion 1212, and an orthographic projection of the active layer 142 on the substrate 11 is located within an orthographic projection of the light blocking portion 1211 on the substrate 11. In this embodiment, since the orthographic projection of the active layer 142 on the substrate 11 is located in the orthographic projection of the light blocking portion 1211 on the substrate 11, that is, the active layer 142 is blocked by the light blocking portion 1211 of the data line 121, there is no need to separately provide a metal layer to block the active layer 142, so that the active layer 142 is prevented from being illuminated, and the performance of the array substrate is further affected.

The invention also provides a display panel comprising the array substrate.

In this document, terms such as up, down, left, right, front, rear, etc. are defined by the positions of the structures in the drawings and the positions of the structures with respect to each other, for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of directional terms should not be construed to limit the scope of the application as claimed. It should also be understood that the terms "first" and "second," etc., as used herein, are used merely for distinguishing between names and not for limiting the number and order.

The present invention is not limited to the preferred embodiments, but is capable of modification and variation in detail, and other modifications and variations can be made by those skilled in the art without departing from the scope of the present invention.

Claims

1. An array substrate, characterized in that the array substrate comprises:

a substrate (11);

a data line (121) formed on the substrate (11), the data line (121) including a light blocking portion (1211) and a wire portion (1212), the light blocking portion (1211) having a width greater than that of the wire portion (1212), the light blocking portion (1211) including a middle portion electrically connected to the wire portion (1212) in an extending direction of the wire portion (1212) and two protruding portions located at both sides of the middle portion, the two protruding portions protruding outwardly from both side edges of the wire portion (1212), respectively;

a first insulating layer (13) covering the data line (121) and the substrate (11), wherein a first via hole (101) is arranged at a position of the first insulating layer (13) corresponding to one of the protruding parts of the light blocking part (1211);

the source electrode (141), the active layer (142), the drain electrode (143) and the pixel electrode (144) are formed on the first insulating layer (13), wherein the source electrode (141), the active layer (142), the drain electrode (143) and the pixel electrode (144) are formed by a metal oxide semiconductor layer at the same time by adopting a photomask process, the active layer (142) is a semiconductor, the source electrode (141), the drain electrode (143) and the pixel electrode (144) are changed into conductors from the semiconductor after being subjected to the conductor treatment, the source electrode (141) is electrically connected with the data line (121) through the first via hole (101), the active layer (142) is connected between the source electrode (141) and the drain electrode (143), and the drain electrode (143) is electrically connected with the pixel electrode (144); an orthographic projection of the active layer (142) on the substrate (11) is positioned in an orthographic projection of the light blocking portion (1211) on the substrate (11) and above the intermediate portion and the other protruding portion where the first via hole (101) is not provided;

a gate insulating layer (151) formed on the active layer (142);

and the grid electrode (161) and the scanning line (162) are formed on the grid electrode insulating layer (151), the grid electrode (161) and the active layer (142) are arranged in a one-to-one opposite mode, and the scanning line (162) is electrically connected with the grid electrode (161).

2. The array substrate of claim 1, further comprising:

a third insulating layer (17) covering the source electrode (141), the gate electrode (161), the scanning line (162), the drain electrode (143), and the pixel electrode (144);

and a common electrode (181) formed on the third insulating layer (17).

3. The array substrate of claim 2, further comprising:

a common signal line (122) formed on the substrate (11), the common signal line (122) being disposed in the same layer as the data line (121);

the third insulating layer (17) is provided with a second via hole (102), and the second via hole (102) penetrates through the third insulating layer (17) to the public signal line (122);

the common electrode (181) is electrically connected with the common signal line (122) through the second via hole (102).

4. The array substrate of claim 1, wherein the gate electrode (161) is located directly above the active layer (142) and the gate electrode (161) is electrically connected to the scan line (162).

5. The manufacturing method of the array substrate is characterized by comprising the following steps of:

providing a substrate (11);

forming a first metal layer (12) on the substrate (11), etching and patterning the first metal layer (12), so that the first metal layer (12) forms a data line (121), wherein the data line (121) comprises a light blocking part (1211) and a wire part (1212), the width of the light blocking part (1211) is larger than that of the wire part (1212), the light blocking part (1211) comprises a middle part and two protruding parts positioned at two sides of the middle part, the middle part is electrically connected with the wire part (1212) in the extending direction of the wire part (1212), and the two protruding parts respectively extend outwards from two side edges of the wire part (1212);

forming a first insulating layer (13) covering the data line (121) on the substrate (11), etching and patterning the first insulating layer (13) to form a first via hole (101) at a position corresponding to one of the protruding parts of the light blocking part (1211), wherein the data line (121) is exposed through the first via hole (101);

forming a metal oxide semiconductor layer (14) on the first insulating layer (13), etching and patterning the metal oxide semiconductor layer (14), so that the metal oxide semiconductor layer (14) forms a source electrode (141), an active layer (142), a drain electrode (143) and a pixel electrode (144), wherein the active layer (142) is positioned between the source electrode (141) and the drain electrode (143), the source electrode (141) is filled in the first via hole (101) and is electrically connected with the data line (121), and the drain electrode (143) is electrically connected with the pixel electrode (144); an orthographic projection of the active layer (142) on the substrate (11) is positioned in an orthographic projection of the light blocking portion (1211) on the substrate (11) and above the intermediate portion and the other protruding portion where the first via hole (101) is not provided;

sequentially forming a second insulating layer (15) and a second metal layer (16) on the first insulating layer (13) to cover the source electrode (141), the active layer (142), the drain electrode (143) and the pixel electrode (144), etching and patterning the second metal layer (16) to enable the second metal layer (16) to form a grid electrode (161) and a scanning line (162), wherein the grid electrode (161) is positioned right above the active layer (142) and is electrically connected with the scanning line (162), etching and patterning the second insulating layer (15) by taking the grid electrode (161) and the scanning line (162) as masks, and enabling the second insulating layer (15) at the position covered by the grid electrode (161) and the scanning line (162) to remain to form a grid insulating layer (151), and at the moment, the source electrode (141), the drain electrode (143) and the pixel electrode (144) are exposed;

the exposed source electrode (141), drain electrode (143) and pixel electrode (144) are subjected to a conductor treatment, and the source electrode (141), drain electrode (143) and pixel electrode (144) are converted from a semiconductor into a conductor.

6. The method for manufacturing an array substrate according to claim 5, further comprising:

forming a third insulating layer (17) covering the gate electrode (161), the scan line (162), the source electrode (141), the drain electrode (143), and the pixel electrode (144);

a transparent conductive layer (18) is formed on the third insulating layer (17), and the transparent conductive layer (18) is etched and patterned so that the transparent conductive layer (18) forms a common electrode (181).

7. The method for manufacturing an array substrate according to claim 6, further comprising:

when the first metal layer (12) is etched and patterned, the first metal layer (12) is further formed with a common signal line (122);

after forming the third insulating layer (17) covering the gate electrode (161), the scanning line (162), the source electrode (141), the drain electrode (143), and the pixel electrode (144), etching and patterning the third insulating layer (17) so that the third insulating layer (17) and the first insulating layer (13) form a second via hole (102) at a position corresponding to the common signal line (122), the common signal line (122) being exposed through the second via hole (102);

when the transparent conductive layer (18) is formed into a common electrode (181), a part of the common electrode (181) is filled into the second via hole (102) and is electrically connected with the common signal line (122).

8. The method according to claim 5, wherein the conductive treatment comprises a hydrogenation treatment or an ion doping treatment.

9. A display panel comprising the array substrate of any one of claims 1 to 4.