CN113782616B - Thin film transistor, preparation method thereof, array substrate and display device - Google Patents
Thin film transistor, preparation method thereof, array substrate and display device Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- General Physics & Mathematics (AREA)
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- Crystallography & Structural Chemistry (AREA)
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- Thin Film Transistor (AREA)
Abstract
The invention provides a thin film transistor, a preparation method thereof, an array substrate and a display device, belongs to the technical field of display, and can solve the problems that an active layer loses the semiconductor performance or the distribution uniformity of TFT channel length on the substrate is poor due to the existing conductive treatment. The preparation method of the thin film transistor comprises the step of forming a via hole on one side of the conductive region adjacent to the semiconductor region, wherein the via hole can prevent the conductive region from diffusing to the semiconductor region, and can prevent the middle part of the active layer from being diffused to form a conductor.
Description
The application is 201910024065.2 and 2019 and 01
The invention relates to a thin film transistor and a preparation method thereof, an array substrate and a display device, which are applied for 10 days.
Technical Field
The invention belongs to the technical field of display, and particularly relates to a thin film transistor, a preparation method thereof, an array substrate and a display device.
Background
With the increasing size of displays, amorphous silicon thin film transistors have problems of insufficient electron mobility and poor uniformity, and in order to solve the above problems, a technology of using an oxide semiconductor material such as IGZO, ITZO, IZO instead of amorphous silicon as an active layer has been developed.
When the thin film transistor (Thin Film Transistor, abbreviated as TFT) is manufactured, in order to ensure that the source electrode and the drain electrode (S/D) in the TFT are well contacted with the IGZO, the S/D overlap impedance is reduced, the performance of the TFT is improved, and the edge of the active layer is required to be subjected to conductive treatment at the position where the active layer is contacted with the source electrode and the drain electrode.
The inventor finds that at least the following problems exist in the prior art: after the edge of the active layer is subjected to the conductive treatment, the problem of conductive diffusion cannot be avoided, and the conductive diffusion can cause the middle part of the active layer to be diffused to form a conductor, lose the semiconductor performance or cause poor uniformity of the distribution of the TFT channel length on the substrate.
Disclosure of Invention
The invention provides a thin film transistor, a preparation method thereof, an array substrate and a display device, aiming at the problems that the existing conductive treatment can cause the active layer to lose the semiconductor performance or the TFT channel length is distributed on the substrate with poor uniformity.
The technical scheme adopted for solving the technical problems of the invention is as follows:
a preparation method of a thin film transistor comprises the steps of forming an oxide active layer on a substrate, and a source electrode and a drain electrode, wherein the oxide active layer comprises a conductive region and a semiconductor region which are connected, and the source electrode and the drain electrode are electrically connected with the conductive region;
the method further includes the step of forming a via on a side of the semiconductive region adjacent to the semiconductor region.
Optionally, the forming the oxide active layer specifically includes the following steps:
forming a pattern of oxide semiconductor material on a substrate and including a via, the pattern of oxide semiconductor material including a conductive region and a semiconductor region connected, the via being located on a side of the conductive region adjacent to the semiconductor region;
and conducting the oxide semiconductor material of the conducting area to obtain the oxide active layer.
Optionally, the conducting treatment of the conductive region includes hydrogenation or deoxidation of the oxide semiconductor material of the conductive region by means of ion bombardment.
Optionally, the forming the oxide active layer, and the source electrode and the drain electrode specifically include the steps of:
forming an oxide active layer over a substrate;
forming a gate insulating layer on the substrate on which the above steps are completed;
forming a gate electrode on the substrate on which the above steps are completed;
forming an interlayer insulating layer on the substrate having completed the above steps;
and forming a source electrode and a drain electrode on the substrate which completes the steps.
Optionally, the via hole includes a sidewall, wherein the sidewall far from the semiconducting region is a first sidewall; the source and drain electrodes cover at least a portion of the first sidewall.
The invention also provides a thin film transistor, which comprises a substrate, an oxide active layer arranged above the substrate, and a source electrode and a drain electrode, wherein the oxide active layer comprises a conductive area and a semiconductor area which are connected, and the source electrode and the drain electrode are electrically connected with the conductive area; and a via hole is formed in one side, close to the semiconductor region, of the conductive region.
Optionally, the conductive region is formed by hydrogenation or deoxidation of the same oxide semiconductor material as the semiconductor region.
Optionally, the conductive region forms a side surface at the via hole, wherein the side surface far away from the semiconductor region is a first side surface; the source and drain electrode cover at least part of the first side surface.
Optionally, the thin film transistor is a top gate type.
The invention also provides an array substrate comprising the thin film transistor.
The invention also provides a display device comprising the array substrate.
Drawings
Fig. 1 is a schematic structural diagram of a thin film transistor according to embodiment 1 of the present invention;
fig. 2 is a schematic flow chart of a thin film transistor according to embodiment 2 of the present invention;
fig. 3 is a schematic view illustrating the formation of an active layer of a thin film transistor according to embodiment 2 of the present invention;
fig. 4 is a schematic view showing the formation of the source and drain electrodes of the thin film transistor according to embodiment 2 of the present invention;
fig. 5 is a schematic structural diagram of a thin film transistor according to embodiment 3 of the present invention;
fig. 6 is another schematic structural diagram of a thin film transistor according to embodiment 3 of the present invention;
wherein, the reference numerals are as follows: 1. a substrate; 11. a protective layer; 12. a buffer layer; 2. an oxide active layer; 21. a conductive region; 22. a semiconductor region; 23. a via hole; 3. a source electrode and a drain electrode; 4. a gate insulating layer; 5. a gate; 6. an interlayer insulating layer; 7. and (3) photoresist.
Detailed Description
The present invention will be described in further detail below with reference to the drawings and detailed description for the purpose of better understanding of the technical solution of the present invention to those skilled in the art.
Example 1:
the present embodiment provides a method for manufacturing a thin film transistor, as shown in fig. 1, including the steps of forming an oxide active layer 2 on a substrate 1, and a source electrode and a drain electrode, wherein the oxide active layer 2 includes a conductive region 21 and a semiconductor region 22 connected to each other, and the source electrode and the drain electrode are electrically connected to a first conductive region 211 of the conductive region 21; the method further comprises the step of forming a via between the first and second semiconducting regions 211, 212 of the semiconducting region 21, i.e. the step of forming a via 23 at the side of the semiconducting region 21 adjacent to the semiconductor region 22.
The method for manufacturing the thin film transistor of the embodiment includes the step of forming the via hole 23 on one side of the conductive region 21 adjacent to the semiconductor region 22, wherein the via hole 23 can prevent the conductive region 21 from diffusing into the semiconductor region 22, so that the middle part of the active layer can be prevented from being diffused to form a conductor, and the two sides of the via hole are adjacent to the conductive region 21, thereby improving the uniformity of manufacturing the via hole 23.
Example 2:
the embodiment provides a preparation method of a thin film transistor, as shown in fig. 2-4, comprising the following preparation steps:
optionally, S01, forming a patterned protective layer 11 on the substrate 1, and a buffer layer 12 covering the protective layer 11; the substrate 1 may be made of a transparent material such as glass, and is preliminarily cleaned. The buffer layer 12 may have a single layer structure or a stacked structure of a plurality of sub-layers, and the buffer layer 12 may be formed using silicon oxide or silicon nitride. Specifically, the buffer layer 12 may be formed by a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method, or a sputtering method.
S02, forming an oxide active layer 2 on the substrate 1 after the steps are completed; wherein the oxide active layer 2 includes a conductive region 21 and a semiconductor region 22 connected; specifically, S02 includes:
s02a, forming a pattern of oxide semiconductor material and including a via 23 on the substrate 1 after the above steps are completed by a one-step patterning process, wherein the pattern of oxide semiconductor material includes a conductive region 21 and a semiconductor region 22 connected to each other, the conductive region 21 includes a first conductive region 211 and a second conductive region 212, and the via 23 is disposed between the first conductive region 211 and the second conductive region 212, and the via 23 is located on one side of the conductive region 21 adjacent to the semiconductor region 22; specifically, as shown in fig. 3, a layer of photoresist 7 may be formed on an oxide semiconductor material, the photoresist 7 may be exposed and developed, and then dry etched to form a pattern including an active layer and a via 23.
S02b, conducting the oxide semiconductor material of the conducting region 21 to obtain the oxide active layer 2.
As an alternative to this embodiment, the conducting treatment of the conducting region 21 includes hydrogenation or oxidation of the oxide semiconductor material of the conducting region 21 by means of ion bombardment.
In this embodiment, the via 23 is formed first and then the conductive layer is formed, so that diffusion of hydrogen atoms in the conductive layer can be avoided to a greater extent, where the via 23 can be formed with the active layer by a one-step mask.
As a preferred solution of the present embodiment, as shown in fig. 5 and 6, the first conductive region 211 forms a first sidewall 213 near the source and drain electrodes 3, and the second conductive region 212 forms a second sidewall 214 far from the semiconductor region 22, where the first sidewall 213 and the second sidewall 214 together form the via 23; the source and drain electrodes 3 cover at least part of the first sidewall 213.
This is equivalent to increasing the overlap contact area between the source and drain electrodes and the side surface of the via hole 23 of the conductive region 21, which is more favorable for electron transport.
S03, forming a gate insulating layer 4 on the substrate 1 after the steps are completed; specifically, the gate insulating layer 4 may be formed over the active layer by a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or an electron cyclotron resonance chemical vapor deposition method, or a sputtering method.
S04, forming a grid electrode 5 on the substrate 1 after the steps are completed; the gate 5 may be formed of at least one material of molybdenum, molybdenum-niobium alloy, aluminum-neodymium alloy, titanium, or copper. Specifically, the gate metal electrode film may be formed by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition.
S05, forming an interlayer insulating layer 6 on the substrate 1 after the steps are completed; the interlayer insulating layer 6 may be formed of silicon oxide, silicon nitride, hafnium oxide, or aluminum oxide.
S06, forming a source and a drain 3 on the substrate 1 after the above steps, wherein the source and the drain 3 are electrically connected to the first conductive region 211 of the conductive region 21. The source electrode and the drain electrode are formed by at least one material selected from molybdenum, molybdenum-niobium alloy, aluminum-neodymium alloy, titanium or copper. As shown in fig. 4, a photoresist 7 may be formed on the conductive material layer, the photoresist 7 may be exposed and developed, and then etched to form a pattern including the source and drain electrodes 3.
The method for manufacturing the thin film transistor of the embodiment includes forming the via hole 23 on one side of the conductor region adjacent to the semiconductor region 22 before the conductor is formed, the via hole 23 can prevent the conductor region 21 from diffusing to the semiconductor region 22, effectively prevent the middle part of the active layer from being diffused to form a conductor, and the two sides of the via hole 23 are adjacent to the conductor region 21, so that the uniformity of manufacturing the via hole is improved. When the SD bonding is performed subsequently, the source electrode and the drain electrode 3 cover at least part of the first sidewall of the via hole 23, which is equivalent to increasing the contact area, and can effectively reduce the bonding resistance and improve the conductivity. The TFT prepared by the method has better uniformity.
In the drawings corresponding to the present embodiment, the sizes, thicknesses, and the like of the respective structural layers are shown only as illustrations. In the process implementation, the projection areas of the structural layers on the substrate 1 can be the same or different, and the required projection areas of the structural layers can be realized through an etching process; meanwhile, the structure shown in the drawings does not limit the geometric shape of each structural layer, for example, the structure can be rectangular as shown in the drawings, trapezoid or other etched shapes, and the structure can be realized by etching.
Example 3:
the present embodiment provides a thin film transistor, as shown in fig. 5, which includes a substrate 1, an oxide active layer 2 disposed over the substrate 1, and a source electrode and a drain electrode 3, wherein the oxide active layer 2 includes a conductive region 21 and a semiconductor region 22 connected to each other, the conductive region 21 includes a first conductive region 211 and a second conductive region 212, and the source electrode and the drain electrode 3 are electrically connected to the first conductive region 211 of the conductive region 21; a via 23 is disposed between the first conductive region 211 and the second conductive region 212, that is, the conductive region 21 is disposed with the via 23 on a side close to the semiconductor region 22.
In the thin film transistor of the present embodiment, the via hole 23 is disposed on the side of the conductive region 21 adjacent to the semiconductor region 22, and since the second conductive region 212 is disposed close to the semiconductor region 22, the via hole 23 is disposed between the first conductive region 211 and the second conductive region 212, so that the via hole 23 can prevent the conductive region 21 from diffusing into the semiconductor region 22, and can prevent the middle portion of the active layer from being diffused to form a conductor, and the two sides of the via hole 23 are adjacent to the conductive region 21, thereby improving the uniformity of via hole fabrication. Further, since the width of the first conductive region 211 is not equal to the width of the second conductive region 212, and optionally the width of the first conductive region 211 is greater than the width of the second conductive region 212, the influence of the second conductive region 212 on the middle of the active layer can be further reduced.
As an alternative to this embodiment, the conductive region 21 is formed by hydrogenation or deoxidation of the same oxide semiconductor material as the semiconductor region 22.
In this embodiment, a hydrogenated or deoxygenated conductive pattern is provided, and similar vias 23 may be provided using other conductive patterns as well. The via 23 is formed first and then the conductive layer is formed, so that diffusion of hydrogen atoms during the conductive layer can be avoided to a greater extent, and the via 23 may be formed with the active layer by a one-step mask.
In one embodiment, the thin film transistor is a top gate type. A gate insulating layer 4 is arranged above the oxide active layer 2, and a gate 5 is arranged above the gate insulating layer 4.
In one embodiment, the thin film transistor further includes a first insulating layer covering the second sidewall 214 and filling the via 23. The first insulating layer comprises a third side at the location of the via 23, which third side extends into the via 23. The first insulating layer may be an interlayer insulating layer 6 disposed above the gate electrode 5, so that the leakage current can be effectively reduced due to the fact that the first insulating layer is partially filled in the via hole 23.
In this embodiment, a top gate type thin film transistor is specifically described as an example, and other bottom gate type thin film transistors may also adopt similar schemes, which are not described herein.
In one embodiment, as shown in fig. 6, the conductive region 21 forms a side surface at the via 23, wherein the side surface away from the semiconductive region 21 is a first side surface; the source and drain electrodes 3 cover at least part of the first side. That is, in the scheme shown in fig. 6, the overlap contact area between the source and drain and the side surface of the via 23 of the conductive region 21 is increased, which is more beneficial to electron transfer.
In one embodiment, as shown in fig. 6, the gate 5 does not overlap the first conductive region 211. The gate 5 does not overlap the second conductive region 212. Since the gate 5 is disposed above the gate insulating layer 4 and the gate 5 is further provided with a first insulating layer, the first insulating layer is partially filled in the via hole 23, so that the gate 5 does not overlap with the first conductive region 211 and the second conductive region 212, thereby greatly reducing parasitic capacitance.
In one embodiment, as shown in fig. 6, the gate 5 and the via 23 do not overlap, and since the gate 5 is covered by the first insulating layer, the gate 5 and the via 23 do not overlap, thereby improving uniformity of channel fabrication.
Example 4:
the embodiment provides an array substrate, which comprises the thin film transistor.
Example 5:
the embodiment provides a display device, which comprises any one of the array substrates. The display device may be: any product or component with display function such as a liquid crystal display panel, electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (12)
1. The thin film transistor is characterized by comprising a substrate, an active layer, a source electrode, a drain electrode and a grid electrode, wherein the active layer is arranged above the substrate, the active layer comprises a conductive area and a semiconductor area which are connected, the conductive area comprises a first conductive area connected with the source electrode and the drain electrode and a second conductive area connected with the active layer, and a through hole is arranged between the first conductive area and the second conductive area;
the first conductive region forms a first side wall close to the source electrode and the drain electrode, and the second conductive region forms a second side wall far away from the semiconductor region; a first insulating layer is arranged on one side, away from the substrate, of the active layer, the first insulating layer covers the second side wall, and the second conductive region is not in direct contact with the source electrode and the drain electrode.
2. The thin film transistor of claim 1, wherein the width of the first conductive region is not equal to the width of the second conductive region.
3. The thin film transistor of claim 1, further comprising a first insulating layer covering the second sidewall and filling the via.
4. The thin film transistor of claim 3, wherein the first insulating layer includes a third side at the via hole, the third side extending into the via hole.
5. The thin film transistor of claim 1, wherein the gate electrode does not overlap the first conductive region.
6. The thin film transistor of claim 1, wherein the gate electrode does not overlap the second conductive region.
7. The thin film transistor of claim 1, wherein the gate electrode does not overlap the via.
8. The thin film transistor of claim 1, wherein the thin film transistor is top gate.
9. The thin film transistor according to claim 1, wherein the active layer material is an oxide semiconductor material.
10. An array substrate comprising the thin film transistor of any one of claims 1-9.
11. A display device comprising the array substrate of claim 10.
12. A display device according to claim 11, wherein the display device is an OLED panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111069469.7A CN113782616B (en) | 2019-01-10 | 2019-01-10 | Thin film transistor, preparation method thereof, array substrate and display device |
Applications Claiming Priority (2)
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| CN105428243A (en) * | 2016-01-11 | 2016-03-23 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof, array substrate and display apparatus |
| CN107946315A (en) * | 2017-11-15 | 2018-04-20 | 上海天马微电子有限公司 | A kind of array base palte, display panel and electronic equipment |
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| CN108231595A (en) * | 2018-01-02 | 2018-06-29 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array substrate, display device |
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| CN104022076B (en) * | 2014-05-27 | 2017-01-25 | 京东方科技集团股份有限公司 | Array substrate, preparing method thereof and display device |
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| CN107946315A (en) * | 2017-11-15 | 2018-04-20 | 上海天马微电子有限公司 | A kind of array base palte, display panel and electronic equipment |
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| CN108598089A (en) * | 2018-04-27 | 2018-09-28 | 武汉华星光电技术有限公司 | The production method and TFT substrate of TFT substrate |
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| CN113782616A (en) | 2021-12-10 |
| CN109742031A (en) | 2019-05-10 |
| CN115663032A (en) | 2023-01-31 |
| CN109742031B (en) | 2022-07-05 |
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