CN210723028U - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN210723028U CN210723028U CN201922107852.1U CN201922107852U CN210723028U CN 210723028 U CN210723028 U CN 210723028U CN 201922107852 U CN201922107852 U CN 201922107852U CN 210723028 U CN210723028 U CN 210723028U
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Abstract
The application discloses display panel, display device, including the substrate base plate to and the light shield layer and the thin film transistor that a plurality of arrays were arranged on the substrate base plate. The shading layer is composed of a plurality of shading units, each shading unit corresponds to the thin film transistor one by one and is positioned on one side of the thin film transistor in the direction close to the substrate; the shading unit comprises a first shading area and a second shading area, and the second shading area surrounds the first shading area; according to the technical scheme provided by the application, due to the existence of the first shading area of the shading unit, on one hand, the shading function of the shading layer can not be influenced, and the active layer can be protected; meanwhile, even if the interlayer insulating layer through hole extends to the shading layer due to process problems, a short circuit caused by a conductive path between the source electrode and the drain electrode and the first electrode cannot be formed, so that a bright spot is not caused when voltage is applied to the drain electrode, and the display effect and the product quality can be effectively improved.
Description
Technical Field
The utility model relates to a show technical field, especially relate to display panel, display device.
Background
A Thin Film Transistor (TFT) is a field effect Transistor having a multi-functional Thin Film layer made of transparent glass as a substrate, and has an important role in the operation performance of a display device. The TFT type display screen is a kind of active matrix liquid crystal display device, each liquid crystal pixel of which is driven by a thin film transistor array integrated behind the pixel, and the thin film transistor array technology is often used in the art to improve the picture quality, so the TFT type display screen is widely used in electronic display devices such as mobile phones, flat panels, computer monitors, televisions, and the like.
The top gate type TFT is one of TFT types, and has a short channel characteristic so that an on-state current can be effectively increased when it operates. In addition, the overlapping area of the grid electrode and the source electrode and the drain electrode of the top grid type TFT is small, so that the generated parasitic capacitance is small, the display effect can be obviously improved, and the power consumption can be effectively reduced. The top gate type TFT has been receiving more and more attention because of its remarkable advantages as described above. Currently, most of top gate TFTs adopt IGZO (indium gallium zinc oxide) semiconductors with high carrier mobility as active layers.
SUMMERY OF THE UTILITY MODEL
The utility model provides a display panel and display panel preparation method, display device.
The adopted technical scheme is a display panel, comprising:
base substrate, and
the light shielding layer and the plurality of thin film transistors are arranged in an array mode;
the light shielding layer is composed of a plurality of light shielding units, each light shielding unit corresponds to the thin film transistor one by one and is positioned on one side of the thin film transistor in the direction close to the substrate;
a buffer layer is arranged on the substrate in the direction away from the light shielding layer;
the thin film transistor comprises an active layer, a grid electrode insulating layer, a grid electrode, an interlayer insulating layer and a source drain electrode layer which are sequentially arranged in the direction far away from the buffer layer;
the active layer comprises a conductor region in which the projections of the active layer and the gate insulating layer on the substrate do not overlap, and a channel region in which the projections of the active layer and the gate insulating layer on the substrate overlap;
the source drain layer comprises a first electrode and a second electrode;
the shading unit comprises a first shading area and a second shading area, and the second shading area surrounds the first shading area;
the projection of the channel region on the substrate base plate is positioned in the projection of the second shading region on the substrate base plate;
the thin film transistor is provided with a passivation layer and an anode in sequence towards the direction far away from the substrate base plate.
Optionally, the interlayer insulating layer includes a first via hole and a second via hole;
at least part of the projection areas of the first shading area and the first via hole on the shading layer has an overlapping area;
at least part of the projection areas of the second shading area and the second through hole on the shading layer has an overlapping area.
Optionally, wherein at least a portion of the first electrode is located within the first via; the first shading area is completely overlapped with the projection area of the first through hole on the shading layer, and the first through hole is in contact with the first electrode.
Optionally, wherein at least a portion of the second electrode is located within the second via; the second shading area is located outside a projection area of the first via hole on the shading layer and is in contact with the second electrode through the second via hole.
Optionally, in the light shielding unit, the first light shielding region and the second light shielding region are isolated from each other by a gap and are not connected to each other.
Optionally, a projection of the gap on the substrate base plate completely falls outside a projection area of the channel region on the substrate base plate.
Optionally, the first light-shielding region and the second light-shielding region comprise metal conductive materials such as aluminum, molybdenum or aluminum-molybdenum-niobium alloy, and the thickness of the metal conductive materials is 0.20-0.25 um.
Optionally, the first light-shielding region and the second light-shielding region may also be integrally connected in a seamless manner.
Optionally, the first light-shielding region is made of an insulating material, and the second light-shielding region is configured as a conductive material.
Optionally, the insulating material in the first shading area is a metal oxide or a metal nitride, the conductive material in the second shading area is a metal material such as aluminum, molybdenum or an aluminum-molybdenum-niobium alloy, and the thickness of the conductive material is 0.20-0.25 um.
The utility model provides a display device, a serial communication port, including an arbitrary technical characteristic of above-mentioned display panel.
The utility model provides a display panel preparation method, include:
providing a base substrate, and
patterning and depositing to form a plurality of shading units in a shading layer, and forming a first shading area and a second shading area on the shading units, wherein the second shading area is configured to surround the first shading area;
depositing a buffer layer, patterning and depositing to form an active layer, depositing a gate insulating layer, patterning and depositing to form a gate, depositing an interlayer insulating layer, patterning and depositing to form a source drain;
preferably, when a plurality of the light shielding units are formed, a gap is prepared through processes of coating photoresist, exposing, developing and dry etching, so that the first light shielding region is surrounded by the second light shielding region and is isolated from the second light shielding region through the gap;
the first light-shielding region and the second light-shielding region are both configured to be metal conductive materials.
Preferably, a buffer layer is deposited on the light shielding unit, an active layer pattern is formed on the buffer layer by patterning using photoresist, a gate insulating layer pattern is formed on the active layer by patterning, and a metal gate is formed on the gate insulating layer by patterning;
the photoresist used in the process of composition above the grid electrode is not stripped, the self-alignment process is adopted to etch the grid electrode insulating layer, the edge of the exposed active layer is subjected to a conductor process;
depositing an interlayer insulating layer, forming a pattern to be etched, and forming a first through hole and a second through hole by plasma dry etching;
preferably, when a plurality of the light shielding units are formed, the light shielding unit includes:
carrying out exposure and development process by adopting a half-tone mask, completely reserving the photoresist of the opaque region corresponding to the second shading region, partially reserving the photoresist of the semi-transparent region corresponding to the first shading region, developing and removing the photoresist of the completely transparent region, and carrying out etching process to form a first shading layer pattern;
ashing the residual photoresist on the light shielding layer pattern to remove the photoresist in the semi-light-transmitting area by ashing;
oxidizing or nitriding the exposed part of the first shading area corresponding to the semi-light-transmitting area to form an insulator;
stripping all the photoresist to form the light shielding layer
Wherein the light shielding unit is configured as an integral structure, wherein the first light shielding region and the second light shielding region are configured as seamless connection;
the first light-shielding region is configured to be a metal oxide or metal nitride material, and the second light-shielding region is configured to be a metal material;
depositing an interlayer insulating layer, forming a pattern to be etched, and forming a first through hole and a second through hole by plasma dry etching;
the utility model discloses a display panel and display device, including the substrate base plate to and the thin film transistor that light shield layer and a plurality of array on the substrate base plate were arranged. The shading layer is composed of a plurality of shading units, each shading unit corresponds to the thin film transistor one by one and is positioned on one side of the thin film transistor in the direction close to the substrate; the shading unit comprises a first shading area and a second shading area, and the second shading area surrounds the first shading area. According to the technical scheme provided by the application, due to the existence of the first shading area of the shading unit, on one hand, the shading function of the shading layer can not be influenced, and the active layer can be protected; meanwhile, even if the interlayer insulating layer through hole extends to the shading layer due to process problems, a short circuit caused by a conductive path between the source electrode and the drain electrode and the first electrode cannot be formed, so that a bright spot is not caused when voltage is applied to the drain electrode, and the display effect and the product quality can be effectively improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic cross-sectional view of a display panel with a thin film transistor;
FIG. 2 is a schematic diagram of a sub-pixel circuit according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a display panel;
FIG. 4 is a schematic view of a light shielding unit;
FIG. 5 is a schematic cross-sectional view of another display panel;
FIG. 6 is a schematic view of another light shielding unit structure;
FIG. 7 is a schematic view of a process for manufacturing a display panel;
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are illustrated in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
FIG. 1 is a schematic cross-sectional view of a display panel with a thin film transistor;
as shown in the drawings, a display panel is provided, which includes a substrate 10, and a plurality of thin film transistors fabricated thereon, including an active layer 40, a gate electrode 60, and a source drain layer 80; the projection area of the active layer 40 on the substrate is overlapped and non-overlapped with the projection area of the gate electrode on the substrate. The active layer can be made of semiconductor materials such as amorphous silicon, polycrystalline silicon, metal oxide and the like.
Optionally, the material selected in this embodiment is IGZO (indium gallium zinc oxide); the non-overlapping portion may be formed by doping metal ions into a conductor region 401 for electrical connection; and the overlapping portion constitutes an active region, i.e., a channel region 402, in the thin film transistor.
A metal shading layer 20 deposited on the substrate base plate 10 is also arranged between the substrate base plate 10 and the thin film transistor; the light shielding unit 20 is a light shielding metal layer, and is composed of a plurality of light shielding units corresponding to a plurality of thin film transistors one to one, and a projection of each light shielding unit on the substrate is at least overlapped with a projection of each thin film transistor on the substrate, so as to protect an active layer structure in the thin film transistor thereon from being directly irradiated by light, and avoid the function failure or weakening of the transistor.
The display panel further comprises a plurality of functional layers, wherein: a buffer layer 30 disposed between the light-shielding layer 20 and the active layer 40 for relieving an influence of an external stress on the inside of the display panel; a gate insulating layer 50 disposed between the active layer 40 and the gate electrode 60 for preventing electrical connection between the active layer and the gate electrode; an interlayer insulating layer 70 disposed inside the thin film transistor for preventing the source and drain electrodes from being electrically connected to other connection lines in the display panel, and a passivation layer 90 disposed in a direction away from the substrate to cover the thin film transistor; wherein, the source and drain electrodes in the thin film transistor on the display panel are connected with the conductive region 401 of the active layer 40 through the first via hole 701 arranged in the interlayer insulating layer 70; the source and drain levels in the thin film transistor on the display panel are connected with the light shielding layer 40 through second via holes 702 which are arranged in the interlayer insulating layer 70 and the buffer layer 30 in a penetrating manner; the source/drain electrodes of the thin film transistors on the display panel are electrically connected to the anode layer 100 through the passivation layer, and the anode layer is made of a transparent electrode ITO.
In the circuit design of the AMOLED product, fig. 2 is adopted as one of the embodiments of the present invention, the sub-pixel circuit connection diagram: the basic structure of the sub-pixel circuit is illustrated with an N-type transistor as an example, and specifically, the sub-pixel circuit includes a driving transistor T3, a first switching transistor T1, a second switching transistor T2, and a light emitting element.
A first electrode of the first switching transistor T1 is connected to a DATA line DATA, a second electrode of the first switching transistor T2 is connected to the gate of the driving transistor T3, and a gate of the first switching transistor T1 is connected to a first scan line G1. A first electrode of the driving transistor T3 is connected to a first power source terminal VDD, a second electrode of the driving transistor T3 is connected to an anode of a light emitting element, a cathode of the light emitting element is connected to a second power source terminal VSS, a first electrode of the second switching transistor T2 is connected to a second electrode of the driving transistor T3, a second electrode of the second switching transistor T2 is connected to a sensing line Sense, and a gate of the second switching transistor T2 is connected to a second scan line G2.
In this embodiment, an IGZO semiconductor is used as an active layer. The process flow comprises the following steps: the method comprises the steps of forming a light shielding layer on a substrate by adopting a chemical vapor deposition process (hereinafter referred to as deposition), using an optical mask through the processes of coating (photoresist PR), exposing, developing and the like (hereinafter referred to as composition), further depositing a buffer layer, further patterning and depositing to form an active layer, further depositing a grid insulating layer, further patterning and depositing to form a grid, further not stripping PR (photoresist) above a pattern, further carrying out a high-energy gas dry etching process on the lower grid insulating layer by adopting a self-alignment process, further carrying out a conductor process of the active layer, further depositing an interlayer insulating layer, patterning and continuing dry etching to form a first via hole and a second via hole, further patterning and depositing to form a source/drain electrode, and finally depositing a passivation layer and an anode. A first power supply terminal VDD signal passes through a signal line connected to the source 801; the drain electrode 802 and the anode 100 are lapped together; the drain electrode 802 is electrically connected with the shielding layer 20 through the second via hole 702, and the access of an electric signal is realized through the source and drain electrode layer;
optionally, the conductor region 401 of the non-channel portion in the active layer 20 and the shielding unit together form a storage capacitor. The storage capacitor, which is formed by using the light shielding layer 20 and the conductor region 401 in the active layer 40 as the bipolar plates, is separated from the buffer layer 30 only and is close to the buffer layer, so that a larger amount of electric charge can be stored, and the working performance is excellent.
In the actual process of manufacturing the thin film transistor, due to the non-uniformity of large-area dry etching, the gate insulating layer in the pixel region is etched unevenly, and the lower buffer layer is etched at some positions, so that the light emitting efficiency of the display device is uneven; secondly, the buffer layers at different positions are etched to different degrees, so that the process is not easy to control when the interlayer insulating layer is etched subsequently, and the lower grating shielding layer pattern layer is easy to be etched and damaged; in addition, the etching amount is not easy to control when the via hole is prepared, and the short circuit condition is often caused by over etching, so that certain pixel points of the display equipment cannot be normally lightened, and the dead pixel is caused. Based on the defects and shortcomings of the prior art, a brand new display panel structure design and a display panel preparation method need to be provided during actual process operation, so that the display quality of a product is improved.
In the actual process, the dry etching strength in the process is not easy to control when the first via hole is formed, so that the situation of large over-etching amount is easy to occur; in addition, the active layer is generally formed to be thin in an actual process, so that some parts are easy to be lost or are etched away, the first via hole is always hit on the shading unit of the lower shading layer, the subsequent drain electrode is short-circuited with the shading unit in the shading layer, and a path of the source electrode → the shading unit → the drain electrode → the anode ITO is formed, so that a bright spot is caused to be bad when voltage is applied to the drain electrode.
The following examples illustrate a plurality of embodiments, which can effectively solve the problem of poor high luminance caused by short circuit between the drain and the light shielding unit, thereby significantly improving the display quality of the product.
Example 1:
FIG. 3 is a schematic cross-sectional view of a display panel;
the display panel comprises a substrate base plate 10, a plurality of thin film transistors prepared on the substrate base plate, an active layer 40, a grid 60 and a source drain electrode layer 80; the projection area of the active layer 40 on the substrate is overlapped and non-overlapped with the projection area of the gate electrode on the substrate. Generally, the material of the active layer is selected from amorphous silicon, polysilicon, metal oxide and other semiconductor materials. Optionally, the material selected in this embodiment is IGZO (indium gallium zinc oxide); the non-overlapping portion may be formed by doping metal ions into a conductor region 401 for electrical connection; and the overlapping portion constitutes an active region 402 in the thin film transistor.
A metal shading layer 20 deposited on the substrate base plate 10 is also arranged between the substrate base plate 10 and the thin film transistor; the light shielding unit 20 is a light shielding metal layer, and is composed of a plurality of light shielding units corresponding to a plurality of thin film transistors one to one, and a projection of each light shielding unit on the substrate is at least overlapped with a projection of each thin film transistor on the substrate, so as to protect an active layer structure in the thin film transistor thereon from direct irradiation of light and avoid functional failure or weakening of the transistor.
The display panel further comprises a plurality of functional layers, wherein: a buffer layer 30 disposed between the light-shielding layer 20 and the active layer 40 for relieving an influence of an external stress on the inside of the display panel; a gate insulating layer 50 disposed between the active layer 40 and the gate electrode 60 for preventing electrical connection between the active layer and the gate electrode; an interlayer insulating layer 70 disposed inside the thin film transistor for preventing the source-drain electrodes from being electrically connected to other connection lines in the display panel, and a passivation layer 90 disposed in a direction away from the substrate to cover the thin film transistor; wherein, the source/drain in the thin film transistor on the display panel is connected with the conductive region 401 which is made conductive in the active layer 40 through the first via hole 701 provided in the interlayer insulating layer 70; a source/drain electrode of the thin film transistor on the display panel is connected to the light shielding layer 40 through a second via hole 702 penetratingly formed in the interlayer insulating layer 70 and the buffer layer 30; and source and drain electrodes in the thin film transistor on the display panel penetrate through the passivation layer to be electrically connected with the anode layer 100, and the anode layer is made of a transparent electrode ITO.
In the display panel, the light shielding unit corresponding to the thin film transistor includes a first light shielding region 201 and a second light shielding region 202, the second light shielding region is arranged to surround the first light shielding region, and the light shielding layer 20 is designed to be a partially hollow structure;
the first light shielding region is positioned in a projection region of the first via hole on the light shielding region and is in contact with a source electrode or a drain electrode in the first via hole;
the second shading area is positioned outside the projection area of the first via hole on the shading layer and is contacted with the drain electrode or the source electrode in the second via hole;
FIG. 4 is a schematic view of a light shielding unit;
in the shading unit, the first shading area is surrounded by the second shading area, wherein in the shading unit, the first shading area and the second shading area are isolated from each other through a gap and are not connected with each other; the projection of the gap on the substrate base plate completely falls outside the projection area of the active layer channel area on the substrate base plate. Therefore, the two areas are disconnected due to the slit and are not overlapped with the channel area of the active layer, and the phenomenon that the service life of a device is influenced because the ambient light irradiates the active area in the thin film transistor through the slit is avoided.
The first light-shielding region and the second light-shielding region are made of conductive materials, and generally, metal materials such as iron, aluminum, silver and the like or nano materials with higher conductivity coefficients can be selected. Therefore, on the one hand, the shading function of the shading layer is not influenced, and meanwhile, even if the first via hole is contacted with the shading unit due to process problems, the first shading area becomes an island structure due to the existence of the isolation gap, a path between the drain electrode and the anode ITO can not be formed, and therefore the defect of bright spots caused when the voltage is applied to the drain electrode is avoided.
The embodiment of the utility model provides an in display panel preparation method, including the step: providing a substrate, and sequentially patterning and depositing a shading layer, a buffer layer, an active layer, a gate insulating layer, a gate, an interlayer insulating layer, a source and a drain;
a plurality of light shielding units are arranged on the light shielding layer; and forming a first light-shielding area and a second light-shielding area on the light-shielding unit, wherein the second light-shielding area surrounds the first light-shielding area.
Preferably, the display panel manufacturing method further includes: when a plurality of shading units are formed, preparing gaps through processes of coating photoresist, masking, exposing, developing and dry etching, enabling the first shading area to be surrounded by the second shading area, and enabling the first shading area and the second shading area to be isolated from each other through the gaps; the first light-shielding area and the second light-shielding area are both made of metal conductive materials;
optionally, the material is a metal conductive material such as aluminum, molybdenum or aluminum-molybdenum-niobium alloy, and the thickness is 0.20-0.25 um.
Preferably, the method for manufacturing a display panel further includes: depositing a buffer layer on the light shielding unit, forming an active layer pattern on the buffer layer by using photoresist in a patterning way, forming a gate insulating layer pattern on the active layer in a patterning way, and forming a metal gate on the gate insulating layer in a patterning way;
the photoresist used in the process of composition above the grid electrode is not stripped, the self-alignment process is adopted to etch the grid electrode insulating layer, the edge of the exposed active layer is subjected to a conductor process;
depositing an interlayer insulating layer, forming a pattern to be etched, and forming a first through hole and a second through hole by plasma dry etching;
at least part of a projection area of the first shading area on the shading layer and a projection area of the first via hole on the shading layer are overlapped;
at least part of the projection area of the second shading area on the shading layer and the projection area of the second through hole on the shading layer have an overlapping area.
Therefore, on one hand, the shading function of the shading unit is not influenced, and on the other hand, even if the etching amount of the via hole of the interlayer insulating layer is excessively etched on the shading layer due to process problems, a path of the source electrode → the shading unit → the drain electrode → the anode ITO is not formed, so that the defect of a bright spot is not caused when the voltage is applied to the drain electrode. By adopting the scheme of the embodiment, the incidence rate of the bright spot failure can be obviously reduced, so that the display quality of the product is obviously improved.
Example 2:
FIG. 5 is a schematic cross-sectional view of another display panel;
the present example provides a display panel including a substrate base plate 10, and a plurality of thin film transistors prepared thereon, including an active layer 40, a gate electrode 60, and source/drain electrode layers 80; the projection area of the active layer 40 on the substrate is overlapped and non-overlapped with the projection area of the gate electrode on the substrate. Generally, the material of the active layer is selected from amorphous silicon, polysilicon, metal oxide and other semiconductor materials. Optionally, the material selected in this embodiment is IGZO (indium gallium zinc oxide); the non-overlapping portion may be formed by doping metal ions into a conductor region 401 for electrical connection; and the overlapping portion constitutes an active region, i.e., a channel region 402, in the thin film transistor.
A metal shading layer 20 deposited on the substrate base plate 10 is also arranged between the substrate base plate 10 and the thin film transistor; the light shielding unit 20 is a light shielding metal layer, and is composed of a plurality of light shielding units corresponding to a plurality of thin film transistors one to one, and a projection of each light shielding unit on the substrate is at least overlapped with a projection of each thin film transistor on the substrate, so as to protect an active layer structure in the thin film transistor thereon from being directly irradiated by light, and avoid the function failure or weakening of the transistor.
The display panel further comprises a plurality of functional layers, wherein: a buffer layer 30 disposed between the light-shielding layer 20 and the active layer 40 for relieving an influence of an external stress on the inside of the display panel; a gate insulating layer 50 disposed between the active layer 40 and the gate electrode 60 for preventing electrical connection between the active layer and the gate electrode; an interlayer insulating layer 70 disposed inside the thin film transistor for preventing the source-drain electrodes from being electrically connected to other connection lines in the display panel, and a passivation layer 90 disposed in a direction away from the substrate to cover the thin film transistor; wherein, the source and drain electrodes in the thin film transistor on the display panel are connected with the conductive region 401 of the active layer 40 through the first via hole 701 arranged in the interlayer insulating layer 70; the source and drain levels in the thin film transistor on the display panel are connected with the light shielding layer 40 through second via holes 702 which are arranged in the interlayer insulating layer 70 and the buffer layer 30 in a penetrating manner; and source and drain electrodes in the thin film transistor on the display panel penetrate through the passivation layer to be electrically connected with the anode layer 100, and the anode layer is made of a transparent electrode ITO.
In the display panel, the light shielding unit corresponding to the thin film transistor includes a first light shielding region 201 and a second light shielding region 202, and the second light shielding region is disposed to surround the first light shielding region; preferably, the shading unit is designed as a partially insulated structure;
the first light shielding region is positioned in a projection region of the first via hole on the light shielding region and is in contact with a source electrode or a drain electrode in the first via hole;
the second shading area is positioned outside the projection area of the first via hole on the shading layer and is contacted with the drain electrode or the source electrode in the second via hole;
FIG. 6 is a schematic view of another light shielding unit structure;
within the light shielding unit, the first light shielding region is surrounded by the second light shielding region; the shading units are of an integrated structure, wherein the first shading unit and the second shading unit are connected with each other;
the first light shielding unit is configured to be an insulating material, and the second light shielding unit is configured to be a conductive material; the insulating material may be a metal oxide or a metal nitride; the conductive material can be selected from metal conductive materials such as iron, aluminum, silver, molybdenum or aluminum-molybdenum-niobium alloy, or nano materials with higher conductivity coefficient. Therefore, on the one hand, the shading function of the shading layer is not influenced, and meanwhile, even if the first via hole is contacted with the shading unit due to process problems, due to the existence of the first shading area, the over-etching part is located in the area corresponding to the shading layer and is an insulating area, a passage between the drain electrode and the anode ITO cannot be formed, and therefore the defect of bright spots caused when voltage is applied to the drain electrode is avoided.
FIG. 7 is a schematic view of a process for manufacturing a display panel;
the preparation method of the display panel comprises the following steps: providing a substrate, and sequentially patterning and depositing a shading layer, a buffer layer, an active layer, a gate insulating layer, a gate, an interlayer insulating layer, a source and a drain;
a plurality of light shielding units are arranged on the light shielding layer; forming a first light-shielding area and a second light-shielding area on the light-shielding unit, wherein the first light-shielding area and the second light-shielding area are arranged in a staggered manner;
correspondingly forming a plurality of thin film transistors on the plurality of light shielding units;
preferably, the forming of a plurality of the light shielding units includes: carrying out exposure and development process by adopting a half-tone mask, completely reserving the photoresist of the opaque region corresponding to the second shading region, partially reserving the photoresist of the semi-transparent region corresponding to the first shading region, developing and removing the photoresist of the completely transparent region, and carrying out etching process to form a first shading layer pattern;
ashing the residual photoresist on the light shielding layer pattern to remove the photoresist in the semi-light-transmitting area by ashing;
oxidizing or nitriding the exposed part of the first shading area corresponding to the semi-light-transmitting area to form an insulator;
stripping all the photoresist to form the light shielding layer
Wherein the light shielding units are configured as an integral structure, wherein the first light shielding region and the second light shielding region are configured to be directly connected to each other;
the first light-shielding region is configured to be a metal oxide or metal nitride material, and the second light-shielding region is configured to be a metal material;
depositing an interlayer insulating layer, forming a pattern to be etched, and forming a first through hole and a second through hole by plasma dry etching;
at least part of a projection area of the first shading area on the shading layer and a projection area of the first via hole on the shading layer are overlapped;
at least part of the projection area of the second shading area on the shading layer and the projection area of the second through hole on the shading layer have an overlapping area.
Therefore, on one hand, the shading function of the shading unit is not influenced, and on the other hand, even if the interlayer insulating layer is perforated on the shading layer due to process problems, the path of the source electrode → the shading unit → the drain electrode → the anode ITO is not formed, so that the defect of bright spots is not caused when the voltage is applied to the drain electrode.
By adopting the technical scheme, the problem of poor high-luminance caused by short circuit of the source/drain electrode and the shading layer can be effectively solved, so that the display quality of a product is remarkably improved, and the technical proposal does not increase any exposure process.
Example 3:
the present embodiment provides a display device including the display panel described in embodiment 1 or embodiment 2. The display device may be: the display device comprises any product or component with a display function, such as an OLED panel, a mobile phone, a tablet personal computer, a digital photo frame, a notebook computer, a display, a television, a navigator, a vehicle-mounted multifunctional rearview mirror device and the like.
The display device of the embodiment has the display panel in the embodiment 1 or 2, so the preparation process is simple, the process reliability is high, the problem of poor performance caused by local short circuit is solved, and the display effect and the product quality can be effectively improved.
Of course, the display device of the present embodiment may further include other conventional structures, such as a power supply unit, a display driving unit, a light emitting unit, a packaging unit, a frame structure, and the like.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral connections; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
It is to be understood that the above description is only exemplary of the present application and is intended to provide an illustration of the principles of the technology, structure, and process steps employed. It will be understood by those skilled in the art that the scope of the present invention is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is possible without departing from the spirit of the present invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (11)
1. A display panel, comprising:
base substrate, and
the light shielding layer and the plurality of thin film transistors are arranged in an array mode;
the light shielding layer is composed of a plurality of light shielding units, each light shielding unit corresponds to the thin film transistor one by one and is positioned on one side of the thin film transistor in the direction close to the substrate;
a buffer layer is arranged on the substrate in the direction away from the light shielding layer;
the thin film transistor comprises an active layer, a grid electrode insulating layer, a grid electrode, an interlayer insulating layer and a source drain electrode layer which are sequentially arranged in the direction far away from the buffer layer;
the active layer comprises a conductor region in which the projections of the active layer and the gate insulating layer on the substrate do not overlap, and a channel region in which the projections of the active layer and the gate insulating layer on the substrate overlap;
the source drain layer comprises a first electrode and a second electrode;
the shading unit comprises a first shading area and a second shading area, and the second shading area surrounds the first shading area;
the projection of the channel region on the substrate base plate is positioned in the projection of the second shading region on the substrate base plate;
the thin film transistor is provided with a passivation layer and an anode in sequence towards the direction far away from the substrate base plate.
2. The display panel according to claim 1,
the interlayer insulating layer comprises a first via hole and a second via hole;
at least part of the projection areas of the first shading area and the first via hole on the shading layer has an overlapping area;
at least part of the projection areas of the second shading area and the second through hole on the shading layer has an overlapping area.
3. The display panel according to claim 2,
at least a portion of the first electrode is positioned within the first via; the first shading area is completely overlapped with the projection area of the first through hole on the shading layer, and the first through hole is in contact with the first electrode.
4. The display panel according to claim 2,
at least a portion of the second electrode is positioned within the second via; the second shading area is located outside a projection area of the first via hole on the shading layer and is in contact with the second electrode through the second via hole.
5. The display panel according to claim 1 or 2, wherein the first light-shielding region and the second light-shielding region are isolated from each other by a gap and are not connected to each other in the light-shielding unit.
6. The display panel according to claim 5, wherein a projection of the slit on the substrate base plate completely falls outside a projection area of the channel region on the substrate base plate.
7. The display panel of claim 5, wherein the first and second light-shielding regions are made of a conductive material such as aluminum, molybdenum or aluminum-molybdenum-niobium alloy with a thickness of 0.20-0.25 um.
8. The display panel according to claim 1 or 2, wherein the first light-shielding region and the second light-shielding region are integrally connected seamlessly.
9. The display panel according to claim 7, wherein the first light-shielding region is an insulating material, and the second light-shielding region is configured as a conductive material.
10. The display panel according to claim 9, wherein the insulating material of the first light-shielding region is a metal oxide or a metal nitride, and the conductive material of the second light-shielding region is a metal material such as aluminum, molybdenum, or an aluminum-molybdenum-niobium alloy.
11. A display device characterized by comprising the display panel of any one of claims 1 to 10.
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| CN201922107852.1U CN210723028U (en) | 2019-11-29 | 2019-11-29 | Display panel and display device |
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| CN201922107852.1U CN210723028U (en) | 2019-11-29 | 2019-11-29 | Display panel and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729313A (en) * | 2019-11-29 | 2020-01-24 | 京东方科技集团股份有限公司 | Display panel, display panel preparation method and display device |
| CN111739910A (en) * | 2020-06-16 | 2020-10-02 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display device |
| CN113192934A (en) * | 2021-03-29 | 2021-07-30 | 合肥维信诺科技有限公司 | Array substrate and display panel |
-
2019
- 2019-11-29 CN CN201922107852.1U patent/CN210723028U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729313A (en) * | 2019-11-29 | 2020-01-24 | 京东方科技集团股份有限公司 | Display panel, display panel preparation method and display device |
| CN111739910A (en) * | 2020-06-16 | 2020-10-02 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display device |
| CN111739910B (en) * | 2020-06-16 | 2023-05-09 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display device |
| CN113192934A (en) * | 2021-03-29 | 2021-07-30 | 合肥维信诺科技有限公司 | Array substrate and display panel |
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