CN111739910B - Array substrate, preparation method thereof and display device - Google Patents

Array substrate, preparation method thereof and display device Download PDF

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Publication number
CN111739910B
CN111739910B CN202010550081.8A CN202010550081A CN111739910B CN 111739910 B CN111739910 B CN 111739910B CN 202010550081 A CN202010550081 A CN 202010550081A CN 111739910 B CN111739910 B CN 111739910B
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layer
thin film
film transistor
hole
substrate
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CN111739910A (en
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林高波
张晓星
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses an array substrate, a preparation method thereof and a display device, wherein the array substrate comprises a substrate; the thin film transistor structure layer is arranged on one side surface of the substrate and comprises more than two thin film transistor devices; the flat layer is arranged on the surface of one side of the thin film transistor structure layer, which is far away from the substrate; the first through holes penetrate through the flat layer and are arranged on two sides of each thin film transistor device; the conductive layer is arranged on one side surface of the thin film transistor structure layer, which is far away from the substrate; the middle part of the conductive layer is opposite to the thin film transistor device, and two ends of the conductive layer extend to the first through holes respectively and are attached to the thin film transistor structure layer at the bottom of the first through holes. The invention has the beneficial effects that: according to the array substrate, the preparation method thereof and the display device, through holes are etched in the flat layer, and the shielding is formed on the side face through the conducting layer, so that light rays on the side face and the front face of the conducting layer enter the thin film transistor structural layer, and the service life of the array substrate is prolonged.

Description

Array substrate, preparation method thereof and display device
Technical Field
The application relates to the field of display panels, in particular to an array substrate, a preparation method thereof and a display device.
Background
Due to the light-sensitive characteristics of the Active region semiconductor material, the characteristics of a field effect transistor (Field Effect Transistor abbreviation (FET)) may be affected by external ambient light, self-luminescence of an AMOLED (Active-matrix organic light-emitting diode, in english), or the like, resulting in a decrease in display performance. The anode of the top-emitting back plate structure has a reflective top-emitting light, but light in a blank region between the pixel electrodes is irradiated to the FET through the PLN layer, thereby affecting the stability of the FET.
Disclosure of Invention
The embodiment of the application provides an array substrate, a preparation method thereof and a display device, which are used for solving the technical problem that the performance of a thin film transistor structure layer is reduced because external light irradiates the thin film transistor structure layer in the prior art.
The technical scheme for solving the technical problems is as follows: the invention provides an array substrate, which comprises a substrate; the thin film transistor structure layer is arranged on one side surface of the substrate and comprises more than two thin film transistor devices; the flat layer is arranged on one side surface of the thin film transistor structure layer, which is far away from the substrate; the first through holes penetrate through the flat layer and are arranged on two sides of each thin film transistor device; the conductive layer is arranged on one side surface of the thin film transistor structure layer, which is far away from the substrate; the middle part of a conductive layer is opposite to a thin film transistor device, and two ends of the conductive layer extend to a first through hole respectively and are attached to a thin film transistor structure layer at the bottom of the first through hole.
Further, the thin film transistor structure layer further comprises a shading layer, and the shading layer is arranged on one side surface of the substrate; the buffer layer is arranged on the surface of the substrate and covers the shading layer; an active layer arranged on one side surface of the buffer layer away from the substrate; the grid insulation layer is arranged on the surface of one side of the active layer, which is far away from the buffer layer; the grid electrode layer is arranged on one side surface of the grid electrode insulating layer, which is far away from the active layer; the dielectric layer is arranged on the surface of one side, far away from the substrate, of the buffer layer, and covers the active layer, the gate insulating layer and the gate layer; the source-drain electrode layer is arranged on one side surface of the dielectric layer, which is far away from the buffer layer, wherein the source-drain electrode layer partially penetrates through the dielectric layer and the buffer layer and is connected to the shading layer; the passivation layer is arranged on one side surface of the dielectric layer, which is far away from the buffer layer, and the passivation layer covers the source drain electrode layer; the thin film transistor device comprises the shading layer, the active layer, the gate insulating layer, the gate layer and the source drain electrode layer.
Further, a second through hole is formed in the flat layer corresponding to the source drain electrode layer, and the conducting layer fills the second through hole and is connected to the source drain electrode layer.
Further, the conductive layer is made of a metal material.
Further, the display panel further comprises a retaining wall, wherein the retaining wall is arranged on one side surface of the flat layer, which is far away from the thin film transistor structure layer, and a third through hole is formed in the position, corresponding to the conducting layer, of the retaining wall; a light emitting layer disposed in the third via hole and connected to the conductive layer; and the cathode is arranged on one side surface of the retaining wall, which is far away from the flat layer, and the cathode covers the light-emitting layer.
The invention also provides a preparation method of the array substrate, which comprises the following steps: providing a substrate; preparing a thin film transistor structure layer on the substrate, wherein the thin film transistor structure layer comprises more than two thin film transistor devices; preparing a flat layer on the thin film transistor structure layer; etching a first through hole and a first through hole on the flat layer, wherein the second through hole is formed in each thin film transistor device; and preparing a layer of metal material on the flat layer, wherein the metal material extends to the inner wall of the first through hole and is attached to the thin film transistor structure layer at the bottom of the first through hole.
Further, the specific preparation steps of the thin film transistor structure layer are as follows: depositing a light shielding layer on the substrate; depositing a buffer layer on the substrate, wherein the material of the buffer layer comprises at least one of silicon nitride or silicon oxide; depositing a layer of semiconductor material on the buffer layer, and forming an active layer after carrying out local conductor formation on the semiconductor material; preparing a gate insulating layer on the active layer; preparing a gate electrode layer on the gate insulating layer; depositing a dielectric layer on the gate layer, gate insulating layer, active layer and buffer; etching a through hole on the dielectric layer, wherein the through hole penetrates through the dielectric layer and the buffer layer; preparing a source-drain electrode layer on the dielectric layer, wherein the source-drain electrode layer penetrates through the through hole to be connected to the shading layer; and depositing a passivation layer on the dielectric layer and the source drain electrode layer.
Further, the second through hole corresponds to the source/drain electrode layer and penetrates through the flat layer and the passivation layer; the conductive layer fills the second via hole and is connected to the source/drain electrode layer.
Further, the method also comprises the following steps: preparing a retaining wall on the flat layer, wherein the retaining wall covers the conductive layer; forming a through hole at the position of the retaining wall corresponding to the conductive layer, and preparing a luminous layer in the through hole; and preparing a cathode on the retaining wall, wherein the cathode covers the light-emitting layer.
The invention also provides a display device comprising the display panel.
The invention has the beneficial effects that: according to the array substrate, the preparation method thereof and the display device, through holes are etched in the flat layer, and the shielding is formed on the side face through the conducting layer, so that light rays on the side face and the front face of the conducting layer enter the thin film transistor structural layer, and the service life of the array substrate is prolonged.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an array substrate in an embodiment.
Fig. 2 is a schematic view of the structure of the first via and the second via in the embodiment.
Fig. 3 is a schematic view of the structure of the conductive layer in the embodiment.
Fig. 4 is a schematic view of a flat layer structure in an embodiment.
Reference numerals in the figures
A substrate 1; a thin film transistor structure layer 2;
a flat layer 4; a conductive layer 5;
a retaining wall 6; a light-emitting layer 7;
a cathode 8; a light shielding layer 21;
a buffer layer 22; an active layer 23;
a gate insulating layer 24; a gate layer 25;
a dielectric layer 26; a source/drain layer 27;
a passivation layer 28; a first through hole 41;
a second through hole 42; and a third through hole 61.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In this application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
Examples
In this embodiment, the display device of the present invention includes an array substrate and a color film substrate.
As shown in fig. 1, the array substrate of the present invention includes a substrate 1, a thin film transistor structure layer 2, and a planarization layer 4; conductive layer 5, barrier wall 6, light-emitting layer 7, and cathode 8.
The substrate 1 is a hard substrate, typically a glass substrate, and serves as a support and a substrate.
The thin film transistor structure layer 2 includes a plurality of thin film transistor devices, wherein each thin film transistor device includes a light shielding layer 21, an active layer 23, a gate insulating layer 24, a gate layer 25, and a source/drain layer 27. In order to include the thin film transistor device, the thin film transistor structure layer 2 further includes a buffer layer 22, a dielectric layer 26, and a passivation layer 28, which serve as an insulating effect.
The light shielding layer 21 is disposed on the upper surface of the substrate 1, the light shielding layer 21 is made of a light shielding material, and the light shielding material is made of metal and includes: molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, or an alloy, the thickness of the light shielding layer 21 is 500 to 2000 angstroms, and the light shielding layer 21 plays a role of shielding light.
The buffer layer 22 is disposed on the light shielding layer 21 and the upper surface of the substrate 1 to play a role of buffering, the material of the buffer layer 22 is an inorganic material, the inorganic material includes silicon oxide or silicon nitride, or is a multi-layer structure, and the thickness of the buffer layer 22 is 1000-5000 a.
The active layer 23 is disposed on the upper surface of the buffer layer 22, and the active layer 23 is made of a semiconductor material including Indium Gallium Zinc Oxide (IGZO) and indium gallium titanium oxide (IZTO), indium Gallium Zinc Titanium Oxide (IGZTO), and the thickness of the active layer 23 is 100-1000 a. The active layer 23 is disposed above the light shielding layer 21, i.e., the active layer 23 is disposed opposite to the light shielding layer 21, and the active layer 23 provides circuit support for the display panel.
The gate insulating layer 24 is disposed on the upper surface of the active layer 23, the gate insulating layer 24 is made of an inorganic material, the inorganic material includes silicon oxide or silicon nitride or a multi-layer thin film structure, and the thickness of the gate insulating layer 24 is 1000 to 3000 a. The gate insulating layer 24 is disposed opposite to the active layer 23, and the gate insulating layer 24 serves to insulate and prevent a short circuit between lines inside the display panel.
The gate layer 25 is disposed on the upper surface of the gate insulating layer 24, and the gate layer 25 is made of a metal material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, or an alloy, or a multilayer thin film structure. The gate layer 25 has a thickness of 2000 to 8000 a, and the gate layer 25 is disposed opposite to the gate insulating layer 24.
The dielectric layer 26 is disposed on the upper surfaces of the gate layer 25, the gate insulating layer 24, the active layer 23 and the buffer layer 22, the dielectric layer 26 is an interlayer insulating layer, the dielectric layer 26 is made of an inorganic material, and the inorganic material comprises silicon oxide or silicon nitride or a multilayer film structure, so as to perform an insulating function and prevent a short circuit. The thickness of the dielectric layer 26 is 2000 to 10000 a. Above the active layer 23 and the light shielding layer 21, a via hole is provided, which facilitates electrical connection between the pixel electrode layer 6 and the active layer 23.
The source/drain layer 27 is disposed on the upper surface of the dielectric layer 26, and the source/drain layer 27 is made of a metal material, where the metal material includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, or is an alloy, or is a multilayer thin film structure. A portion of the metal material is disposed in the via hole, and the source/drain layer 27 is electrically connected to the active layer 23 through the via hole, thereby forming a circuit connection. The thickness of the source/drain layer 27 is 2000 to 8000.
The passivation layer 28 is disposed on the upper surfaces of the dielectric layer 26 and the source/drain layer 27, the passivation layer 28 is made of silicon oxide material, and the thickness of the passivation layer 28 is 1000-5000 a/m. The passivation layer 28 serves as an insulator and insulates the outside water from oxygen.
As shown in fig. 2 and 4, the planarization layer 4 is disposed on the upper surface of the passivation layer 28, and the planarization layer 4 makes the surface of the film flat, which is beneficial to the adhesion of the subsequent film and prevents the detachment phenomenon. The flat layer 4 is provided with a second through hole 42 for providing a channel for the conductive layer 5, and the flat layer 4 is also provided with a first through hole 41, wherein the first through hole 41 is arranged at two sides of the second through hole 42 and at two sides of the source drain electrode layer 27.
The conductive layer 5 is disposed on the upper surface of the flat layer 4, and the conductive layer 5 corresponds to the thin film transistor device, the conductive layer 5 is made of a metal material with high reflectivity, the conductive layer 5 corresponding to the second through hole 42 is filled with the second through hole 42, the conductive layer 5 is electrically connected with the source drain layer 27, circuit support is provided for light emission of the subsequent luminescent material, two ends of the conductive layer 5 respectively cover the inner side wall of the first through hole 41 and extend to the bottom surface of the first through hole 41, and due to the fact that the conductive layer 5 adopts the metal material with high reflectivity, the conductive layer 5 not only has good conductive efficiency, but also can shield light, two ends of the conductive layer 5 cover the inner side wall of the first through hole 41 and extend to the bottom surface of the first through hole 41, a side surface 'retaining wall' is formed, the light on the front surface and the side of the conductive layer 5 can be effectively shielded, and the thin film transistor structure layer 2 is protected.
As shown in fig. 3, the retaining wall 6 is disposed on the flat layer 4 and the conductive layer 5, and the retaining wall 6 fills the first through hole 41 and covers the conductive layer 5 to isolate outside water vapor. The area of the retaining wall 6 corresponding to the conductive layer 5 is provided with a third through hole 61, a light-emitting layer 7 is arranged in the third through hole 61, and when the electric signal is connected, the light-emitting layer 7 can emit light and emit light, so that a picture is displayed.
In order to better explain the invention, the embodiment also provides a preparation method of the array substrate, which comprises the following steps:
and S1, providing a substrate, wherein the substrate is a substrate, generally a glass substrate, and plays a supporting role and a substrate role.
And S2, preparing a functional layer, namely preparing a thin film transistor structure layer on the upper surface of the substrate 1, wherein the preparation step of the thin film transistor structure layer specifically comprises the following steps of.
Cleaning a substrate, depositing a layer of shading material on the upper surface of the substrate, wherein the shading material is metal, and comprises the following steps: molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, or an alloy, is etched to form a pattern by etching treatment, and a light shielding layer having a thickness of 500 to 2000 angstroms is formed, and the light shielding layer plays a role in shielding light.
And depositing a layer of inorganic material on the upper surfaces of the light shielding layer and the substrate, wherein the inorganic material comprises silicon oxide or silicon nitride or has a multilayer structure, so as to form a buffer layer for buffering, and the thickness of the buffer layer is 1000-5000 m.
And depositing a layer of semiconductor material on the upper surface of the buffer layer, wherein the semiconductor material comprises Indium Gallium Zinc Oxide (IGZO) and indium gallium titanium oxide (IZTO), and patterning the semiconductor material to form an active layer, and the thickness of the active layer is 100-1000 m. The active layer is arranged above the shading layer, namely, the active layer is arranged opposite to the shading layer, and the active layer provides circuit support for the array substrate.
And depositing a layer of inorganic material on the upper surface of the active layer, wherein the inorganic material comprises silicon oxide or silicon nitride or a multilayer film structure, and forming a gate insulating layer after patterning treatment, wherein the thickness of the gate insulating layer is 1000-3000 m. The grid insulating layer is arranged opposite to the active layer, and plays a role in insulation to prevent short circuit among all circuits inside the array substrate.
A layer of metal material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., either an alloy or a multi-layered thin film structure is deposited on the upper surface of the gate insulating layer. The pattern of the grid electrode layer is etched by utilizing yellow light, then the grid electrode layer is utilized to be self-aligned, the grid electrode insulating layer is etched, the grid electrode insulating layer exists only under the film layer with the grid electrode layer, the grid electrode insulating layers in other places are etched, the thickness of the grid electrode layer is 2000-8000A, and the grid electrode layer is arranged opposite to the grid electrode insulating layer.
The entire surface of the gate layer is subjected to laser treatment, and after the treatment, the resistance of the semiconductor layer, which is not protected by the gate insulating layer and the gate layer, is significantly reduced, and an n+ conductor layer is formed.
And depositing a dielectric layer on the upper surfaces of the gate layer, the gate insulating layer, the active layer and the buffer layer, wherein the dielectric layer is an interlayer insulating layer, and the dielectric layer is made of an inorganic material, and the inorganic material comprises silicon oxide or silicon nitride or a multilayer film structure, so that the insulating effect is achieved, and short circuit of a circuit is prevented. The thickness of the dielectric layer is 2000-10000A.
After exposure and development, forming through holes above the active layer and the shading layer by adopting a mask plate, and simultaneously making contact holes for connecting signals to the shading layer; the through holes are convenient for the electrical connection of the subsequent film layers.
A layer of metal material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., either as an alloy or as a multi-layered thin film structure is deposited on the upper surface of the dielectric layer. And part of metal material is arranged in the through hole, and after patterning treatment, a source drain electrode layer is formed, and the source drain electrode layer is electrically connected to the active layer through the through hole to form a circuit conduction. The thickness of the source drain electrode layer is 2000-8000.
And depositing a layer of silicon oxide material on the upper surfaces of the dielectric layer and the source drain electrode layer to form a passivation layer, wherein the thickness of the passivation layer is 1000-5000 m. The passivation layer plays an insulating role and an external water-oxygen isolating role.
S3, preparing a flat layer on the upper surface of the dielectric layer, wherein the flat layer enables the surface of the film layer to be flat, is beneficial to the lamination of the film layers such as the conductive layer and the like, and prevents the detachment phenomenon. And preparing a first through hole and a second through hole on the flat layer, wherein the second through hole corresponds to the source drain electrode layer, the first through hole corresponds to two sides of the source drain electrode layer, and the second through hole provides a channel for the conductive layer.
And S4, preparing a conductive layer, namely depositing an indium tin oxide material on the upper surface of the flat layer, filling the second through hole, covering the side wall of the first through hole at two ends of the conductive layer, contacting the bottom surface of the first through hole, and forming the conductive layer after patterning treatment, wherein the conductive layer is electrically connected with the source drain electrode layer through the second through hole, so as to provide circuit support for the light emission of the subsequent luminescent material, and the conductive layer forms a 'shading retaining wall' on the side surface through the first through hole, so that light is prevented from passing through the side surface of the conductive layer, and damage is caused to the structural layer of the thin film transistor.
The beneficial effects of this embodiment lie in: according to the array substrate and the preparation method thereof, through holes are etched in the flat layer, and shielding is formed on the side face through the conducting layer, so that light rays on the side face and the front face of the conducting layer enter the thin film transistor structure layer, and the service life of the array substrate is prolonged.
The above description of the embodiments is only for helping to understand the technical solution of the present application and its core ideas; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. An array substrate is characterized by comprising
A substrate;
the thin film transistor structure layer is arranged on one side surface of the substrate and comprises more than two thin film transistor devices; the flat layer is arranged on one side surface of the thin film transistor structure layer, which is far away from the substrate;
the first through holes penetrate through the flat layer and are arranged on two sides of each thin film transistor device; and
the conductive layer is arranged on the surface of one side of the thin film transistor structure layer far away from the substrate and is electrically connected to the source-drain electrode layer of the thin film transistor structure layer; the conductive layer is made of a metal material with high reflectivity;
the middle part of a conductive layer is opposite to a thin film transistor device, and two ends of the conductive layer extend to a first through hole respectively and are attached to a thin film transistor structure layer at the bottom of the first through hole.
2. The array substrate of claim 1, wherein the thin film transistor structure layer further comprises
A light shielding layer arranged on one side surface of the substrate;
the buffer layer is arranged on the surface of the substrate and covers the shading layer;
an active layer arranged on one side surface of the buffer layer away from the substrate;
the grid insulation layer is arranged on the surface of one side of the active layer, which is far away from the buffer layer;
the grid electrode layer is arranged on one side surface of the grid electrode insulating layer, which is far away from the active layer;
the dielectric layer is arranged on the surface of one side, far away from the substrate, of the buffer layer, and covers the active layer, the gate insulating layer and the gate layer;
the source-drain electrode layer is arranged on one side surface of the dielectric layer, which is far away from the buffer layer, wherein the source-drain electrode layer partially penetrates through the dielectric layer and the buffer layer and is connected to the shading layer; and
the passivation layer is arranged on the surface of one side, far away from the buffer layer, of the dielectric layer, wherein the passivation layer covers the source drain layer;
the thin film transistor device comprises the shading layer, the active layer, the gate insulating layer, the gate layer and the source drain electrode layer.
3. The array substrate of claim 2, wherein,
and a second through hole is formed in the flat layer corresponding to the source drain electrode layer, and the conducting layer fills the second through hole and is connected to the source drain electrode layer.
4. The array substrate of claim 2, wherein the conductive layer is a metallic material.
5. The array substrate of claim 1, further comprising
The retaining wall is arranged on one side surface of the flat layer, which is far away from the thin film transistor structure layer, and a third through hole is formed in the retaining wall corresponding to the conductive layer;
a light emitting layer disposed in the third via hole and connected to the conductive layer; and
and the cathode is arranged on one side surface of the retaining wall, which is far away from the flat layer, and the cathode covers the light-emitting layer.
6. The preparation method of the array substrate is characterized by comprising the following steps of:
providing a substrate;
preparing a thin film transistor structure layer on the substrate, wherein the thin film transistor structure layer comprises more than two thin film transistor devices;
preparing a flat layer on the thin film transistor structure layer;
etching a first through hole and a second through hole on the flat layer, wherein the first through hole is arranged on two sides of each thin film transistor device, and the second through hole is opposite to the thin film transistor device;
and preparing a layer of high-reflectivity metal material on the flat layer, wherein the metal material fills the second through hole, extends to the inner wall of the first through hole, is attached to the thin film transistor structure layer at the bottom of the first through hole, and is subjected to patterning treatment to form a conductive layer.
7. The method for manufacturing an array substrate according to claim 6, wherein the specific manufacturing steps of the thin film transistor structure layer are as follows:
depositing a light shielding layer on the substrate;
depositing a buffer layer on the substrate, wherein the material of the buffer layer comprises at least one of silicon nitride or silicon oxide;
depositing a layer of semiconductor material on the buffer layer, and forming an active layer after carrying out local conductor formation on the semiconductor material;
preparing a gate insulating layer on the active layer;
preparing a gate electrode layer on the gate insulating layer;
depositing a dielectric layer on the gate layer, gate insulating layer, active layer and buffer;
etching a through hole on the dielectric layer, wherein the through hole penetrates through the dielectric layer and the buffer layer;
preparing a source-drain electrode layer on the dielectric layer, wherein the source-drain electrode layer penetrates through the through hole to be connected to the shading layer;
and depositing a passivation layer on the dielectric layer and the source drain electrode layer.
8. The method for manufacturing an array substrate according to claim 7, wherein,
the second through hole corresponds to the source drain electrode layer and penetrates through the flat layer and the passivation layer; the conductive layer fills the second via hole and is connected to the source/drain electrode layer.
9. The method for manufacturing an array substrate according to claim 6, further comprising the steps of:
preparing a retaining wall on the flat layer, wherein the retaining wall covers the conductive layer;
forming a through hole at the position of the retaining wall corresponding to the conductive layer, and preparing a luminous layer in the through hole;
and preparing a cathode on the retaining wall, wherein the cathode covers the light-emitting layer.
10. A display device comprising the array substrate of any one of claims 1 to 5.
CN202010550081.8A 2020-06-16 2020-06-16 Array substrate, preparation method thereof and display device Active CN111739910B (en)

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