CN112309968A - Display panel manufacturing method and display panel - Google Patents
Display panel manufacturing method and display panel Download PDFInfo
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- CN112309968A CN112309968A CN202011137602.3A CN202011137602A CN112309968A CN 112309968 A CN112309968 A CN 112309968A CN 202011137602 A CN202011137602 A CN 202011137602A CN 112309968 A CN112309968 A CN 112309968A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The application provides a display panel manufacturing method and a display panel, wherein the display panel manufacturing method includes the steps that when a source drain electrode of the display panel is manufactured, a double-layer conducting layer covering a display area and an edge area is formed at first, and then the source drain electrode with the double-layer conducting layer and the edge electrode with a single-layer conducting layer are formed through two times of continuous etching operation on the double-layer conducting layer; the conductivity of the source and drain electrodes is improved by the double-layer conducting layer structure; meanwhile, the manufacturing method of the display panel combines the manufacturing process of the edge electrode and the manufacturing process of the source and drain electrodes, and the edge electrode and the source and drain electrodes are manufactured simultaneously through the same deposition and etching process, so that the operation of independently manufacturing the edge electrode is omitted, the manufacturing process of the display panel is simplified, and the production efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel and a manufacturing method thereof.
Background
An OLED (Organic Light Emitting Diode) display has the performance characteristics of self-luminescence, low driving voltage, high luminous efficiency, short response time, high contrast, wide viewing angle, and the like, and has many advantages of flexible display, large-area full-color display, and the like, and is considered to be a display with the most potential development in the industry.
The OLED display panel generally has a display area and an edge area, the display area is mainly used for achieving a display function of the display panel, and the edge area is provided with an edge electrode, such as a binding trace and a binding pad, for electrically connecting the display area with an external signal element. The layered structure of the OLED display panel comprises an array substrate and a pixel defining layer arranged on the array substrate; a thin film transistor device is arranged in the array substrate and is provided with a source electrode and a drain electrode; an anode, a light emitting function layer, and a cathode for realizing a light emitting function are provided in the pixel defining layer. In the prior art, a source electrode and a drain electrode are made of copper metal, and an anode is made of silver or silver alloy; in the manufacturing process of the OLED display panel, the edge electrode arranged in the edge area cannot be manufactured with the source and drain electrodes or the anode through the same manufacturing process, because if the edge electrode is manufactured by copper or silver alloy, the edge electrode is easily corroded by etching liquid in the subsequent manufacturing process, so that the edge electrode fails; therefore, in the prior art, the edge electrode is made of a metal or alloy material which is stable in chemical property and not easy to be corroded by the etching solution, but a separate edge electrode deposition, photomask and etching process needs to be added, so that the OLED display panel manufacturing process is complicated, the production cost is not reduced, and the production efficiency is not improved.
Disclosure of Invention
Based on the defects in the prior art, the application provides a display panel manufacturing method and a display panel, when a source drain electrode is manufactured, a double-layer conducting layer covering a display area and an edge area is formed, and a source drain electrode and an edge electrode are formed through two times of continuous etching operations on the double-layer conducting layer, so that the problem of complicated process caused by manufacturing the edge electrode through a single process in the prior art is solved.
The application provides a display panel manufacturing method, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a display area and an edge area;
manufacturing an array layer on the substrate base plate, wherein the array layer comprises an interlayer insulating layer;
manufacturing a double-layer conducting layer on the interlayer insulating layer, wherein the double-layer conducting layer comprises a first conducting layer and a second conducting layer laminated on the first conducting layer, the double-layer conducting layer corresponding to the display area forms a source drain electrode, and the double-layer conducting layer corresponding to the edge area forms an original edge electrode;
removing the second conductive layer in the original edge electrode to form an edge electrode;
manufacturing a passivation layer covering the source drain electrode and the edge electrode;
forming a first opening exposing the source and drain electrodes and a second opening exposing the edge electrode on the passivation layer;
and manufacturing a pixel defining layer on the passivation layer, wherein the pixel defining layer comprises an anode, and the anode is electrically connected with the source and drain electrodes through the first opening.
According to an embodiment of the present application, the first conductive layer is made of indium tin oxide and the second conductive layer is made of copper.
According to an embodiment of the present application, before the fabricating the pixel defining layer, the method further includes: and manufacturing a flat layer on the passivation layer.
According to an embodiment of the application, the array layer including set up in semiconductor layer on the substrate base plate, set up in gate insulation layer on the semiconductor layer and set up in gate on the gate insulation layer, the interlayer insulation layer covers semiconductor layer, gate insulation layer with the gate, source leakage electrode through set up in on the interlayer insulation layer the trompil with semiconductor layer electric connection.
According to an embodiment of the present application, the pixel defining layer further includes a light emitting functional layer disposed on the anode, and a cathode disposed on the light emitting functional layer.
According to an embodiment of the present application, a method for forming the source-drain electrode and the edge electrode includes:
forming the double-layer conductive layer of an entire surface type on the interlayer insulating layer by a vapor deposition method;
etching the double-layer conducting layer through a first etching process to form the source drain electrode and the original edge electrode;
and etching and removing the second conducting layer in the original edge electrode by a second etching process to form the edge electrode.
The application provides a display panel, which is manufactured by the display panel manufacturing method.
The present application also provides a display panel, including:
the substrate comprises a display area and an edge area;
the array layer is arranged on the substrate and comprises an interlayer insulating layer, a source drain electrode is arranged on the interlayer insulating layer corresponding to the display area, an edge electrode is arranged on the interlayer insulating layer corresponding to the edge area, the source drain electrode comprises a first conducting layer and a second conducting layer arranged on the first conducting layer, and the edge electrode comprises the first conducting layer;
a passivation layer disposed on the array layer;
the pixel electrode layer comprises an anode, and the anode is electrically connected with the source and drain electrodes through the first opening on the passivation layer.
According to an embodiment of the present disclosure, the first conductive layer is an ito layer, and the second conductive layer is a cu layer.
According to an embodiment of the present application, the edge electrode is exposed through a second opening on the passivation layer.
The beneficial effect of this application is: according to the display panel manufacturing method and the display panel, when the source drain electrode of the display panel is manufactured, firstly, a double-layer conducting layer covering a display area and an edge area is formed, and then the source drain electrode with the double-layer conducting layer and the edge electrode with a single-layer conducting layer are formed through two times of continuous etching operation on the double-layer conducting layer; the conductivity of the source and drain electrodes is improved by the double-layer conducting layer structure; meanwhile, the manufacturing method of the display panel combines the manufacturing process of the edge electrode and the manufacturing process of the source and drain electrodes, and the edge electrode and the source and drain electrodes are manufactured simultaneously through the same deposition and etching process, so that the operation of independently manufacturing the edge electrode is omitted, the manufacturing process of the display panel is simplified, and the production efficiency is improved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a display panel after an interlayer insulating layer is manufactured in a manufacturing method of the display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a display panel manufacturing method according to an embodiment of the present disclosure after a double-layer conductive layer is manufactured;
fig. 4 is a schematic structural diagram of the double-layer conductive layer after a first etching process is performed on the double-layer conductive layer in the display panel manufacturing method according to the embodiment of the present application;
fig. 5 is a schematic structural diagram of a display panel manufacturing method according to an embodiment of the present disclosure after a planarization layer is manufactured;
fig. 6 is a schematic structural diagram of a display panel finally manufactured by the display panel manufacturing method according to the embodiment of the present application.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. Directional phrases used in this application, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting. In the drawings, elements having similar structures are denoted by the same reference numerals.
The embodiment of the application provides a manufacturing method of a display panel, which indicates that: when the source and drain electrodes of the display panel are manufactured, the double-layer conducting layer covering the display area and the edge area is firstly formed, and then the source and drain electrodes and the edge electrode are formed through two times of continuous etching operation on the double-layer conducting layer, so that the manufacturing process of the edge electrode is simplified, the production cost of the display panel is reduced, and the production efficiency is improved.
Fig. 1 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure. The manufacturing method of the display panel comprises the following steps:
step S1, referring to fig. 2, a substrate 10 is provided, where the substrate 10 has a display area AA and an edge area NA.
Alternatively, the base substrate 10 may be made of a hard material such as glass, or may be made of a flexible material such as polyimide.
Step S2, referring to fig. 2, an array layer 20 is fabricated on the substrate 10, where the array layer 20 includes an interlayer insulating layer 25.
Specifically, the method further includes the following steps before the array layer 20 is fabricated on the substrate 10: depositing a metal layer on the substrate 10, and performing an etching operation on the metal layer to form a light shielding layer 51 and a first electrode plate 52, wherein the metal layer may be made of molybdenum, titanium, copper, or the like; the buffer layer 50 covering the light-shielding layer 51 and the first electrode plate 52 is formed by deposition or coating, and the buffer layer 50 may be formed of silicon nitride, silicon oxide, or the like.
Further, the method of fabricating the array layer 20 includes the steps of: depositing a semiconductor material layer on the buffer layer 50, wherein the semiconductor material layer may be indium gallium zinc oxide; etching the semiconductor material layer to form a semiconductor layer 22 and a second electrode plate 21, and forming a storage capacitor between the second electrode plate 21 and the first electrode plate 52; forming a gate insulating layer 23 on the semiconductor layer 22; forming a gate electrode 24 on the gate insulating layer 23; performing plasma treatment on the semiconductor layer 22, thereby forming doped regions at both ends of the semiconductor layer 22; forming an interlayer insulating layer 25 covering the semiconductor layer 22, the gate insulating layer 23, the gate electrode 24, and the second electrode plate 21; an opening is formed in the interlayer insulating layer 25 corresponding to the doped region of the semiconductor layer 22.
Step S3, referring to fig. 4, a double-layer conductive layer is fabricated on the interlayer insulating layer 25, where the double-layer conductive layer includes a first conductive layer 261 and a second conductive layer 262 stacked on the first conductive layer 261, the double-layer conductive layer corresponding to the display area AA forms a source/drain electrode 26, and the double-layer conductive layer corresponding to the margin area NA forms an original margin electrode 27'.
Specifically, the method for manufacturing the source-drain electrode 26 and the original edge electrode 27' includes the following steps: referring to fig. 3, the first conductive layer 261 and the second conductive layer 262 are formed in a full-surface type on the interlayer insulating layer 25 by a vapor deposition method, and the first conductive layer 261 and the second conductive layer 262 penetrate into the opening of the interlayer insulating layer 25 and are electrically connected to the semiconductor layer 22; referring to fig. 4, the first conductive layer 261 and the second conductive layer 262 are etched by a first etching process to form the source/drain electrode 26 and the original edge electrode 27'; after the etching is completed, the photoresist layer disposed on the source/drain electrode 26 is retained, and the photoresist layer disposed on the original edge electrode 27 'is removed, so as to further etch the original edge electrode 27'.
Further, the first conductive layer 261 is made of indium tin oxide, and the second conductive layer 262 is made of copper. It should be understood that, the first conductive layer 261 and the second conductive layer 262 are made of different conductive materials, respectively, which can ensure that the etching solution for etching the second conductive layer 262 does not corrode the first conductive layer 261, and in this embodiment, the etching solution for etching the copper metal does not corrode the indium tin oxide, thereby ensuring that the performance of the indium tin oxide conductive layer is stable.
It should be noted that the source-drain electrode 26 manufactured by the method provided in this embodiment includes a first conductive layer 261 made of indium tin oxide and a second conductive layer 262 made of copper, and the conductivity of the source-drain electrode 26 is further improved by a metal copper layer in the source-drain electrode 26.
Step S4, referring to fig. 4 and 5, removes the second conductive layer 262 in the primitive edge electrode 27' to form the edge electrode 27.
Specifically, the second conductive layer 262 is removed by a second etching process. It should be noted that, after the first etching process is completed, the photoresist layer disposed on the source/drain electrode 26 is retained, and the photoresist layer disposed on the original edge electrode 27 'is removed, so that when the second etching process is used for etching, the etching liquid only etches the original edge electrode 27'; the etching solution used in the second etching process is an etching solution capable of etching copper, so that the etching solution does not damage the second conductive layer 262, thereby ensuring the stable performance of the formed edge electrode 27.
Step S5, referring to fig. 5, a passivation layer 30 covering the source-drain electrode 26 and the edge electrode 27 is fabricated.
Optionally, the passivation layer 30 is manufactured by a vapor deposition process, the material for manufacturing the passivation layer 30 may be silicon oxide or silicon nitride, and the thickness of the passivation layer is 1000 to 5000 angstroms.
Optionally, after the passivation layer 30 is manufactured, the method further includes: fabricating a flat layer 60 on the passivation layer 30, wherein the flat layer 60 is disposed in the display area AA; and manufacturing a contact hole corresponding to the source/drain electrode 26 on the flat layer 60 by a yellow light etching process. It should be noted that, when the contact holes on the planarization layer 60 and the planarization layer 60 are made, the passivation layer 30 is not etched and punched, and the passivation layer 30 completely covers the source/drain electrode 26 and the edge electrode 27, so as to protect the source/drain electrode 26 and the edge electrode 27 from oxidation; meanwhile, the heat generated during the process of fabricating the planarization layer 60 may cause the edge electrode 27 to change from the amorphous state to the crystalline state, and the edge electrode 27 in the crystalline state is not easily corroded by the etching solution in the subsequent etching process.
Optionally, the planarization layer 60 includes a first planarization layer 61 and a second planarization layer 62 for optimal planarization; the thickness of the planarization layer 60 is 0.5 to 3 micrometers.
In step S6, referring to fig. 5, a first opening 31 exposing the source/drain electrode 26 and a second opening 32 exposing the edge electrode 27 are formed on the passivation layer 30.
Step S7, as shown in fig. 5 and 6, fabricating a pixel defining layer 40 on the passivation layer 60, where the pixel defining layer 40 includes an anode 41, and the anode 41 is electrically connected to the source/drain electrode 26 through the first opening 31.
Optionally, the anode 41 comprises three conductive layers, i.e. an ito layer, a ag layer, and an ito layer; when the anode 41 is manufactured, three conductive layers covering the entire surfaces of the display area AA and the edge area NA are formed by a vapor deposition method, and then the three conductive layers of the edge area NA are removed by an etching process, and the three conductive layers of the display area AA are patterned to form the anode 41. It should be noted that, because the indium tin oxide in the three conductive layers is amorphous, when the edge area NA is etched, neither the silver etching solution nor the amorphous etching solution of indium tin oxide can corrode the crystalline edge electrode 27, thereby ensuring stable performance of the edge electrode 27.
Specifically, the anode 41 is electrically connected to the source/drain electrode 26 through a contact hole disposed on the planarization layer 60 and the first opening 31.
Further, the pixel defining layer 40 further includes a defining layer 44, a plurality of concave holes are disposed on the defining layer 44, and the anode 41 is disposed corresponding to the concave holes; the pixel defining layer 40 further includes a light-emitting functional layer 42 disposed on the anode 41, and a cathode 43 disposed on the light-emitting functional layer 42; the anode 41, the light-emitting functional layer 42, and the cathode 43 are directly stacked in the recess hole, and the anode 41 and the light-emitting functional layer 42 are separated by the defining layer 44 in a region outside the recess hole. Alternatively, the delimiting layer 44 may include a first delimiting layer 441 and a second delimiting layer 442 stacked on the first delimiting layer 441.
Further, the display panel manufacturing method further includes a step of manufacturing a thin film encapsulation layer 70 on the pixel defining layer 40. The thin film encapsulation layer 70 may be a stacked structure of an inorganic layer, an organic layer, and an inorganic layer.
To sum up, the display panel manufacturing method provided by the embodiment of the present application provides that when manufacturing the source and drain electrodes of the display panel, the double-layer conductive layer covering the display region and the edge region is formed first, and then the source and drain electrodes having the double-layer conductive layer and the edge electrode having the single-layer conductive layer are formed by performing two continuous etching operations on the double-layer conductive layer, so that the conductivity of the source and drain electrodes is improved, the manufacturing process of the edge electrode is simplified, and the manufacturing cost of the display panel is reduced, and the production efficiency is improved.
The embodiment of the application also provides a display panel, and the display panel is manufactured by adopting the manufacturing method of the display panel.
The embodiment of the present application further provides a display panel, as shown in fig. 6, the display panel includes a substrate base plate 10, an array layer 20 disposed on the substrate base plate 10, a passivation layer 30 disposed on the array layer 20, and a pixel defining layer 40 disposed on the passivation layer 30. The substrate base plate 10 includes a display area AA and an edge area NA.
Optionally, the display panel further includes a light shielding layer 51 and a first electrode plate 52 disposed on the substrate 10, a buffer layer 50 disposed on the substrate 10 and covering the light shielding layer 51, a planarization layer 60 disposed on the passivation layer 30, and a thin film encapsulation layer 70 disposed on the pixel defining layer 40; the array layer 20 is disposed on the buffer layer 50, and the pixel defining layer 40 is disposed on the planarization layer 60. The buffer layer 50 is further provided with a second polar plate 21, the first polar plate 52 and the second polar plate 21 are electrically insulated by the buffer layer 50, and the first polar plate 52 and the second polar plate 21 form a storage capacitor. Optionally, the planarization layer 60 includes a first planarization layer 61 and a second planarization layer 62 for optimal planarization.
Alternatively, the base substrate 10 may be made of a hard material such as glass, or may be made of a flexible material such as polyimide. The light shielding layer 51 is made of an opaque metal material, such as molybdenum, titanium, or copper; the first electrode plate 52 and the light shielding layer 51 may be made of the same material. The buffer layer 50 has a single-layer or multi-layer thin film structure made of silicon oxide or silicon nitride.
The array layer 20 includes a semiconductor layer 22 disposed on the buffer layer 50, a gate insulating layer 23 disposed on the semiconductor layer 22, a gate electrode 24 disposed on the gate insulating layer 23, and an interlayer insulating layer 25 disposed on the buffer layer 50 and covering the semiconductor layer 22, the gate insulating layer 23, and the gate electrode 24. A source/drain electrode 26 is disposed on the interlayer insulating layer 25 corresponding to the display area AA, and an edge electrode 27 is disposed on the interlayer insulating layer 25 corresponding to the edge area NA. Wherein the source and drain electrodes 26 are electrically connected to the semiconductor layer 22 through via holes disposed on the interlayer insulating layer 25.
Further, the source/drain electrode 26 includes a first conductive layer 261 and a second conductive layer 262 disposed on the first conductive layer 261, and the edge electrode 27 includes the first conductive layer 261. It should be noted that, in this embodiment, the source/drain electrode 26 includes two conductive layers, which ensures that the source/drain electrode 26 has good conductivity; meanwhile, the edge electrode 27 is made of a conductive layer which is the same as one of the source and drain electrodes 26, the manufacturing process of the edge electrode 27 and the manufacturing process of the source and drain electrodes 26 can be combined, and the edge electrode 27 and the source and drain electrodes 26 are simultaneously manufactured through the same deposition and etching process, so that the operation of independently manufacturing the edge electrode is omitted, the manufacturing process of the display panel is facilitated to be simplified, and the cost of the display panel is reduced.
Optionally, the first conductive layer 261 is an ito layer, and the second conductive layer 262 is a cu layer. It should be understood that the metal copper layer in the source and drain electrodes 26 further improves the conductivity of the source and drain electrodes 26; the ito in the edge electrode 27 is crystallized in the subsequent process of the display panel and is not easily corroded by the etching solution in the subsequent process, thereby ensuring the stability of the performance of the edge electrode 27.
As shown in fig. 5 and 6, the passivation layer 30 is provided with a first opening 31 for exposing the source/drain electrode 26 and a second opening 32 for exposing the edge electrode, and the planarization layer 60 is provided with a contact hole corresponding to the first opening 31 for exposing the source/drain electrode 26.
The pixel defining layer 40 further includes a defining layer 44, an anode 41, a light-emitting functional layer 42, and a cathode 43, wherein a plurality of concave holes are disposed on the defining layer 44, the anode 41, the light-emitting functional layer 42, and the cathode 43 are sequentially stacked in the concave holes, and in an area outside the concave holes, the anode 41 and the light-emitting functional layer 42 are separated by the defining layer 44. Alternatively, the delimiting layer 44 may include a first delimiting layer 441 and a second delimiting layer 442 stacked on the first delimiting layer 441.
The anode 41 is electrically connected to the source/drain electrode 26 through a contact hole formed in the planarization layer 60 and the first opening 31.
Further, the display panel further includes a thin film encapsulation layer 70 disposed on the pixel defining layer 40; the thin film encapsulation layer 70 may be a stacked structure of an inorganic layer, an organic layer, and an inorganic layer for sealing and protecting internal devices of the display panel.
In summary, the display panel provided in the embodiment of the present application includes a source drain electrode and an edge electrode, where the source drain electrode has a first conductive layer and a second conductive layer, and the edge electrode has the first conductive layer; the above structural features ensure that the source-drain electrode 26 has good conductivity, and at the same time, the edge electrode is made of a conductive layer identical to one of the source-drain electrodes, so that the edge electrode manufacturing process can be combined with the source-drain electrode manufacturing process, and the edge electrode and the source-drain electrode are simultaneously manufactured through the same deposition and etching process, thereby omitting the operation of independently manufacturing the edge electrode, facilitating the simplification of the display panel manufacturing process, and reducing the display panel cost.
It should be noted that, although the present application has been described with reference to specific examples, the above-mentioned examples are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be limited by the appended claims.
Claims (10)
1. A manufacturing method of a display panel is characterized by comprising the following steps:
providing a substrate, wherein the substrate is provided with a display area and an edge area;
manufacturing an array layer on the substrate base plate, wherein the array layer comprises an interlayer insulating layer;
manufacturing a double-layer conducting layer on the interlayer insulating layer, wherein the double-layer conducting layer comprises a first conducting layer and a second conducting layer laminated on the first conducting layer, the double-layer conducting layer corresponding to the display area forms a source drain electrode, and the double-layer conducting layer corresponding to the edge area forms an original edge electrode;
removing the second conductive layer in the original edge electrode to form an edge electrode;
manufacturing a passivation layer covering the source drain electrode and the edge electrode;
forming a first opening exposing the source and drain electrodes and a second opening exposing the edge electrode on the passivation layer;
and manufacturing a pixel defining layer on the passivation layer, wherein the pixel defining layer comprises an anode, and the anode is electrically connected with the source and drain electrodes through the first opening.
2. The method according to claim 1, wherein the first conductive layer is made of indium tin oxide and the second conductive layer is made of copper.
3. The method for manufacturing a display panel according to claim 1, wherein before the manufacturing of the pixel defining layer, the method further comprises: and manufacturing a flat layer on the passivation layer.
4. The method according to claim 1, wherein the array layer comprises a semiconductor layer disposed on the substrate, a gate insulating layer disposed on the semiconductor layer, and a gate disposed on the gate insulating layer, the interlayer insulating layer covers the semiconductor layer, the gate insulating layer, and the gate, and the source and drain electrodes are electrically connected to the semiconductor layer through an opening disposed on the interlayer insulating layer.
5. The method according to claim 1, wherein the pixel defining layer further includes a light-emitting functional layer disposed on the anode and a cathode disposed on the light-emitting functional layer.
6. The method for manufacturing the display panel according to claim 1, wherein the method for forming the source-drain electrode and the edge electrode comprises:
forming the double-layer conductive layer of an entire surface type on the interlayer insulating layer by a vapor deposition method;
etching the double-layer conducting layer through a first etching process to form the source drain electrode and the original edge electrode;
and etching and removing the second conducting layer in the original edge electrode by a second etching process to form the edge electrode.
7. A display panel manufactured by the display panel manufacturing method according to any one of claims 1 to 6.
8. A display panel, comprising:
the substrate comprises a display area and an edge area;
the array layer is arranged on the substrate and comprises an interlayer insulating layer, a source drain electrode is arranged on the interlayer insulating layer corresponding to the display area, an edge electrode is arranged on the interlayer insulating layer corresponding to the edge area, the source drain electrode comprises a first conducting layer and a second conducting layer arranged on the first conducting layer, and the edge electrode comprises the first conducting layer;
a passivation layer disposed on the array layer;
the pixel electrode layer comprises an anode, and the anode is electrically connected with the source and drain electrodes through the first opening on the passivation layer.
9. The display panel according to claim 8, wherein the first conductive layer is an indium tin oxide layer, and the second conductive layer is a copper metal layer.
10. The display panel of claim 8, wherein the edge electrode is exposed through a second opening in the passivation layer.
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| CN113192847A (en) * | 2021-04-01 | 2021-07-30 | 武汉华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
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