CN217881570U

CN217881570U - Display panel

Info

Publication number: CN217881570U
Application number: CN202221978699.5U
Authority: CN
Inventors: 张磊; 覃事建
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-07-28
Filing date: 2022-07-28
Publication date: 2022-11-22
Anticipated expiration: 2032-07-28

Abstract

The utility model discloses a display panel. The display panel comprises a substrate, and a metal conducting layer, a passivation layer, a metal protection layer and a blocking layer which are positioned on the substrate; the substrate comprises a display area and a binding area positioned outside the display area; a groove region is formed on the passivation layer on the binding region; the metal protective layer is at least partially positioned in the groove area and covers the metal conductive layer positioned at the bottom of the groove area; the barrier layer is positioned at the side edge of the metal protection layer. The metal protection layer can prevent that the metal conducting layer is not corroded by the etching liquid medicine, and simultaneously, the barrier layer can prevent that the etching liquid medicine from invading from the side and causing the corruption to metal protection layer and metal conducting layer. Therefore, the stability of the metal conducting layer of the binding area can be improved, a mask is not required to be added, the production cost is reduced, and the product yield is improved.

Description

Display panel

Technical Field

The utility model relates to a show technical field, especially relate to a display panel.

Background

In the prior art, in order to reduce the wiring impedance, a Cu (copper) wiring is used as a transistor device such as a gate, a source, and a drain in an OLED (organic light emitting diode) display panel, since the Cu has poor stability and is easily oxidized when exposed to an external environment as shown in fig. 1, the Cu cannot be directly used as a bonding metal in a bonding region.

At present, in a top-emitting TFT (thin film transistor) structure, a pad of Mo-Ti (molybdenum titanium alloy) is often used to cover Cu in a bonding region, or a metal layer in the bonding region is a three-layer metal (Mo-Ti/Cu/Mo-Ti) structure, so as to improve the stability of the bonding metal and prevent Cu corrosion during silver etching.

However, in the above scheme, a mask (mask) needs to be added, a taper tailing phenomenon is easily generated in the three-layer metal structure, and as shown in fig. 2, the length of the taper tailing reaches 0.0657um. These problems result in increased production costs and reduced product yields.

SUMMERY OF THE UTILITY MODEL

Based on not enough among the above-mentioned prior art, the utility model aims at providing a display panel can improve the stability of binding district metal level, and reduction in production cost promotes the product yield.

In order to achieve the above object, the present invention provides a display panel, which includes a substrate, and a metal conductive layer, a passivation layer, a metal protection layer and a barrier layer on the substrate;

the substrate comprises a display area and a binding area positioned outside the display area;

a groove region is formed on the passivation layer on the binding region;

the metal protective layer is at least partially positioned in the groove area and covers the metal conductive layer positioned at the bottom of the groove area;

the barrier layer is positioned at the side edge of the metal protection layer.

Optionally, the groove region includes a first groove and a second groove located outside the first groove, the metal protection layer covers at least a portion located in the first groove, and the barrier layer is at least partially located in the second groove.

Optionally, a portion of the metal protection layer is located in the second recess and in contact with the barrier layer.

Optionally, the depth of the second groove is greater than or equal to the depth of the first groove.

Optionally, a cross-sectional shape of the second groove along the light exit direction includes at least one of a rectangle and a trapezoid.

Optionally, the width of the portion of the metal conductive layer covered by the groove region is 3 micrometers to 5 micrometers.

Optionally, the barrier layer has a thickness of 0.5 to 4 microns.

Optionally, the light emitting structure layer further comprises an anode layer, a cathode layer and a light emitting layer, the light emitting layer is located between the anode layer and the cathode layer, and a part of the anode layer forms the metal protection layer.

Optionally, the metal conductive layer further includes a first metal layer and a second metal layer, a dielectric layer is formed between the first metal layer and the second metal layer, the first metal layer is located on the substrate, the dielectric layer covers the first metal layer, the second metal layer is located on the dielectric layer, and a portion of the second metal layer is located at the bottom of the groove region.

Optionally, the display device further includes an active layer, an insulating layer, a light shielding layer and a buffer layer, wherein the light shielding layer is located on the display region of the substrate, the buffer layer covers the light shielding layer and the substrate, the active layer is located on the buffer layer, the insulating layer is located on the active layer, the first metal layer is located on the insulating layer, and the dielectric layer covers the active layer, the insulating layer, the light shielding layer and the buffer layer.

Compared with the prior art, the beneficial effects of the utility model include: the display panel of the utility model comprises a substrate, a metal conductive layer, a passivation layer, a metal protective layer and a barrier layer, wherein the metal conductive layer, the passivation layer, the metal protective layer and the barrier layer are arranged on the substrate; the substrate comprises a display area and a binding area positioned outside the display area; a groove region is formed on the passivation layer on the binding region; the metal protective layer is at least partially positioned in the groove area and covers the metal conductive layer positioned at the bottom of the groove area; the barrier layer is positioned at the side edge of the metal protection layer. The metal protection layer can prevent the metal conducting layer from being corroded by etching liquid medicine (such as silver acid), and meanwhile, the barrier layer can prevent the etching liquid medicine from invading from the side edge to corrode the metal protection layer and the metal conducting layer. Therefore, the stability of the metal conducting layer of the binding area can be improved, a mask is not required to be added, the production cost is reduced, and the product yield is improved.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art bonding region metal corrosion;

FIG. 2 is a prior art schematic diagram of a second metal layer taper tail;

fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a barrier layer and a metal protection layer according to an embodiment of the present invention;

FIG. 5 is a schematic view of a groove region according to an embodiment of the present invention;

FIG. 6 is a top view of the region P of FIG. 5;

FIG. 7 is a schematic diagram of an undercut structure of a display panel according to an embodiment of the present invention;

fig. 8 is a first flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

fig. 9 is a second flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

fig. 10 is a third flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

fig. 11 is a flow structure diagram of a method for manufacturing a display panel according to an embodiment of the present invention;

fig. 12 is a fifth flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

fig. 13 is a sixth flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

fig. 14 is a seventh flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

fig. 15 is a flow structure diagram eight of the display panel manufacturing method according to the embodiment of the present invention;

fig. 16 is a ninth flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

fig. 17 is a flow chart illustrating a manufacturing method of a display panel according to an embodiment of the present invention;

fig. 18 is a flow chart illustrating a method for manufacturing a display panel according to an embodiment of the present invention.

Detailed Description

The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments in which the invention may be practiced. In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and to simplify the description, but do not indicate or imply that the module or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

The utility model provides a display panel, as shown in fig. 3 to 5, comprising a substrate 1, a metal conductive layer 2, a passivation layer 3, a metal protection layer 4 and a barrier layer 5 which are positioned on the substrate 1; the substrate 1 includes a display area 101 and a binding area 102 located outside the display area 101; the passivation layer 3 on the bonding region 102 is formed with a groove region 31; the metal protection layer 4 is at least partially positioned in the groove area 31 and covers the metal conducting layer 2 positioned at the bottom of the groove area 31; the barrier layer 5 is located at the side of the metal protection layer 4.

Adopt above-mentioned structure, metal protection layer 4 can prevent that metal conducting layer 2 from not being corroded by the etching liquid medicine when etching, and simultaneously, barrier layer 5 can prevent that the etching liquid medicine from the side invasion to cause the corruption to metal protection layer 4 and metal conducting layer 2. Therefore, the stability of the metal conducting layer 2 of the binding region 102 can be improved, a mask does not need to be added, the production cost is reduced, and the product yield is improved.

In the present embodiment, the material of the metal protection layer 4 may include, but is not limited to, IZO (indium zinc oxide), and APC alloy, which is an alloy of silver (Ag), palladium (Pd), and copper (Cu). The barrier layer 5 may be made of a material that is resistant to etching liquid. The substrate 1 is a glass substrate. The passivation layer 3 can be made of SiO ₂ (silicon dioxide), and the like.

In one embodiment, as shown in fig. 4 and 5, the groove region 31 includes a first groove 311 and a second groove 312 located outside the first groove 311, the metal protection layer 4 is at least partially covered in the first groove 311, and the barrier layer 5 is at least partially located in the second groove 312. The barrier layer 5 can prevent the etching solution from entering the first recess 311 from the second recess 312, and corroding the metal protection layer 4 and the metal conductive layer 2.

In one embodiment, a portion of the metal protection layer 4 is located in the second groove 312 and contacts the barrier layer 5. During etching, the metal protection layer 4 is formed in the first recess 311 and the second recess 312, and then the barrier layer 5 is formed in the second recess 312.

As shown in fig. 6, in this embodiment, the second groove 312 may be located at the periphery of the metal conductive layer 2 on the bonding region 102, so that the barrier layer in the second groove 312 may perform barrier protection on the periphery of the metal conductive layer 2 on the bonding region 102.

In one embodiment, the depth of the second recess 312 is greater than or equal to the depth of the first recess 311. This prevents the etching liquid from invading into the metal conductive layer 2 from the bottom.

In one embodiment, a cross-sectional shape of the second groove 312 along the light-emitting direction includes at least one of a rectangle and a trapezoid. Therefore, the groove can be formed by better patterning when etching.

In one embodiment, the width L of the portion of the metal conductive layer 2 covered by the recessed region 31 is 3 to 5 microns. Specifically, the width L may be 4.25 micrometers. Thus, the metal conductive layer 2 can be sufficiently protected, and the etching solution can be prevented from invading the metal conductive layer 2 from the passivation layer 3 material of the groove.

In one embodiment, the barrier layer 5 has a thickness of 0.5 to 4 microns. This ensures the protective ability of the barrier layer 5 and prevents the etching solution from penetrating the barrier layer 5 and invading the metal conductive layer 2.

In one embodiment, the display panel further includes a light emitting structure layer 6, the light emitting structure layer 6 includes an anode layer 61, a cathode layer 62 and a light emitting layer 63, the light emitting layer 63 is located between the anode layer 61 and the cathode layer 62, and a portion of the anode layer 61 forms the metal protection layer 4. The material of the anode layer 61 may be IZO or APC alloy.

In one embodiment, the metal conductive layer 2 further includes a first metal layer 21 and a second metal layer 22, a dielectric layer 7 is formed between the first metal layer 21 and the second metal layer 22, the first metal layer 21 is located on the substrate 1, the dielectric layer 7 covers the first metal layer 21, the second metal layer 22 is located on the dielectric layer 7, and a portion of the second metal layer 22 is located at the bottom of the recess 31. The first metal layer 21 includes a gate G and a gate trace, and the second metal layer 22 includes source, drain and bonding region 102 metals.

In one embodiment, the display panel further includes an active layer 81, an insulating layer 82, a light shielding layer 83 and a buffer layer 9, the light shielding layer 83 is located on the display region 101 of the substrate 1, the buffer layer 9 covers the light shielding layer 83 and the substrate 1, the active layer 81 is located on the buffer layer 9, the insulating layer 82 is located on the active layer 81, the first metal layer 21 is located on the insulating layer 82, and the dielectric layer 7 covers the active layer 81, the insulating layer 82, the light shielding layer 83 and the buffer layer 9. The insulating layer 82 is specifically a gate insulating layer 82, and forms an insulating protection between the gate and the active layer 81. The light shielding layer 83 can shield the active layer 81 from light and prevent light from irradiating the active layer 81 to affect electrical properties.

In one embodiment, as shown in fig. 7, the display panel further includes an auxiliary cathode a and an undercut structure B. The undercut structure B is a space formed by a groove of the auxiliary cathode a and the passivation layer 3, the cathode layer 62 can extend into the space through the cathode layer trace C and contact with the auxiliary cathode a, and the edge of the anode layer 61 contacts with the undercut structure B and the cathode layer trace C. The voltage drop phenomenon of the cathode layer 62 can be improved by the auxiliary cathode a and the undercut structure B.

In an embodiment, a via hole 71 is further formed in the dielectric layer 7, a metal trace is disposed in the via hole 71, and the source and drain (S/D) are electrically connected to the light shielding layer 83 through the metal trace. This allows charge transfer between the source/drain (S/D) and the light-shielding layer 83, thereby compensating for Vth (switching threshold).

In one embodiment, the passivation layer 3 is further covered with a planarization layer PLN, and the planarization layer PLN may be SiN (silicon nitride). The light emitting structure layer 6 is formed on the planarization layer PLN.

The display panel of the embodiment of the present invention comprises a substrate 1, and a metal conductive layer 2, a passivation layer 3, a metal protection layer 4 and a barrier layer 5 located on the substrate 1; the substrate 1 includes a display area 101 and a binding area 102 located outside the display area 101; the passivation layer 3 on the bonding region 102 is formed with a groove region 31; the metal protection layer 4 is at least partially positioned in the groove area 31 and covers the metal conducting layer 2 positioned at the bottom of the groove area 31; the barrier layer 5 is located at the side of the metal protection layer 4.

Specifically, the groove region 31 includes a first groove 311 and a second groove 312 located outside the first groove 311, the metal protection layer 4 is covered and at least partially located in the first groove 311, and the barrier layer 5 is at least partially located in the second groove 312. A portion of the metal protection layer 4 is located in the second recess 312 and contacts the barrier layer 5. The depth of the second groove 312 is greater than or equal to the depth of the first groove 311. The sectional shape of the second groove 312 in the light exit direction includes at least one of a rectangle and a trapezoid. The width L of the portion of the metal conductive layer 2 covered by the recessed region 31 is 3 to 5 micrometers. Specifically, the width L may be 4.25 micrometers. The barrier layer 5 has a thickness of 0.5 to 4 microns.

The display panel further comprises a light emitting structure layer 6, the light emitting structure layer 6 comprises an anode layer 61, a cathode layer 62 and a light emitting layer 63, the light emitting layer 63 is positioned between the anode layer 61 and the cathode layer 62, and a part of the anode layer 61 forms the metal protection layer 4. The material of the anode layer 61 may be IZO or APC alloy.

The metal conductive layer 2 further includes a first metal layer 21 and a second metal layer 22, a dielectric layer 7 is formed between the first metal layer 21 and the second metal layer 22, the first metal layer 21 is located on the substrate 1, the dielectric layer 7 covers the first metal layer 21, the second metal layer 22 is located on the dielectric layer 7, and a portion of the second metal layer 22 is located at the bottom of the groove region 31. The first metal layer 21 includes a gate and a gate trace, and the second metal layer 22 includes source, drain and bonding region 102 metals.

The display panel further comprises an active layer 81, an insulating layer 82, a light shielding layer 83 and a buffer layer 9, the light shielding layer 83 is located on the display region 101 of the substrate 1, the buffer layer 9 covers the light shielding layer 83 and the substrate 1, the active layer 81 is located on the buffer layer 9, the insulating layer 82 is located on the active layer 81, the first metal layer 21 is located on the insulating layer 82, and the dielectric layer 7 covers the active layer 81, the insulating layer 82, the light shielding layer 83 and the buffer layer 9.

In the display panel of this embodiment, the metal protection layer 4 can prevent the second metal layer 22 from being corroded by the etching solution, and meanwhile, the barrier layer 5 can prevent the etching solution from invading from the side to corrode the metal protection layer 4 and the second metal layer 22. Therefore, the stability of the second metal layer 22 on the bonding region 102 can be improved, a mask is not required to be added, the production cost is reduced, and the product yield is improved.

The embodiment of the utility model provides an in the embodiment display panel's manufacturing method as follows step:

as shown in fig. 8, on a glass substrate (arrayglass)The method comprises the steps of depositing a metal layer Mo/Cu and a light shielding layer (LS layer) by utilizing physical vapor sputtering, depositing a diffusion barrier layer (materials with work functions similar to those of Cu such as MoTi, mo and Ta) and an etching barrier layer (metal oxides such as ITO and IGZO) on the metal layer by utilizing sputtering, and forming a light shielding layer pattern through a photoetching process. H can be used for the first metal layer and the diffusion barrier layer ₂ O ₂ The etching agent is a liquid chemical, and the etching barrier layer is an oxalic acid liquid chemical.

As shown in fig. 9, in the previous step, a Buffer layer (Buffer layer) is deposited by a chemical vapor deposition method, an active layer is deposited by a physical vapor sputtering method, a metal oxide such as ITO/IGZO is formed into an IGZO pattern by a photolithography process, and an oxalic acid-based chemical solution is used as an etchant.

As shown in fig. 10, in the foregoing steps, a gate insulating layer (GI layer) and a first metal layer are deposited by a chemical vapor deposition method, a gate and a gate insulating layer pattern are formed by a photolithography process, and after a gate photoresist is stripped, an IGZO is converted into a conductor by a plasma etching process.

As shown in fig. 11, on the basis of the previous step, a dielectric layer (ILD layer) is deposited by a chemical vapor deposition method, the ILD layer and the Buffer layer are respectively subjected to hole digging through two photolithography processes, dry etching treatment is performed by using oxidizing gases such as F (fluorine) series, and when the dry etching barrier layer is IGZO, a dry etching plasma is simultaneously used for conducting treatment on the etching barrier layer, so that charge transfer between subsequent source/drain electrodes (S/D electrodes) and the LS layer is ensured, and Vth (switching threshold) is compensated.

As shown in fig. 12, on the basis of the previous step, a metal layer M2 such as MoTi/Cu/MoTi is deposited by a physical vapor deposition method to serve as a second metal layer, a source/drain (S/D) is formed by a photolithography process, and H is used ₂ O ₂ The liquid chemical is used as an etchant to etch and produce source/drain electrodes.

As shown in fig. 13, on the basis of the previous step, a passivation layer (PV layer) is deposited by a chemical vapor method.

As shown in fig. 14, on the basis of the previous step, a patterning process is performed to complete the fabrication of the planarization layer PLN, and the passivation layer PV is opened to form a recess region, and a PLN process is performed;

as shown in fig. 15, on the basis of the previous step, a wet etching process is performed to complete the patterning of the anode (IZO/APC/IZO) by using a hydrophilic Photoresist (PR), and simultaneously, a metal protection layer is formed in the groove region; the photoresist PR is left without removing the photoresist.

As shown in fig. 16, a barrier layer (bank) process is performed, the photoresist is exposed through a bank patterning process, and the bank is patterned through development.

As shown in fig. 17, on the basis of the previous steps, IJP printing of the HIL (hole injection layer), the HTL (hole transport layer), and the (EML) R/G/B organic light emitting layer was performed; and performing ETL (electron transport layer), EIL (electron injection layer) and cathode evaporation processes.

As shown in fig. 18 and 7, on the basis of the previous steps, the Cathode is sputtered by a sputter (sputtering process) so that the anode edge and the undercut region are in contact with the Cathode, and the Cathode and the auxiliary Cathode are connected.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A display panel is characterized by comprising a substrate, and a metal conducting layer, a passivation layer, a metal protection layer and a blocking layer which are positioned on the substrate;

a groove region is formed on the passivation layer on the binding region;

the barrier layer is located at a side of the metal protection layer.

2. The display panel of claim 1, wherein the groove region comprises a first groove and a second groove located outside the first groove, wherein the metal protection layer covers at least a portion located in the first groove, and wherein the barrier layer is at least partially located in the second groove.

3. The display panel according to claim 2, wherein a portion of the metal protection layer is located in the second groove and is in contact with the barrier layer.

4. The display panel according to claim 2, wherein a depth of the second groove is greater than or equal to a depth of the first groove.

5. The display panel according to claim 2, wherein a cross-sectional shape of the second groove in the light exit direction includes at least one of a rectangle and a trapezoid.

6. The display panel of claim 1, wherein the width of the portion of the metal conductive layer covered by the groove region is 3 to 5 micrometers.

7. The display panel according to claim 1, wherein the barrier layer has a thickness of 0.5 to 4 micrometers.

8. The display panel according to claim 1, further comprising a light emitting structure layer including an anode layer, a cathode layer, and a light emitting layer, the light emitting layer being located between the anode layer and the cathode layer, a portion of the anode layer forming the metal protection layer.

9. The display panel according to any one of claims 1 to 8, wherein the metal conductive layer further comprises a first metal layer and a second metal layer, a dielectric layer is formed between the first metal layer and the second metal layer, the first metal layer is located on the substrate, the dielectric layer covers the first metal layer, the second metal layer is located on the dielectric layer, and a portion of the second metal layer is located at the bottom of the groove region.

10. The display panel according to claim 9, further comprising an active layer, an insulating layer, a light-shielding layer, and a buffer layer, wherein the light-shielding layer is located on the display region of the substrate, the buffer layer covers the light-shielding layer and the substrate, the active layer is located on the buffer layer, the insulating layer is located on the active layer, the first metal layer is located on the insulating layer, and the dielectric layer covers the active layer, the insulating layer, the light-shielding layer, and the buffer layer.