JP2007157916A - Tft board, and manufacturing method therefor - Google Patents

Tft board, and manufacturing method therefor Download PDF

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Publication number
JP2007157916A
JP2007157916A JP2005349374A JP2005349374A JP2007157916A JP 2007157916 A JP2007157916 A JP 2007157916A JP 2005349374 A JP2005349374 A JP 2005349374A JP 2005349374 A JP2005349374 A JP 2005349374A JP 2007157916 A JP2007157916 A JP 2007157916A
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gate
wiring
oxide layer
electrode
etch stopper
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Kazuyoshi Inoue
Kiminori Yano
一吉 井上
公規 矢野
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Idemitsu Kosan Co Ltd
出光興産株式会社
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Abstract

An object of the present invention is to propose a TFT substrate and a method for manufacturing a TFT substrate that can significantly reduce the manufacturing cost and improve the manufacturing yield by reducing the number of manufacturing steps.
A channel that includes a glass substrate, a gate electrode and a gate wiring, a gate insulating film, an n-type oxide semiconductor layer, and an oxide conductor layer, and that protects a channel portion. A part etching stopper 53 and a source wiring 65, a drain wiring 66, a source electrode 63, a drain electrode 64, and a pixel electrode 67 having an oxide conductor layer 60 are provided.
[Selection] Figure 6

Description

  The present invention relates to a TFT substrate and a TFT substrate manufacturing method, and in particular, an oxide semiconductor as an active layer of a TFT (thin film transistor), a channel portion etch stopper for protecting a channel portion, and the same channel portion etch stopper. A gate wiring etch stopper formed from a protective layer of the second, and the second oxide layer (oxide conductor layer) serves as a source wiring, a drain wiring, a source electrode, a drain electrode, and a pixel electrode. The present invention relates to a TFT substrate and a TFT substrate manufacturing method capable of improving the quality by reliably protecting the parts, and reducing the manufacturing process to reduce the manufacturing cost.

  LCDs (liquid crystal display devices) and organic EL display devices are widely used for reasons such as display performance and energy saving. In particular, it has become almost mainstream as a display device for mobile phones, PDAs (personal personal digital assistants), personal computers, laptop computers, televisions, and the like. In these display devices, a TFT substrate is generally used.

  For example, a liquid crystal display device is configured to fill a display material such as liquid crystal between a TFT substrate and a counter substrate, and to selectively apply a voltage to the display material for each pixel. Here, the TFT substrate refers to a substrate on which a TFT (thin film transistor) made of a semiconductor thin film (also referred to as a semiconductor film) is disposed. In general, a TFT substrate is also called a “TFT array substrate” because TFTs are arranged in an array.

  Note that in a TFT substrate used for a liquid crystal display device or the like, a set of TFTs and one pixel of a screen of the liquid crystal display device (this is called one unit) is arranged vertically and horizontally on a glass substrate. In the TFT substrate, gate wirings are arranged at regular intervals in the vertical direction on a glass substrate, and source wirings or drain wirings are arranged at regular intervals in the horizontal direction. Further, a gate electrode, a source electrode, and a drain electrode are provided in each of the units constituting each pixel.

<Conventional manufacturing method of TFT substrate>
As a manufacturing method of this TFT substrate, there are generally known a five-mask process using five masks, a four-mask process in which the number of masks is reduced to four using a halftone exposure technique, and the like. .
By the way, since such a TFT substrate manufacturing method uses five or four masks, the manufacturing process tends to have a large number of steps. For example, even in the case of a four-mask process, it is known that a process exceeding 35 steps (processes) and in the case of a five-mask process requires more than 40 steps (processes). If the number of processes increases in this way, the manufacturing yield may be reduced. In addition, if the number of processes is large, the process tends to be complicated, and the manufacturing cost may increase.

(Manufacturing method using five masks)
11A and 11B are schematic views for explaining a conventional TFT substrate manufacturing method. FIG. 11A is a cross-sectional view in which a gate electrode is formed, and FIG. 11B is a cross-sectional view in which an etch stopper is formed. (C) is a sectional view in which a source electrode and a drain electrode are formed, (d) is a sectional view in which an interlayer insulating film is formed, and (e) is a sectional view in which a transparent electrode is formed.
In FIG. 2A, a gate electrode 212 is formed on a glass substrate 210 using a first mask (not shown). That is, first, a metal (for example, Al) is deposited on the glass substrate 210 by sputtering, and after that, a resist is formed by photolithography using a first mask and etched into a desired shape. An electrode 212 is formed and the resist is ashed.

  Next, as shown in FIG. 2B, a gate insulating film 213 to be a SiN film (silicon nitride film) and an α-Si: H (i) film 214 are formed on the glass substrate 210 and the gate electrode 212. Laminate in order. Subsequently, a SiN film (silicon nitride film) serving as a channel protective layer is deposited, and a resist is formed by photolithography using a second mask (not shown), and the SiN film is formed using CHF gas. Dry etching is performed into a desired shape, an etch stopper 215 is formed, and the resist is ashed.

Next, as shown in FIG. 3C, an α-Si: H (n) film 216 is deposited on the α-Si: H (i) film 214 and the etch stopper 215, and further, Cr is formed thereon. A / Al bilayer film is deposited by vacuum evaporation or sputtering. Subsequently, a resist is formed by photolithography using a third mask (not shown), and the Cr / Al bilayer film is etched to form a source electrode 217a and a drain electrode 217b having desired shapes. This etching is performed by photoetching using H 3 PO 4 —CH 3 COOH—HNO 3 for Al, and by photoetching using an aqueous solution of ceric ammonium nitrate for Cr. Done. Further, the α-Si: H film (216 and 214) is etched by using both dry etching using CHF gas and wet etching using an aqueous hydrazine solution (NH 2 NH 2 .H 2 0). The α-Si: H (n) film 216 and the α-Si: H (i) film 214 having the following shapes are formed, and the resist is ashed.

  Next, as shown in FIG. 4D, before forming the transparent electrode 219, an interlayer insulating film 218 is deposited on the gate insulating film 213, the etch stopper 215, the source electrode 217a and the drain electrode 217b. Subsequently, a resist is formed by photolithography using a fourth mask (not shown), the interlayer insulating film 218 is etched, and the source electrode 217a is electrically connected to the transparent electrode 219 described below. Through-holes 218a are formed and the resist is ashed.

Next, as shown in FIG. 4E, the amorphous transparent conductive material mainly composed of indium oxide and zinc oxide is formed on the interlayer insulating film 218 in the region where the pattern of the source electrode 217a and the drain electrode 217b is formed. A film is deposited by sputtering. Subsequently, a resist is formed by photolithography using a fifth mask (not shown), photo-etching is performed using an amorphous transparent conductive film as an etchant with an aqueous solution of 4% by weight of oxalic acid, and the source electrode 217a. And patterning into a shape that is electrically connected to the resist, and ashing the resist. Thereby, the transparent electrode 219 is formed.
Thus, according to the manufacturing method of the TFT substrate according to this conventional example, five masks are required.

(Manufacturing method using three masks)
As a technique for improving the conventional technique, various techniques for manufacturing a TFT substrate by a method in which the number of masks is reduced (for example, from 5 to 3) and the manufacturing process is further reduced have been proposed. For example, Patent Documents 1 to 7 listed below describe a method for manufacturing a TFT substrate using three masks.
Japanese Patent Laid-Open No. 2004-317685 JP 2004-319655 A JP-A-2005-017669 JP 2005-019664 A JP 2005-049667 A JP 2005-106881 A JP 2005-108912 A

However, the method of manufacturing a TFT substrate using the three masks described in Patent Documents 1 to 7 is a very complicated manufacturing process such that an anodizing step for a gate insulating film is added, and is practical. There is a problem that it is a technology that is difficult to provide.
Further, in an actual production line, improvement of quality, that is, yield is extremely important, and there has been a demand for a practical technique that can improve quality and productivity.

  The present invention has been made in view of the above problems, and by reducing the number of manufacturing steps, a manufacturing cost can be significantly reduced and a manufacturing yield can be improved. The purpose is to propose a manufacturing method.

In order to achieve the above object, a TFT substrate of the present invention includes a substrate, a gate electrode and a gate wiring formed on the substrate, a gate insulating film formed on the gate electrode and the gate wiring, and at least the gate insulating film. A TFT substrate comprising a first oxide layer formed on a gate insulating film on a gate electrode and a second oxide layer formed on the first oxide layer and separated by a channel portion. A channel portion etch stopper is formed on the first oxide layer and protects the channel portion.
In this case, the channel portion is reliably protected by the channel portion etch stopper, so that the quality can be improved. Further, by using an oxide semiconductor as the active layer of the TFT, it is stable even when a current is passed, and is useful for an organic electroluminescence device that is operated by current control.

In the TFT substrate of the present invention, the first oxide layer is an n-type oxide semiconductor layer, and the second oxide layer is an oxide conductor layer.
In this way, the channel part, the source electrode, and the drain electrode can be easily formed.

In the TFT substrate of the present invention, the second oxide layer also serves as a source wiring, a drain wiring, a source electrode, a drain electrode, and a pixel electrode.
If it does in this way, the number of masks to be used can be reduced, the production process can be reduced, the production efficiency can be improved, and the production cost can be reduced.
“The second oxide layer also serves as a source wiring, a drain wiring, a source electrode, a drain electrode, and a pixel electrode” means that the molded second oxide layer is a source wiring, a drain wiring, and a source electrode. , Having a function as a drain electrode and a pixel electrode.

In the TFT substrate of the present invention, the pixel electrode is composed of a laminated film of the first oxide layer and the second oxide layer.
In this way, since the laminated film can be made transparent, malfunction due to light can be prevented.

The TFT substrate of the present invention has a configuration in which the first oxide layer is formed at least on the substrate side of the second oxide layer.
In this way, the second oxide layer and the first oxide layer can be made transparent, so that malfunction due to light can be prevented.

The TFT substrate of the present invention includes a gate wiring etch stopper formed of the same protective layer as the channel portion etch stopper, and the gate wiring etch stopper has an opening.
In this case, the gate wiring can be protected by the gate wiring etch stopper formed from the same protective layer as the channel portion etch stopper. In addition, the gate insulating film stacked on the gate wiring pad can be removed by the opening of the gate wiring etch stopper, which makes it possible to manufacture with three masks and reduce the manufacturing process. Cost reduction.

In the TFT substrate of the present invention, the gate insulating film is etched using the resist for forming the second oxide layer and the first oxide layer and the gate wiring etch stopper. It is as.
In this case, when the gate wiring pad is formed, an unnecessary gate insulating film can be removed, so that the amount of transmitted light can be increased without increasing the manufacturing process, and the quality can be improved.

The TFT substrate of the present invention has a configuration in which an auxiliary conductive layer is formed on at least one of the source wiring, drain wiring, source electrode, drain electrode, and pixel electrode.
If it does in this way, the electrical resistance of each wiring and an electrode can be reduced, reliability can be improved, and the fall of energy efficiency can be controlled.

In the TFT substrate of the present invention, the gate insulating film is etched using the auxiliary conductive layer, the crystallized second oxide layer, and an etch stopper for gate wiring.
In this case, when the gate wiring pad is formed, an unnecessary gate insulating film can be removed, so that the amount of transmitted light can be increased without increasing the manufacturing process, and the quality can be improved.

Further, the TFT substrate of the present invention has a configuration in which an insulating film is provided on at least the source wiring, drain wiring, source electrode, and drain electrode.
If it does in this way, an organic electroluminescent apparatus can be obtained easily by providing an organic electroluminescent material, an electrode, and a protective film in a TFT substrate.

In the TFT substrate of the present invention, the energy gap between the first oxide layer and the second oxide layer is 3.0 eV or more.
In this way, by setting the energy gap to 3.0 eV or more, malfunction due to light can be prevented. In general, the energy gap may be 3.0 eV or more, preferably 3.2 eV or more, and more preferably 3.4 eV or more. Thus, by increasing the energy gap, malfunction due to light can be prevented more reliably.

In order to achieve the above object, a manufacturing method of a TFT substrate of the present invention includes a step of forming a gate electrode and a gate wiring on a substrate using a first mask, and the substrate, gate electrode and gate. A gate insulating film, a first oxide layer, a protective layer, and a second resist are laminated in this order on the wiring, and a second mask is used to etch the channel portion etch stopper and the gate wiring. Forming an etch stopper; and laminating a second oxide layer and a third resist in this order on the first oxide layer, the channel portion etch stopper, and the gate wiring etch stopper; Using the mask, the step of forming the third resist into a predetermined shape, and using the third resist, the channel portion etch stopper, and the gate wiring etch stopper Etching the second oxide layer and the first oxide layer to form a source wiring, a drain wiring, a source electrode, a drain electrode and a pixel electrode made of the second oxide layer; After the ashing of the third resist, the gate insulating layer is formed by using the gate wiring etch stopper having an opening and the molded second oxide layer while protecting the channel portion with the channel portion etch stopper. And a step of forming a gate wiring pad by etching the film.
As described above, the present invention is also effective as a method for manufacturing a TFT substrate, and the channel portion is reliably protected by the etch stopper, so that the quality can be improved and the number of masks can be reduced. As a result, production efficiency can be improved and manufacturing costs can be reduced. Furthermore, since the gate insulating film stacked on the gate wiring can be removed by the gate wiring etch stopper formed from the same protective layer as the channel portion etching stopper, the manufacturing process can be reduced and the manufacturing cost can be reduced. Cost can be reduced.

In order to achieve the above object, a manufacturing method of a TFT substrate of the present invention includes a step of forming a gate electrode and a gate wiring on a substrate using a first mask, and the substrate, gate electrode and gate. A gate insulating film, a first oxide layer, a protective layer, and a second resist are laminated in this order on the wiring, and a second mask is used to etch the channel portion etch stopper and the gate wiring. A step of forming an etch stopper, and a second oxide layer, an auxiliary conductive layer, and a third resist are laminated in this order on the first oxide layer, the channel portion etch stopper, and the gate wiring etch stopper. A step of forming the third resist into a predetermined shape by halftone exposure;
Etching the auxiliary conductive layer, the second oxide layer, and the first oxide layer using the third resist, the channel portion etch stopper, and the gate wire etch stopper to form a source wiring, a drain wiring, A step of forming a source electrode, a drain electrode and a pixel electrode; a step of re-forming the third resist; a step of changing the etching resistance of the second oxide layer; and on the source wiring and the drain wiring. Etching the auxiliary conductive layer on the pixel electrode using the re-formed third resist on the source electrode and the drain electrode, and forming the auxiliary conductive layer, and the channel portion etch stopper The gate wiring etch stopper and the molded second oxide layer having an opening while protecting the channel portion by Etching the gate insulating film, it is a method and a step of forming a gate wire pad.
If it does in this way, the electrical resistance of each wiring and an electrode can be reduced, reliability can be improved, and the fall of energy efficiency can be controlled.

In the TFT substrate manufacturing method of the present invention, an insulating film and a resist are laminated on the substrate in this order, and the insulating film on the gate wiring pad, the source / drain wiring pad, and the pixel electrode is used using a mask. And an insulating film is formed on at least the source wiring, drain wiring, source electrode and drain electrode.
In this way, an insulating film can be formed on the upper part of the substrate. For example, an organic electroluminescent device can be obtained by providing an organic EL material, an electrode and a protective film on the TFT substrate.
The source / drain wiring pads refer to source wiring pads or drain wiring pads.

  According to the TFT substrate and the TFT substrate manufacturing method of the present invention, the manufacturing cost can be significantly reduced by reducing the number of manufacturing steps, and the manufacturing yield is improved by providing the channel portion etch stopper. Can be made.

[First Embodiment in Manufacturing Method of TFT Substrate]
FIG. 1 is a schematic flowchart for explaining a method of manufacturing a TFT substrate according to the first embodiment of the present invention.
In the figure, first, a gate electrode 21 and a gate wiring 22 are formed on a substrate 10 using a first mask 22 (step S1).
Next, processing using the first mask 22 will be described with reference to the drawings.

(Process using the first mask)
FIG. 2 is a schematic view for explaining a process using a first mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention, and (a) is a cross-sectional view of the glass substrate before the process. (B) is a cross-sectional view with a metal film formed, (c) is a cross-sectional view with a resist applied, and (d) is exposed / developed / etched / resist stripped to form a gate electrode and a gate wiring. A cross-sectional view is shown.
In FIG. 1A, first, a translucent glass substrate 10 is prepared.

Next, as shown in FIG. 4B, a metal film is formed on the glass substrate 10 to form a gate electrode / wiring thin film (gate electrode and gate wiring thin film) 20.
In this embodiment, Al (aluminum) and Mo (molybdenum) are formed on the glass substrate 10 as a metal thin film having a film thickness of about 250 nm and 50 nm, respectively, by using a high-frequency sputtering method in this order. Subsequently, using a sputtering target made of indium oxide-tin oxide-samarium oxide (ITSmO: In203: SnO 2 : Sm 2 O 3 = about 90: 7: 3 wt%), a thin film having a thickness of about 100 nm is formed, A gate electrode / wiring thin film 20 made of Al / Mo / ITSmO is formed.
Mo on Al is used for the purpose of lowering the contact resistance with the oxide thin film. If the contact resistance is low enough not to be concerned, the Mo layer may not be formed. Moreover, Ti (titanium), Ni (nickel), etc. can be used instead of Mo. Further, a metal thin film such as Ag (gold) or Cu (copper) or an alloy thin film can be used as the gate wiring.

  Next, a first resist 21 is applied on the gate electrode / wiring thin film 20 as shown in FIG.

  Next, as shown in FIG. 4D, a resist (not shown) is formed into a predetermined shape by photolithography using the first mask 22. Subsequently, the ITSmO thin film is etched using an oxalic acid aqueous solution, and the metal thin film is etched using a mixed acid of phosphoric acid, acetic acid and nitric acid (generally called PAN) to form a gate having a desired shape. The electrode 23 and the gate wiring 24 are formed (see FIG. 3). The gate electrode 23 and the gate wiring 24 shown in FIG. 2D show the AA cross section and the BB cross section in FIG. Here, ITSmO can be etched using a mixed acid of phosphoric acid, acetic acid, and nitric acid, and may be collectively etched with the metal wiring using the mixed acid.

Further, after the formation of the gate electrode / wiring thin film 20, heat treatment may be performed to lower the resistance of Al and ITSmO may be crystallized. That is, when ITSmO is crystallized, it does not dissolve in an oxalic acid-based etching solution or a mixed acid of phosphoric acid, acetic acid and nitric acid, so that the Al / Mo layer can be protected.
Further, by forming an oxide conductive film such as ITSmO on the surface of the gate wiring 24, when the gate wiring pad 25 is formed, the metal surface used for the gate wiring 24 is not exposed, so that a highly reliable connection is possible. It becomes.

Next, as shown in FIG. 1, a gate insulating film 30, an n-type oxide semiconductor layer 40 as a first oxide layer, a protective layer 50, and a second layer are formed on the glass substrate 10, the gate electrode 23, and the gate wiring 24. These resists 51 are stacked in this order, and a channel portion etch stopper 53 and a gate wiring etch stopper 54 formed of the protective layer 50 are formed using the second mask 52 (step S2).
Next, processing using the second mask 52 will be described with reference to the drawings.

(Process using the second mask)
FIG. 4 is a schematic view for explaining a process using the second mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention, and (a) is a gate insulating film formation / n-type. Oxide semiconductor layer deposition / protection layer deposition / resist coated cross-sectional view, (b) is a cross-section where exposure / development / etching / resist stripping is performed, and an etch stopper for a channel portion and an etch stopper for a gate wiring are formed. The figure is shown.
In FIG. 2A, first, a gate insulating film 30 that is a silicon nitride (SiNx) film is formed on the glass substrate 10, the gate electrode 23, and the gate wiring 24 by a glow discharge CVD (chemical vapor deposition) method. Deposit 300 nm. In the present embodiment, a SiH 4 —NH 3 —N 2 -based mixed gas is used as the discharge gas.

Next, an n-type film having a thickness of about 150 nm is formed on the gate insulating film 30 by high frequency sputtering using an indium oxide-gallium oxide-zinc oxide (InGaZnO 4 ) target under conditions of about 15% oxygen and about 85% argon. The oxide semiconductor layer 40 is formed. The energy gap of this n-type oxide semiconductor layer 40 was about 3.6 eV.

Next, a protective layer 50 that is a silicon nitride (SiNx) film is deposited on the n-type oxide semiconductor layer 40 by a glow discharge CVD method to a thickness of about 350 nm. In the present embodiment, a SiH 4 —NH 3 —N 2 -based mixed gas is used as the discharge gas.
Here, it is important to stack the protective layer 50 thicker than the gate insulating film 30. That is, in the subsequent process, when the gate wiring pad 25 is formed (when the gate insulating film 30 on the gate wiring pad 25 is etched to form the gate wiring pad 25), the protective layer 50 is also formed together with the gate insulating film 30. Etched. Therefore, by depositing the protective layer 50 thicker than the gate insulating film 30, even if the gate insulating film 30 on the gate wiring pad 25 is etched, the protective layer 50 (channel portion etch stopper 53) can be left. The remaining channel portion etch stopper 53 reliably protects the channel portion 41 of the n-type oxide semiconductor layer 40 and improves the quality (yield) of the TFT substrate 1.

  In the present embodiment, a silicon nitride film having substantially the same characteristics as the gate insulating film 30 is stacked as the protective layer 50 (physically) thicker than the gate insulating film 30, but is limited to this configuration. It is not something. For example, even if the gate insulating film 30 on the gate wiring pad 25 is etched by laminating the protective layer 50 having a higher etching resistance than the gate insulating film 30, the protective layer 50 (channel portion etch stopper 53) is formed. Can leave. In such a case, even if the protective layer 50 is thinner than the gate insulating film 30, the remaining channel portion etch stopper 53 reliably protects the channel portion 41 of the n-type oxide semiconductor layer 40, so that the quality of the TFT substrate 1 is improved. Will improve.

Next, a second resist 51 is applied on the protective layer 50, and a resist (not shown) is formed into a predetermined shape by photolithography using a second mask 52 as shown in FIG. Z). Subsequently, the protective layer 50 is etched using CHF (CF 4 , CHF 3 gas, etc.) to form a channel portion etch stopper 53 and a gate wiring etch stopper 54 (see FIG. 5). An etch stopper 53 and a gate wiring pad etch stopper 54 shown in FIG. 4B show a CC cross section and a DD cross section in FIG.

As shown in FIG. 5, the channel portion etch stopper 53 is formed in a substantially rectangular shape covering the gate electrode 23, and protects the channel portion 41 of the n-type oxide semiconductor layer 40.
Further, as shown in FIG. 5, the gate wiring etch stopper 54 is formed in a shape covering the gate wiring 24, and further has an opening 55 for forming the gate wiring pad 25. In this way, the gate insulating film 30 on the gate wiring 24 is protected, and the gate wiring pad 25 can be easily formed by the opening 55.

Next, as shown in FIG. 1, on the n-type oxide semiconductor layer 40, the channel portion etch stopper 53, and the gate wiring etch stopper 54, an oxide conductor layer 60 and a third oxide layer are formed as second oxide layers. The resists 61 are stacked in this order, and the third resist 61 is formed into a predetermined shape using the third mask 62 (step S3).
Next, processing using the third mask 62 will be described with reference to the drawings.

(Process using third mask)
FIG. 6 is a schematic view for explaining a process using a third mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention. FIG. FIG. 4B is a cross-sectional view after resist coating / exposure / development, FIG. 5B is a cross-sectional view after etching of source and drain electrodes and wiring and pixel electrodes, and FIG. FIG.
In FIG. 6A, first, indium oxide-zinc oxide (IZO: In 2 O 3 : ZnO = about 90) is formed on the n-type oxide semiconductor layer 40, the channel portion etch stopper 53, and the gate wiring etch stopper 54. : 10 wt%) Using a target, an oxide conductor layer 60 having a thickness of about 150 nm is formed by high-frequency sputtering under conditions of about 1% oxygen and about 99% argon. The energy gap of the oxide conductor layer 60 was about 3.2 eV.

  Next, a third resist 61 is applied on the oxide conductor layer 60, and the first resist 61 is formed into a predetermined shape by photolithography using a third mask 62 as shown in FIG. A third resist 61 is formed. That is, the third resist 61 is formed into a shape corresponding to the source electrode 63, the drain electrode 64, the source wiring 65, the drain wiring 66, and the pixel electrode 67.

Next, as shown in FIG. 4B, the third resist 61 formed in a predetermined shape is used to form IZO that is the oxide conductor layer 60 and indium oxide-oxide that is the n-type oxide semiconductor layer 40. The gallium-zinc oxide (InGaZnO 4 ) film is collectively etched with an oxalic acid-based etchant to form the desired source electrode 63, drain electrode 64, source wiring 65, drain wiring 66, and pixel electrode 67 (step S4). ). At this time, the channel portion etch stopper 53, the gate wiring etch stopper 54, and the gate insulating film 30 are resistant to an oxalic acid-based etchant and are not etched. That is, the channel portion 41 of the n-type oxide semiconductor layer 40 is protected by the channel portion etch stopper 53. On the other hand, the oxide conductor layer 60 stacked in the opening 55 of the gate wiring etch stopper 54 and the n-type oxide semiconductor layer 40 stacked below the oxide conductor layer 60 are etched. . Here, the gate wiring etch stopper 54 functions as a resist for etching the n-type oxide semiconductor layer 40 below the opening 55.

Next, as shown in FIG. 5C, after the third resist 61 is ashed, the exposed gate insulating film 30 is etched using CHF (CF 4 , CHF 3 gas, etc.). . Thus, the gate insulating film 30 on the gate wiring pad 25 is removed, and the ITSmO film on the gate wiring 24 is exposed to form the gate wiring pad 25 (Step S5). By the etching, the channel portion etch stopper 53 and the gate wiring etch stopper 54 are also etched. However, as described above, the channel portion etch stopper 53 is laminated thicker than the gate insulating film 30, so that the gate wiring When the etching is finished when the gate insulating film 30 on the pad 25 is removed, the channel portion etch stopper 53 remains, and the channel portion etch stopper 53 protects the channel portion 41.

On the TFT substrate 1, a gate electrode 23, a source electrode 63, a drain electrode 64, a gate wiring 24, a source wiring 65, a drain wiring 66, and a pixel electrode 67 are formed (see FIG. 7). The gate electrode 23, the source electrode 63, the drain electrode 64, the source wiring 65, and the pixel electrode 67 shown in FIG. 6C are taken along the line EE in FIG. 7, and the gate wiring 24 and the gate wiring pad 25 are shown in FIG. , FF cross section is shown, and the drain wiring 66 shows a GG cross section.
Although not shown, the gate electrode 24, the gate insulating film 30, the n-type oxide semiconductor layer 40, and the gate wiring etch stopper 54 are formed on the glass substrate 10 at a portion where the gate wiring 24 and the drain wiring 66 intersect. And the oxide conductor layer 60 are laminated in this order, and the oxide conductor layer 60 to be the drain wiring 66 is insulated from the gate wiring 24 by the gate insulating film 30 and the gate wiring etch stopper 54. Has been.

Thus, according to the manufacturing method of the TFT substrate of this embodiment, the channel portion 41 of the n-type oxide semiconductor layer 40 as the active layer is reliably protected by the channel portion etch stopper 53, so that the quality ( (Yield) can be improved. In addition, the TFT substrate 1 can be manufactured using the three masks 22, 52, 62, the manufacturing process can be reduced, the production efficiency can be improved, and the manufacturing cost can be reduced. In particular, the gate insulating film 30 stacked on the gate wiring pad 25 can be removed by the gate wiring etch stopper 54 having the opening 5 formed from the same protective layer 50 as the channel portion etching stopper 53. Therefore, the manufacturing process can be reduced and the manufacturing cost can be reduced.
Furthermore, the use of an oxide semiconductor (n-type oxide semiconductor layer 40) for the active layer of the TFT ensures stability even when a current is passed, and is useful for an organic electroluminescence device that operates by controlling the current. is there. Further, since the first oxide layer is the n-type oxide semiconductor layer 40 and the second oxide layer is the oxide conductor layer 60, the channel portion 41, the source electrode 63, and the drain electrode 64 are easily formed. can do.

[Second Embodiment in Manufacturing Method of TFT Substrate]
FIG. 8 is a schematic flowchart for explaining a method for manufacturing a TFT substrate according to the second embodiment of the present invention.
In the figure, first, a gate electrode 21 and a gate wiring 22 are formed on a substrate 10 using a first mask 22 (step S11). Subsequently, a gate insulating film 30, an n-type oxide semiconductor layer 40 as a first oxide layer, a protective layer 50, and a second resist 51 are formed on the glass substrate 10, the gate electrode 23, and the gate wiring 24 in this order. Using the second mask 52, the channel portion etch stopper 53 and the gate wiring etch stopper 54 formed of the protective layer 50 are formed (step S12).
The process using the first mask 22 in step S11 and the process using the second mask 52 in step S12 are processes using the first mask 22 in step S1 of the first embodiment, respectively. And it is the same as the process using the 2nd mask 52 in step S2.

Next, as shown in FIG. 8, on the n-type oxide semiconductor layer 40, the channel portion etch stopper 53, and the gate wiring etch stopper 54, an oxide conductor layer 60 as a second oxide layer, metal The layer 70 and the third resist 71 are laminated in this order, and the third resist 71 is formed into a predetermined shape using the third halftone mask 72 and the halftone exposure technique (step S13).
Next, processing using the third halftone mask 72 will be described with reference to the drawings.

(Processing using a third halftone mask)
FIG. 9 is a schematic view for explaining a process using a third halftone mask in the method for manufacturing a TFT substrate according to the second embodiment of the present invention. FIG. Film / metal layer deposition / resist application / halftone exposure / development / etching cross-sectional view, (b) shows an etching / resist stripped cross-sectional view for the gate wiring pad.
In FIG. 1A, first, indium oxide-tin oxide-samarium oxide (ITSmO: In 2 O 3 : SnO 2 : on the n-type oxide semiconductor layer 40, the etch stopper 53, and the gate wiring pad etch stopper 54: A high frequency sputtering method using a sputtering target made of Sm 2 O 3 = about 90: 7: 3 wt% and using an indium oxide-zinc oxide (IZO: In 2 O 3 : ZnO = about 90:10 wt%) target. Thus, the oxide conductor layer 60 having a thickness of about 150 nm is formed under the conditions of about 1% oxygen and about 99% argon.

Next, a metal layer (Al layer) 70 serving as an auxiliary conductive layer is formed to a thickness of about 250 nm, and then the third resist 71 is formed in a predetermined shape using a third halftone mask 72 and a halftone exposure technique. (Step S13). The third resist 71 covers the source electrode 63, the drain electrode 64, the source wiring 65, the drain wiring 66, and the pixel electrode 67, and the portion that covers the pixel electrode 67 by the halftone mask portion 721 is thinner than the other portions. It is formed into a shape.
In addition, the metal layer 70 is not limited to Al, For example, you may use metals, such as Mo, Ag, and Cu, and an alloy. Moreover, you may use the laminated film of metal thin films, such as Mo / Al / Mo, Ti / Al / Ti.

Next, using the third resist 71, the channel portion etch stopper 53, and the gate wiring etch stopper 54, the metal layer 70, the oxide conductor layer 60, and the n-type oxide semiconductor layer 40 are subjected to the first step. Etching is performed to form the desired source electrode 63, drain electrode 64, source wiring 65, drain wiring 66, and pixel electrode 67 (step S14). Here, Al in the metal layer 70 is etched by a mixed acid of phosphoric acid, acetic acid, and nitric acid. Further, an oxide conductor layer 60 and an n-type oxide semiconductor made of indium oxide-tin oxide-samarium oxide (ITSmO: In 2 O 3 : SnO 2 : Sm 2 O 3 = about 90: 7: 3 wt%) as a base The indium oxide-gallium oxide-zinc oxide (InGaZnO 4 ) film that is the layer 40 is collectively etched with an oxalic acid-based etchant.

Next, the third resist 71 is reshaped (step S15). That is, the resist on the pixel electrode 67 that is thinly formed by the halftone exposure technique in the third resist 71 is ashed.
Subsequently, the etching resistance of the oxide conductor layer 60 is changed (step S16). That is, the oxide conductor layer 60 is crystallized, and this crystallization makes the oxide conductor layer 60 resistant to an etching solution for etching the interlayer insulating film 80.
In this embodiment, after the third resist 71 is reshaped, the etching resistance of the oxide conductor layer 60 is changed. However, the present invention is not limited to this. For example, the oxide conductor layer After changing the etching resistance of 60, the third resist 71 may be reshaped.

  Next, using the resist 71 on the source electrode 63, the drain electrode 64, the source wiring 65, and the drain wiring 66, which is thickly formed by the halftone exposure technique in the third resist 71, The metal layer 70 is etched with a mixed acid of phosphoric acid, acetic acid and nitric acid (step S17). Thereby, the pixel electrode 67 becomes a transparent pixel electrode.

Next, the third resist 71 is all ashed, and an auxiliary conductive layer made of a metal layer 70 on the source electrode 63, the drain electrode 64, the source wiring 65, and the drain wiring 66, that is, an auxiliary electrode for a source electrode. 631, drain electrode auxiliary electrode 641, source wiring auxiliary wiring 651, and drain wiring auxiliary wiring 661 are formed (step S18).
Although not shown, an oxide thin film such as IZO may be formed on the metal layer 70. As described above, the oxide thin film is formed on the metal layer 70 so that the metal is not exposed on the metal layer 70, thereby preventing the metal thin film or the like from being corroded.

Next, as shown in FIG. 6B, the exposed gate insulating film 30 is etched using CHF (CF 4 , CHF 3 gas, etc.). As a result, the gate insulating film 30 on the gate wiring pad 25 is removed, and the ITSmO film (not shown) on the gate wiring pad 25 is exposed to form the gate wiring pad 25 (step S19). .

Next, as shown in FIG. 8, after the gate wiring pad 25 is formed, an interlayer insulating film 80 and a fourth resist 81 as an upper layer of the glass substrate 10 are laminated in this order, and a fourth mask 82 is used. Then, the interlayer insulating film 80 on the gate wiring pad 25, the drain wiring pad (not shown) connected to the drain wiring 66, and the pixel electrode 67 is etched, and then the fourth resist 81 is ashed. Then, an interlayer insulating film 80 as an upper layer is formed (step S20).
Next, processing using the fourth mask will be described.

(Process using the fourth mask)
FIG. 10 is a schematic view for explaining a process using a fourth mask in the method for manufacturing a TFT substrate according to the second embodiment of the present invention, and FIG. / Exposed / developed cross-sectional view, (b) shows a cross-sectional view after etching / resist peeling.
In FIG. 2A, first, an interlayer insulating film 80, which is a silicon nitride (SiNx) film, is deposited to a thickness of about 200 nm on the TFT substrate 1a on which the gate wiring pad 25 is formed by glow discharge CVD. As the discharge gas, a SiH 4 —NH 3 —N 2 -based mixed gas is used. Subsequently, a fourth resist 81 is applied, and the fourth resist 81 is formed into a predetermined shape using the fourth mask 72 and an exposure technique. The fourth resist 81 is formed in a shape that covers the source electrode 63, the drain electrode 64, the source wiring 65, the drain wiring 66, and the gate wiring etch stopper 54.

Next, as shown in FIG. 4B, the gate wiring pad 25, the source wiring pad (not shown), and the interlayer insulating film 80 on the pixel electrode 67 are formed using CHF (CF 4 , CHF 3 gas, etc.). Etch. Thus, an interlayer insulating film 80 is formed as an insulating film on the source electrode 63, the drain electrode 64, the source wiring 65, and the drain wiring 66.

  Thus, according to the manufacturing method of the TFT substrate of the present embodiment, the electrical resistance of each wiring and electrode can be reduced by the auxiliary electrode and auxiliary wiring made of the metal layer 70, and the reliability can be improved. In addition, it is possible to suppress a decrease in energy efficiency. In addition, the TFT substrate 1a can be manufactured using the four masks 22, 52, 72, and 82, the manufacturing process can be reduced, the production efficiency can be improved, and the manufacturing cost can be reduced. it can. Further, by forming the interlayer insulating film 80 on the glass substrate 10 and providing, for example, an organic EL material, an electrode, and a protective film on the TFT substrate 1a, an organic electroluminescent device can be easily obtained.

[First embodiment of TFT substrate]
The present invention is also effective as the invention of the TFT substrate 1.
As shown in FIGS. 6C and 7, the TFT substrate 1 according to the first embodiment includes a substrate 10, a gate electrode 23 and a gate wiring 24 formed on the substrate 10, a gate electrode 23 and a gate. A gate insulating film 30 formed on the wiring 24, an n-type oxide semiconductor layer 40 formed on at least the gate insulating film 30 on the gate electrode 23, and a channel portion 41 on the n-type oxide semiconductor layer 40. An oxide conductor layer 60 formed separately is provided. That is, the n-type oxide semiconductor layer 40 is provided as the first oxide layer, and the oxide conductor layer 60 is provided as the second oxide layer. In this way, the channel portion 41 and the source electrode 63 are provided. In addition, the drain electrode 64 can be easily formed.

The TFT substrate 1 includes a channel portion etch stopper 53 that is formed on the n-type oxide semiconductor layer 40 and protects the channel portion 41. In this way, the channel portion 41 is reliably protected by the channel portion etch stopper 53, and the quality (yield) is improved. Further, by using an oxide semiconductor as the active layer of the TFT, it is stable even when a current is passed, and is useful for an organic electroluminescence device that is operated by current control.
Further, in the TFT substrate 1, the oxide conductor layer 60 also serves as the source wiring 65, the drain wiring 66, the source electrode 63, the drain electrode 64, and the pixel electrode 67. That is, since the three masks 22, 52, 62 are manufactured by the manufacturing method of the first embodiment described above, the manufacturing process can be reduced, the production efficiency can be improved, and the manufacturing cost can be reduced.

In the TFT substrate 1, the pixel electrode 67 is formed of a laminated film of the n-type oxide semiconductor layer 40 and the oxide conductor layer 60. In this way, since the laminated film can be made transparent, malfunction due to light can be prevented.
Further, in the TFT substrate 1, an n-type oxide semiconductor layer 40 is formed at least under the oxide conductor layer 60, and the oxide conductor layer 60 and the n-type oxide semiconductor layer 40 are transparent. Therefore, malfunction due to light can be prevented more reliably.
Further, the energy gap between the n-type oxide semiconductor layer 40 and the oxide conductor layer 60 is set to 3.0 eV or more, and the malfunction due to light can be prevented by setting the energy gap to 3.0 eV or more.

  Further, the TFT substrate 1 includes a gate wiring etch stopper 54 formed of the same protective layer 50 as the channel portion etch stopper 53, and the gate wiring etch stopper 54 forms the gate wiring pad 25. An opening 55 is provided. In this case, the gate wiring 24 can be protected by the gate wiring etch stopper 54 formed from the same protective layer 50 as the channel portion etch stopper 53. Further, since the gate insulating film 30 stacked on the gate wiring pad 25 can be removed by the opening 55 of the gate wiring etch stopper 54, the manufacturing process can be reduced and the manufacturing cost can be reduced. .

  In addition, the TFT substrate 1 is etched using the third resist 61 and the gate wiring etch stopper 54 for forming the oxide conductor layer 60 and the n-type oxide semiconductor layer 40 in the gate insulating film 30. The In this case, when the gate wiring pad 25 is formed, the unnecessary gate insulating film 30 can be removed, so that the amount of transmitted light can be increased without increasing the manufacturing process, and the quality can be improved.

  Thus, the TFT substrate 1 of this embodiment can improve the quality (yield) because the channel portion 41 is reliably protected by the channel portion etch stopper 53. Moreover, since it manufactures with the three masks 22,53,62 by the manufacturing method of 1st embodiment, a manufacturing process is reduced, production efficiency improves, and it can aim at the cost reduction of manufacturing cost.

[Second Embodiment of TFT Substrate]
The present invention is also effective as an invention of the TFT substrate 1a.
Compared with the TFT substrate 1, the TFT substrate 1 a according to the second embodiment has a metal on the source electrode 63, the drain electrode 64, the source wiring 65, and the drain wiring 66 as shown in FIG. The auxiliary conductive layer composed of the layer 70, that is, the source electrode auxiliary electrode 631, the drain electrode auxiliary electrode 641, the source wiring auxiliary wiring 651, and the drain wiring auxiliary wiring 661 is formed. If it does in this way, the electrical resistance of each wiring and an electrode can be reduced, reliability can be improved, and the fall of energy efficiency can be controlled.
In this embodiment, the auxiliary conductive layer is formed on the source electrode 63, the drain electrode 64, the source wiring 65, and the drain wiring 66. However, the present invention is not limited to this configuration. For example, an auxiliary conductive layer may be formed on at least one of the source electrode 63, the drain electrode 64, the source wiring 65, the drain wiring 66, and the pixel electrode 67.

  The TFT substrate 1a is manufactured by the manufacturing method of the second embodiment described above, and the gate insulating film 30 includes the source electrode auxiliary electrode 631, the drain electrode auxiliary electrode 641, the source wiring auxiliary wiring 651, and the drain wiring use. Etching is performed using the auxiliary wiring 661, the crystallized oxide conductor layer 60, and the gate wiring etch stopper 54. In this case, when the gate wiring pad 25 is formed, the unnecessary gate insulating film 30 can be removed, so that the amount of transmitted light can be increased without increasing the manufacturing process, and the quality can be improved.

Further, the TFT substrate 1 a includes an interlayer insulating film 80 as an insulating film on the source electrode 63, the drain electrode 64, the source wiring 65 and the drain wiring 66. If it does in this way, an organic electroluminescent apparatus can be obtained easily by providing organic EL material, an electrode, and a protective film in TFT substrate 1a.
Further, since the TFT substrate 1a is manufactured with the four masks 22, 52, 72, and 82 by the manufacturing method of the second embodiment described above, the manufacturing process is reduced, the production efficiency is improved, and the manufacturing cost is reduced. You can go down.

  Thus, the TFT substrate 1a of the present embodiment can reduce the electrical resistance of each wiring and electrode, can improve the reliability, and can suppress the decrease in energy efficiency. The TFT substrate 1a includes an interlayer insulating film 80 on the glass substrate 10. For example, by providing an organic EL material, an electrode, and a protective film on the TFT substrate 1a, the organic electroluminescence device can be easily formed. Obtainable.

The TFT substrate and the method for manufacturing the TFT substrate according to the present invention have been described with reference to the preferred embodiments. However, the TFT substrate and the method for manufacturing the TFT substrate according to the present invention are not limited to the above-described embodiments. Needless to say, various modifications can be made within the scope of the present invention.
For example, the metal layer 70 or the interlayer insulating film 80 of the TFT substrate 1a may be formed on the TFT substrate 1 of the first embodiment.

  The TFT substrate and the TFT substrate manufacturing method of the present invention are not limited to the TFT substrate and TFT substrate manufacturing method used for LCD (Liquid Crystal Display) and organic EL display devices. For example, LCD (Liquid Crystal Display) The present invention can also be applied to a display device other than a device) or an organic EL display device, or a TFT substrate used for other purposes and a manufacturing method of the TFT substrate.

The schematic flowchart figure for demonstrating the manufacturing method of the TFT substrate concerning 1st embodiment of this invention is shown. It is the schematic for demonstrating the process using the 1st mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is sectional drawing of the glass substrate before a process, (b) ) Is a cross-sectional view formed with a metal film, (c) is a cross-sectional view with a resist applied, and (d) is a cross-sectional view with a gate electrode and a gate wiring formed by exposure / development / etching / resist peeling. ing. In the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, the schematic plan view of the principal part of the glass substrate in which the gate electrode and gate wiring were formed is shown. It is the schematic for demonstrating the process using the 2nd mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is gate insulating film film-forming / n-type oxide semiconductor layer Film forming / protective layer forming / resist coated cross-sectional view, (b) shows a cross-sectional view with exposure / development / etching / resist stripping and channel portion etch stopper and gate wiring etch stopper formed. Yes. In the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, the schematic plan view of the principal part of the glass substrate in which the etch stopper and the etch stopper for gate wiring pads were formed is shown. It is the schematic for demonstrating the process using the 3rd mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is oxide conductor layer film-forming / resist application / exposure. / Developed cross-sectional view, (b) is a cross-sectional view after etching of source and drain electrodes and wiring and pixel electrodes, and (c) is a cross-sectional view after etching / resist peeling for gate wiring pads. Is shown. In the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, the schematic plan view of the principal part of the TFT substrate in which the gate wiring pad was formed is shown. The schematic flowchart figure for demonstrating the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention is shown. It is the schematic for demonstrating the process using the 3rd halftone mask of the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention, (a) is oxide conductor layer film formation / metal layer A cross-sectional view after film formation / resist application / halftone exposure / development / etching is shown, and (b) shows a cross-sectional view after etching / resist peeling for a gate wiring pad. It is the schematic for demonstrating the process using the 4th mask of the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention, (a) is interlayer insulation film formation / resist application / exposure / development (B) shows a cross-sectional view after etching / resist peeling. It is the schematic for demonstrating the manufacturing method of the TFT substrate concerning a prior art example, (a) is sectional drawing in which the gate electrode was formed, (b) is sectional drawing in which the etch stopper was shape | molded, (c). Is a cross-sectional view in which a source electrode and a drain electrode are formed, (d) is a cross-sectional view in which an interlayer insulating film is formed, and (e) is a cross-sectional view in which a transparent electrode is formed.

Explanation of symbols

1, 1a TFT substrate 10 Glass substrate 20 Gate electrode / wiring thin film 21 First resist 22 First mask 23 Gate electrode 24 Gate wiring 25 Gate wiring pad 30 Gate insulating film 40 n-type oxide semiconductor layer 41 Channel section 50 Protective layer 51 Second resist 52 Second mask 53 Channel portion etch stopper 54 Gate wiring etch stopper 55 Opening 60 Oxide conductor layer 61 Third resist 62 Third mask 63 Source electrode 64 Drain electrode 65 Source wiring 66 Drain wiring 67 Pixel electrode 70 Metal layer 71 Third resist 72 Third halftone mask 80 Interlayer insulating film 81 Fourth resist 82 Fourth mask 210 Glass substrate 212 Gate electrode 213 Gate insulating film 214 α− Si: H (i) film 215 Etch stopper 21 6 α-Si: H (n) film 217a Source electrode 217b Drain electrode 218 Interlayer insulating film 218a Through hole 219 Transparent electrode 631 Source electrode auxiliary electrode 641 Drain electrode auxiliary electrode 651 Source wiring auxiliary wiring 661 Drain wiring auxiliary wiring

Claims (14)

  1. A substrate, a gate electrode and a gate wiring formed on the substrate, a gate insulating film formed on the gate electrode and the gate wiring, and a first formed at least on the gate insulating film on the gate electrode A TFT substrate comprising an oxide layer and a second oxide layer formed on the first oxide layer and separated by a channel portion,
    A TFT substrate comprising a channel portion etch stopper formed on the first oxide layer and protecting the channel portion.
  2.   The TFT substrate according to claim 1, wherein the first oxide layer is an n-type oxide semiconductor layer, and the second oxide layer is an oxide conductor layer.
  3.   The TFT substrate according to claim 1, wherein the second oxide layer also serves as a source wiring, a drain wiring, a source electrode, a drain electrode, and a pixel electrode.
  4.   The TFT substrate according to any one of claims 1 to 3, wherein the pixel electrode is formed of a laminated film of the first oxide layer and the second oxide layer.
  5.   The TFT substrate according to any one of claims 1 to 4, wherein the first oxide layer is formed at least on the substrate side of the second oxide layer.
  6.   The gate wiring etch stopper is formed of the same protective layer as the channel portion etch stopper, and the gate wiring etch stopper has an opening. TFT substrate according to item.
  7.   The gate insulating film is etched using a resist for forming the second oxide layer and the first oxide layer and the gate wiring etch stopper. TFT substrate.
  8.   The TFT substrate according to claim 1, wherein an auxiliary conductive layer is formed on at least one of the source wiring, drain wiring, source electrode, drain electrode, and pixel electrode.
  9.   9. The TFT substrate according to claim 8, wherein the gate insulating film is etched using the auxiliary conductive layer, the crystallized second oxide layer, and an etch stopper for gate wiring.
  10.   The TFT substrate according to claim 1, further comprising an insulating film on at least the source wiring, the drain wiring, the source electrode, and the drain electrode.
  11.   11. The TFT substrate according to claim 1, wherein an energy gap between the first oxide layer and the second oxide layer is 3.0 eV or more.
  12. Forming a gate electrode and a gate wiring on the substrate using the first mask;
    On the substrate, the gate electrode, and the gate wiring, a gate insulating film, a first oxide layer, a protective layer, and a second resist are laminated in this order, and a channel portion made of the protective layer using a second mask. Forming an etch stopper for gate and an etch stopper for gate wiring;
    A second oxide layer and a third resist are laminated in this order on the first oxide layer, the channel portion etch stopper, and the gate wiring etch stopper, and the third mask is used to form the third oxide layer. Forming the resist in a predetermined shape;
    A source comprising the second oxide layer by etching the second oxide layer and the first oxide layer using the third resist, the channel portion etch stopper and the gate wiring etch stopper. Forming a wiring, a drain wiring, a source electrode, a drain electrode and a pixel electrode;
    After ashing the third resist, the gate portion is protected by the channel portion etch stopper, and the gate wiring etch stopper having an opening and the formed second oxide layer are used to form the gate. And a step of forming a gate wiring pad by etching the insulating film.
  13. Forming a gate electrode and a gate wiring on the substrate using the first mask;
    On the substrate, the gate electrode, and the gate wiring, a gate insulating film, a first oxide layer, a protective layer, and a second resist are laminated in this order, and a channel portion made of the protective layer using a second mask. Forming an etch stopper for gate and an etch stopper for gate wiring;
    A second oxide layer, an auxiliary conductive layer, and a third resist are laminated in this order on the first oxide layer, the channel portion etch stopper, and the gate wiring etch stopper. Forming three resists in a predetermined shape;
    Etching the auxiliary conductive layer, the second oxide layer, and the first oxide layer using the third resist, the channel portion etch stopper, and the gate wire etch stopper to form a source wiring, a drain wiring, Forming a source electrode, a drain electrode and a pixel electrode;
    Re-forming the third resist;
    Changing the etching resistance of the second oxide layer;
    Etching the auxiliary conductive layer on the pixel electrode using the third resist reshaped on the source wiring, the drain wiring, the source electrode, and the drain electrode to form the auxiliary conductive layer; When,
    The gate insulating film is etched using the etch stopper for gate wiring having an opening and the formed second oxide layer while protecting the channel portion by the etch stopper for channel part, and a gate wiring pad A process for producing a TFT substrate, comprising the step of:
  14.   An insulating film and a resist are stacked in this order on the substrate, and the insulating film on the gate wiring pad, the source / drain wiring pad and the pixel electrode is etched using a mask, and at least the source wiring, the drain wiring, 14. The method of manufacturing a TFT substrate according to claim 12, further comprising a step of forming an insulating film on the source electrode and the drain electrode.
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