JP2007227440A - Tft substrate and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method by which the number of manufacturing steps for a TFT substrate can be reduced, manufacturing processing time be shortened, manufacturing cost be greatly reduced, and manufacturing yield be improved; and to provide a TFT substrate using the method. <P>SOLUTION: The TFT substrate is provided with a gate wiring and a gate insulating film, first and second silicon layers, a source-drain wiring and a source-drain electrode, and a pixel electrode connected electrically to the source-drain electrode. Furthermore, it is provided with a lamination film wherein the first silicon layer, the second silicon layer, a first metal film, an interlayer insulation film, a transparent electrode layer connected with the first metal film through a through-hole of the interlayer insulation film, and a second metal film are stacked in this order. All or a part of the lamination film functions as the source-drain electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a TFT substrate used in a liquid crystal display device or an organic EL light emitting device, a manufacturing method thereof, and a TFT array substrate. Further, the present invention relates to a liquid crystal display device and an organic EL display device using the TFT substrate.

  LCDs (liquid crystal display devices) and organic EL display devices are widely used for reasons such as display performance and energy saving. In particular, display devices such as mobile phones, PDAs, personal computers, laptop computers, and televisions have become almost mainstream.

  In these display devices, a TFT (thin film transistor) substrate is generally used.

For example, a liquid crystal display device is configured to fill a display material such as liquid crystal between a TFT substrate and a counter substrate, and to selectively apply a voltage to the display material for each pixel. Here, the TFT substrate generally refers to a substrate on which a TFT (thin film transistor) made of a semiconductor thin film (also called a semiconductor film) or the like is disposed.

  Generally, this TFT substrate is often called a “TFT array substrate” because thin film transistors are arranged in an array. Therefore, the TFT substrate in the present invention includes this TFT array substrate.

  Note that a TFT array substrate used in a liquid crystal display device or the like is a substrate in which a set of TFTs and one pixel of a screen of a liquid crystal display device (referred to as 1UNIT) is arranged vertically and horizontally on a glass substrate. On the glass substrate, the gate wirings are arranged at regular intervals in the vertical direction, for example, and the source or drain wirings are arranged at regular intervals in the horizontal direction. On the other hand, the gate electrode, the source electrode, and the drain electrode are respectively provided in the UNIT constituting each pixel.

Conventional manufacturing method of TFT substrate As a manufacturing method of this TFT substrate, there are usually a five-mask process using five masks, a four-mask process in which the number of masks is reduced to four using halftone exposure, Etc. are known.

  However, since such a TFT substrate manufacturing method uses five or four masks, the manufacturing process tends to have a large number of steps. It is known that even in the case of a four-mask process, 35 steps (processes) and in the case of a five-mask process, a process exceeding 40 steps (processes) is required. As the number of processes increases as described above, the manufacturing yield may be reduced. In addition, since the number of processes is large, the process tends to be complicated, and the possibility of excessive manufacturing costs cannot be ignored.

A state of manufacturing a TFT substrate by a method using five conventional masks using five masks will be described. This manufacturing process will be described with reference to FIG.

  (1) First, metal Al is deposited on the glass substrate 210 by sputtering, and then the gate electrode 212 is provided by etching into a desired shape. A schematic cross-sectional view showing this state is shown in FIG. In order to set the shape of the gate electrode 212, a first mask is required.

  Thereafter, a gate insulating film 213 to be a SiN film (silicon nitride film) and an α-Si: H (i) film 214 are sequentially stacked.

(2) Next, after depositing a SiN film (silicon nitride film) as a channel protective layer, this SiN film is dry-etched into a desired shape using CH 2 _F gas to form a channel protective layer 215. This channel protective layer 215 is called an etch stopper. A schematic cross-sectional view after the channel protective layer 215 is formed is shown in FIG. In order to determine the shape of the channel protective layer 215, a second mask is necessary.

  (3) Next, an α-Si: H (i) film 216 is deposited. Further, a Cr / Al bilayer film is deposited thereon by vacuum evaporation or sputtering.

Thereafter, the Cr / Al bilayer film is etched to form a source electrode 217a and a drain electrode 217b having desired shapes. This etching is performed by photoetching using H ₃ PO ₄ —CH ₃ COOH—HNO ₃ for Al. Cr is performed by photoetching using a ceric ammonium nitrate aqueous solution.

Further, the α-Si: H film (216 and 214) is etched by using both dry etching using CHF gas and wet etching using a hydrazine aqueous solution (NH ₂ —NH ₂ · H ₂ 0) to obtain a desired shape. Α-Si: H (i) film 216 and α-Si: H (i) film 214 are obtained.

  A cross-sectional schematic diagram showing the results of these etchings is shown in FIG. 20 (3). The shape of this etching (source electrode 217a, drain electrode 217b, α-Si: H (i) film 216 and α-Si: In order to define H (i) the pattern of the film 214, a third mask is necessary.

  (4) Next, before forming the transparent electrode 219, an interlayer insulating film 218 is deposited. Then, a through hole 218a for electrically connecting the source electrode 217a and the transparent electrode 219 described below is formed by etching. This formation requires a fourth mask. FIG. 20 (4) shows a schematic cross-sectional view showing a state in which the through hole 218a is opened in the interlayer insulating film 218.

  (5) Next, an amorphous transparent conductive film mainly composed of indium oxide and zinc oxide is deposited on the upper surface on which the pattern of the source electrode 217a and the drain electrode 217b is formed by a sputtering method. This amorphous transparent conductive film is subjected to photo-etching using an aqueous solution of 20% by weight of oxalic acid as an etchant and patterned into a shape that is electrically connected to the source electrode 217a. Thereby, the transparent electrode 219 is formed. This is shown in FIG. 20 (5). In order to define the shape of the transparent electrode 219, a fifth mask is necessary. An example of a manufacturing process of a TFT substrate using five masks is as described above.

As an improvement to the manufacturing method prior art TFT substrate by three mask process, reduce the number of masks (e.g., three), it is considered to manufacture the TFT substrate in a simpler process. Based on this idea, various manufacturing methods using three masks have been proposed.

  However, many of the currently proposed three-mask processes are difficult to put into practical use. For example, the following Patent Document 1, Patent Document 2, Patent Document 3, Patent Document 4, Patent Document 5, Patent Document 6, and Patent Document 7 describe a manufacturing method using such a three-mask process. However, the three-mask process described in these documents must still be said to be a very complicated manufacturing process such as the addition of an anodizing step for the gate insulating film. Therefore, there is almost no merit to use the currently known three-mask process for practical use.

Japanese Patent Laid-Open No. 2004-317685 JP 2004-319655 A JP-A-2005-017669 JP 2005-019664 A JP 2005-049667 A JP 2005-106881 A JP 2005-108912 A

  As described above, a method capable of manufacturing a TFT substrate by a simpler process is strongly desired. In particular, if the number of masks is reduced, the number of processes is reduced, and a TFT substrate can be formed by a simpler process.

  The present invention has been made in view of the above problems, and a method for reducing the number of steps of manufacturing a TFT substrate, shortening the manufacturing processing time, thereby greatly reducing the manufacturing cost, and improving the manufacturing yield. And a TFT substrate thereof.

  (1) In order to solve the above problems, the present invention provides a gate wiring and a gate insulating film, a first silicon layer and a second silicon layer, a source / drain wiring and a source / drain electrode, and the source / drain electrode. A TFT substrate having a pixel electrode electrically connected to the drain electrode, and further comprising the first silicon layer, the second silicon layer, a first metal film, and an interlayer insulating film And a transparent electrode layer connected to the first metal film through the through hole of the interlayer insulating film, and a second metal film are sequentially laminated, and all or one of the laminated films The TFT substrate is characterized in that the portion is the source / drain electrode.

  According to the TFT substrate having such a configuration, it can be manufactured by a manufacturing method in which the number of masks is reduced.

  (2) Further, according to the present invention, the gate wiring and the gate insulating film, the first silicon layer and the second silicon layer, the source / drain wiring and the source / drain electrode, and the source / drain electrode electrically A TFT substrate provided with a gate wiring extraction portion for connecting the gate wiring to an external circuit on the gate wiring, and further comprising the gate wiring; A gate insulating film; the first silicon layer; a through hole opened in the gate insulating film; and a transparent electrode layer connected to the gate wiring through the through hole opened in the first silicon layer; The TFT substrate is characterized in that all or part of the laminated film is all or part of the gate wiring take-out portion.

  According to the TFT substrate having such a configuration, it can be manufactured by a manufacturing method in which the number of masks is reduced.

  (3) Further, the present invention provides a gate wiring and a gate insulating film, a first silicon layer and a second silicon layer, a source / drain wiring that can be a source wiring or a drain wiring, and a source electrode or a drain electrode. And a transparent electrode electrically connected to the source / drain electrode, further comprising: a first metal film; a first transparent conductive film; 2 and a second transparent conductive film, and a part or all of the laminated film is all or part of the source electrode or the drain electrode. TFT substrate characterized by the above.

  According to the TFT substrate having such a configuration, it can be manufactured by a manufacturing method in which the number of masks is reduced.

  (4) Further, according to the present invention, a protective transparent conductive layer is provided on any one of the gate wiring, the source / drain wiring, and the source / drain electrode (3). TFT substrate described in the above.

  With such a configuration, the durability of the TFT substrate can be improved.

  (5) Further, the present invention provides a first metal film, a gate insulating film, a first silicon layer, a second silicon layer, a second metal film, and a first resist on a substrate. And forming the first resist on the 1a resist pattern using a halftone exposure technique, and the first a formed on the 1a resist pattern. Using a resist, forming a gate wiring and a gate electrode, re-forming the first resist into a 1b resist pattern, and using the first resist of the 1b resist pattern Removing the second metal film on the gate wiring and the gate electrode and the second silicon layer to form a channel; an interlayer insulating film on the substrate; And resist in this order. A step of forming the second resist in a second resist pattern, a gate wiring pad portion is formed using the second resist of the second resist pattern, and the interlayer insulating film Forming a through hole on the interlayer insulating film, forming a transparent conductive film, an auxiliary conductive layer, an insulating film, and a third resist on the interlayer insulating film in this order; and a third mask And using the half-tone exposure technique to form the third resist into a 3a resist pattern, and using the third resist of the 3a resist pattern, the source / drain wiring is positioned. The insulating film covering a region, a region where the source / drain electrode is located, the pixel electrode portion, and the gate wiring pad portion, and not covering the third resist Etching the auxiliary conductive layer and the transparent conductive film; re-forming the third resist into a 3b resist pattern; and using the third resist of the 3b resist pattern. And etching the insulating film of the pixel electrode portion and the auxiliary conductive layer to form a transparent pixel electrode, a source / drain wiring pad, and a gate wiring pad. This is a method for manufacturing a TFT substrate.

  With such a configuration, a TFT substrate can be manufactured using three masks.

  (6) Further, according to the present invention, a first metal film, a first metal film protecting transparent conductive layer, a gate insulating film, a first silicon layer, and a second silicon layer are formed on a substrate. , Forming a second metal film, a second metal film protecting transparent conductive layer, and a first resist in this order, and using the halftone exposure technique, the first resist is A step of forming a resist pattern of 1a, a step of forming a gate wiring and a gate electrode by using the first resist formed in the pattern of 1a, and a step of forming the first resist as 1b. Re-forming the resist pattern, using the first resist of the 1b resist pattern, the second metal film on the gate wiring and the gate electrode, the second silicon layer, Removing and forming a channel; and An interlayer insulating film and a second resist are formed in this order on the plate, and the second resist is formed into a second resist pattern by an exposure technique using a second mask. Forming a gate wiring pad portion using the second resist of the second resist pattern, further forming a through hole in the interlayer insulating film, and transparent on the interlayer insulating film; The step of forming a conductive film, an auxiliary conductive layer, an insulating film, and a third resist in this order, and using a third mask, the third resist is applied to the third a by a halftone exposure technique. Forming the resist pattern, and using the third resist of the 3a resist pattern, the source / drain wiring, the source / drain electrode, the pixel electrode portion, and the gate wiring pattern. A step of etching the insulating film, the auxiliary conductive layer, and the transparent conductive film in a region that is covered with the third resist and is not covered with the third resist, and the third resist is a third resist. Re-forming the pattern, using the third resist of the 3b resist pattern, the gate wiring pad, the source / drain wiring pad, the insulating film of the pixel electrode portion, and the auxiliary conductive And a step of etching the layer to form a transparent pixel electrode, a source / drain wiring pad, and a gate wiring pad.

  With such a configuration, a TFT substrate can be manufactured using three masks.

Hereinafter, the invention related to Example 2 (7) The present invention also relates to a gate wiring metal film and a gate insulating film, a first silicon layer and a second silicon layer, and a plurality of source / drain wirings and source / drains. And a pixel electrode electrically connected to the source / drain electrode, and further, the first silicon layer, the second silicon layer, a third metal film, and an interlayer insulation A laminated body formed by laminating a film, a transparent electrode layer connected to the third metal film through a through hole of the interlayer insulating film, and a metal layer in this order; The part or the whole is a part or the whole of the source / drain electrode, and the first silicon layer is a part or the whole of the source / drain wiring. Said first silico Layer is a TFT array substrate, wherein said first silicon layer of the other of the source and drain lines, an electrically that are insulated.

  According to the TFT array substrate having such a configuration, it can be manufactured by a manufacturing method in which the number of masks is reduced.

  (8) Further, the present invention provides a gate wiring metal film and a gate insulating film, a first silicon layer and a second silicon layer, a plurality of source / drain wirings and source / drain electrodes, and the source / drain electrodes. A pixel electrode electrically connected to the first silicon layer, the second silicon layer, the third metal layer, the interlayer insulating film, and the interlayer insulating film. A transparent electrode layer connected to the third metal film through a through hole and a metal layer are provided, and the first laminate is formed in this order, and all or one of the first laminates is provided. The part is a part or all of the source / drain electrode part, and the first silicon layer of any one of the source / drain wirings is electrically insulated from the first silicon layer of the other source / drain wirings The gate wiring gold And a transparent electrode layer connected to the source / drain wiring via a through hole opened in the gate insulating film and a through hole opened in the first silicon layer. The TFT array substrate is characterized in that all or part of the second stacked body is all or part of a gate wiring pad.

  According to the TFT array substrate having such a configuration, it can be manufactured by a manufacturing method with a reduced number of masks, and insulation between a certain source / drain wiring and another source / drain wiring is ensured. be able to.

  (9) Further, the present invention provides a gate wiring metal film and a gate insulating film, a first silicon layer and a second silicon layer, a plurality of source / drain wirings and source / drain electrodes, and the source / drain electrodes. A pixel electrode electrically connected to the first silicon layer, the second silicon layer, the third metal layer, the interlayer insulating film, and the interlayer insulating film. A first laminated body formed by laminating a transparent conductive layer connected to the third metal layer through a through hole, a metal layer, and a transparent conductive layer in this order; Are all or part of the source / drain electrode portion, and the first silicon layer of any one of the source / drain wirings is connected to the first silicon layer of the other source / drain wirings. It is electrically isolated and A second stacked body in which the third metal layer, the transparent conductive film, the metal layer, and the transparent conductive film are stacked in this order, and all or one of at least one of the source / drain electrodes. The TFT array substrate is characterized in that the portion is all or part of the second stacked body.

  According to the TFT array substrate having such a configuration, it can be manufactured by a manufacturing method in which the number of masks is reduced, and insulation between a certain source / drain wiring and another source / drain wiring is ensured. can do.

  (10) The present invention is the TFT array substrate according to any one of (7) to (9), wherein a transparent conductive layer for protecting a metal thin film is provided on the metal film.

  With such a configuration, the durability of the TFT array substrate can be improved.

  (11) The TFT according to any one of (7) to (9), wherein the third metal layer protecting transparent conductive layer is provided on the third metal layer. It is an array substrate.

  With such a configuration, the durability of the TFT array substrate can be improved.

  (12) The present invention is the TFT array substrate according to any one of claims 7 to 9, wherein a transparent conductive layer for protecting the metal layer is provided on the metal layer.

  With such a configuration, the durability of the TFT array substrate can be improved.

  (13) Further, the present invention provides a gate wiring metal film, a gate insulating film, a first silicon layer, a second silicon layer, a third metal film, and a first resist on a substrate. Are formed in this order, a step of forming the first resist on the 1a resist pattern using a first mask and using a halftone exposure technique, and forming on the 1a resist pattern. The step of etching the gate wiring metal film using the formed first resist to form the gate wiring metal film to be a gate wiring and a gate electrode; and Re-forming the resist pattern, and using the first resist formed in the first-b resist pattern, the third metal film on the gate wiring and the gate electrode, the second silicon , And forming a channel, the gate wiring, the gate electrode, and the gate insulating film, and the second electrode on the gate electrode and the gate insulating film. An interlayer insulating film and a second resist are formed in this order on the substrate having a source / drain electrode composed of a silicon layer, the first silicon layer, and the third metal film. A step of forming a desired 2a resist pattern on the second resist using a halftone exposure technique using a second mask, and the second resist formed on the 2a resist pattern. A step of forming a through hole in a gate wiring pad portion, which is a region where a gate wiring pad is provided, using a resist; and the second resist of the second a resist pattern is changed to a second b A step of re-forming into a resist pattern, and using the second resist formed in the second b resist pattern, through the interlayer insulating film in the source / drain electrode portion which is a region where the source / drain electrode is provided A step of forming a hole, a step of etching and removing the first silicon layer between the source / drain wirings, a transparent conductive film, a metal layer, an insulating film, and a third resist in this order. Forming a third resist pattern using the third mask and halftone exposure technology using a third mask; and forming the third resist pattern on the third a Using a third resist, the source / drain wiring, the source / drain electrode, a pixel electrode portion in which the pixel electrode is located, and the gate A step of etching and removing the insulating film, the metal layer, and the transparent conductive film except for a wiring pad portion, and a step of re-forming the third mask into a resist pattern 3b. And using the third mask formed in the 3b resist pattern, the insulating film located in the gate wiring pad portion, the source / drain wiring pad portion, and the pixel electrode portion, and And a step of etching and removing the metal layer.

  With such a configuration, a TFT array substrate can be manufactured using three masks, and insulation between a certain source / drain wiring and another source / drain wiring can be secured.

  (14) Further, according to the present invention, a gate wiring metal film, a transparent conductive layer for protecting a metal film, a gate insulating film, a first silicon layer, a second silicon layer, A step of forming a metal film, a third metal film protecting transparent conductive layer, and a first resist in this order, and using the first mask and halftone exposure technique, Using the step of forming a resist in a 1a resist pattern and the first resist formed in the 1a resist pattern, the gate wiring metal film is etched, and the gate wiring metal film is formed into a gate wiring. And a step of forming a gate electrode, a step of re-forming the first resist into a 1b resist pattern, and the first resist formed in the first b resist pattern, Gate arrangement And a step of removing the third metal film protecting transparent conductive layer, the third metal film, and the second silicon layer on the gate electrode to form a channel, and the gate The substrate including a wiring, the gate electrode, and the gate insulating film, wherein the second silicon layer, the first silicon layer, and the third on the gate electrode and the gate insulating film Forming an interlayer insulating film and a second resist in this order on the substrate having the source / drain electrodes comprising the metal film and the transparent conductive layer for protecting the third metal film; A step of forming a desired second resist pattern on the second resist by using a second mask and a halftone exposure technique; and the second resist formed on the second resist pattern. Use gate wiring A step of forming a through hole in a gate wiring pad portion, which is a region where a pad is provided, a step of re-forming the second resist of the second a resist pattern into a second resist pattern, and the second a Using the second resist formed in the resist pattern, forming a through hole in the interlayer insulating film of the source / drain electrode portion, which is a region where the source / drain electrode is provided, and a source / drain wiring Etching and removing the first silicon layer in between, a transparent conductive film, a metal layer, a transparent conductive layer for protecting the metal layer, an insulating film, and a third resist are formed in this order. A step of forming the third resist into a 3a resist pattern using a third mask and using a halftone exposure technique; and Using the third resist formed in a resist pattern, the source / drain wiring, the source / drain electrode, a pixel electrode part in which the pixel electrode is located, the gate wiring pad part, The step of etching and removing the insulating film, the transparent conductive layer for protecting the metal layer, the metal layer, and the transparent conductive film, and converting the third resist into a resist pattern of 3b After the re-formation, the insulation located in the gate wiring pad portion, the source / drain wiring pad portion, and the pixel electrode portion using the third resist formed in the resist pattern of 3b. And a step of etching and removing the film, the transparent conductive layer for protecting the metal layer, and the metal layer.

  With such a configuration, a TFT array substrate can be manufactured using three masks, and insulation between a certain source / drain wiring and another source / drain wiring can be secured.

  (15) Further, in the present invention, the transparent conductive film includes a first metal oxide group comprising indium oxide, zinc oxide, tin oxide, germanium oxide, zirconium oxide, tungsten oxide, molybdenum oxide, and a lanthanoid oxide element. The TFT substrate or the TFT array substrate according to any one of claims (1) to (4) or (7) to (9), comprising at least one metal oxide selected from is there.

  With such a configuration, selective etching can be realized.

  (16) Further, in the present invention, the content of the metal oxide added to the indium oxide in the transparent conductive film is 1 to 20 wt% with respect to indium oxide. TFT substrate or TFT array substrate.

  With such a configuration, resistance to a phosphoric acid / acetic acid / nitric acid etching solution in selective etching can be obtained while preventing an increase in specific resistance.

  (17) Further, according to the present invention, the transparent conductive layer for protecting the metal film, and the transparent conductive layer for protecting the barrier metal film include indium oxide, zinc oxide, tin oxide, tungsten oxide, cerium oxide, and a lanthanoid oxide. One or more metal oxides selected from the second metal oxide group consisting of: a composition ratio of indium oxide, zinc oxide, tin oxide, tungsten oxide, and cerium oxide in the transparent conductive film is oxidized. The TFT substrate or TFT array substrate according to any one of (4), (10), (11), and (12), which is 1 to 20 wt% with respect to indium. .

  With such a configuration, selective etching can be realized.

(18) In the present invention, the transparent conductive film is selected from a first metal oxide group consisting of indium oxide, tin oxide, germanium oxide, zirconium oxide, tungsten oxide, molybdenum oxide, and a lanthanoid oxide element. One or more metal oxides,
(5), (6), (13) or (14) is a method for manufacturing a TFT substrate or a TFT array substrate according to any one of the above, wherein the battery reaction is suppressed by such a configuration. be able to.

  (19) Further, in the present invention, the content of the metal oxide added to the indium oxide in the transparent conductive film is 1 to 20 wt% with respect to indium oxide. It is a manufacturing method of a TFT substrate or a TFT array substrate.

  With such a configuration, selective etching can be realized.

  (20) In the present invention, the first transparent conductive layer for protecting a metal film and the second transparent conductive layer for protecting a metal film include indium oxide, zinc oxide, tin oxide, tungsten oxide, and oxide. One or more metal oxides selected from a second metal oxide group consisting of cerium and a lanthanoid oxide, and indium oxide, zinc oxide, tin oxide, tungsten oxide and cerium oxide in the transparent conductive film (5), (6), (13) or (14) production of TFT substrate or TFT array substrate, characterized in that the composition ratio is 1-20 wt% with respect to indium oxide Is the method.

  With such a configuration, selective etching can be realized.

  As described above, according to the present invention, the number of masks used for manufacturing is reduced to three, so that the number of manufacturing steps can be reduced, the processing time can be shortened, and the manufacturing yield can be improved. Furthermore, according to the present invention, since the number of steps is reduced, it is expected that the manufacturing cost is reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In this embodiment, a manufacturing operation of a TFT (array) substrate using three masks will be described.

"Example 1"
Hereinafter, Example 1 will be described.

(A) Processing using the first mask
Metal Thin Film First, a thin metal film 12 having a thickness of 250 nm and 50 nm was formed on a light-transmitting glass substrate 10 by using a high frequency sputtering method in the order of Al and Mo. Thus, a metal thin film 12 composed of two layers of Al and Mo is formed on the glass substrate 10.
In addition, Ti, Cr, etc. can be used as metals other than Mo. This metal thin film 12 becomes a gate wiring.

  By the way, it is conceivable to use a metal thin film such as Ag or Cu or an alloy thin film as the gate wiring. However, since it may be difficult to form an oxide film, it is preferable to use an Al system as in this embodiment.

  Al may be pure Al, but metals such as Nd, Ce, Mo, W, Nb may be added. Ce, W, Nb, etc. are also suitable for suppressing the battery reaction with the transparent conductive film. The addition amount can be selected as appropriate, but is preferably 0.1 wt% to 2.0 wt%.

  The metal thin film 12 corresponds to a preferred example of the first metal film in the claims.

The gate insulating film and then the glow discharge CVD method to a thickness of 300nm is deposited a gate insulating film 14 is a silicon nitride (SiNx) film. As the discharge gas, a mixed gas of SiH ₄ —NH ₃ —N ₂ was used.

Next, an α-Si: H (i) film 16 is deposited to a thickness of 350 nm, following the first silicon layer and the second silicon layer . The α-Si: H (i) film 16 corresponds to a preferred example of the first silicon layer in the claims.
At this time, as the discharge gas, the α-Si: H (i) film 16 uses a SiH ₄ —N ₂ -based mixed gas.

Subsequently, an α-Si: H (n) film 18 is deposited with a film thickness of 300 nm using a SiH ₄ —H ₂ —PH ₃ -based mixed gas. The α-Si: H (n) film 18 corresponds to a preferred example of the second silicon layer in the claims.

Barrier metal Next, a barrier metal 20 made of Mo is deposited thereon by a 50 nm-thickness sputtering method. The barrier metal 20 corresponds to a preferred example of the second metal film (or the third metal film) in the claims.

Resist Next, a first resist film 22 was formed.
6 layers are provided on the glass substrate 10 by the above processes. This is shown in the cross-sectional view of FIG.

Halftone exposure Then , the first resist film 22 is formed in a desired resist pattern by halftone exposure. This pattern is referred to as a 1a resist pattern.

Formation Next, the barrier metal 20 as the Mo film is etched using phosphoric acid / acetic acid / nitric acid / water (9: 8: 1: 2 volume ratio) -based etching solution. In this embodiment, a Mo film is used as the barrier metal 20, but a Ti film or a Cr film may be used.
Further, the α-Si: H films 16 and 18 are etched by using both dry etching using CHF gas and wet etching using hydrazine (NH ₂ —NH ₂ .H ₂ O) aqueous solution. As a result, the α-SiH (i) film 16 is formed in a desired pattern, and the α-Si: H (n) film 18 is also formed in a desired pattern.

Subsequently, the gate insulating film 14 is etched by dry etching using CHF gas. Further, the metal thin film 12 was etched using a phosphoric acid / acetic acid / nitric acid / water (9: 8: 1: 2 volume ratio) etching solution. As described above, the metal thin film 12 is a Mo / Al laminated film, but a Cr / Al laminated film or a Ti / Al laminated film may be used.
In this way, the first etching is finished. A plan view after the completion of the first etching is shown in FIG. In FIG. 2, the first resist film 22 located in the uppermost layer is omitted and not shown.

  Thereafter, the resist pattern of the first resist 22 is re-formed into a 1b resist pattern by ashing. Using the first resist 22 of this 1b resist pattern, the barrier metal (Mo film) 20 and the α-Si: H (n) film 18 were etched by the above-described method to form a channel. Then, the first resist 22a is removed.

  FIG. 3 is a plan view showing how the channel is formed in this way.

(B) Treatment Using Second Mask Next, an insulating protective film 30 that is a silicon nitride (SiNx) film is deposited by a glow discharge CVD method to a thickness of 300 nm. As the discharge gas, a mixed gas of SiH ₄ —NH ₃ —N ₂ was used. Further, a second resist 32 was applied.
Next, the 2nd resist 32 was shape | molded with the 2nd mask, and the predetermined resist pattern was formed.

  Then, the insulating protective film 30 was etched by dry etching using CHF gas to form through holes in the gate wiring pad portion and the source / drain electrode portions. Then, the barrier metal 20 in the source / drain wiring pad portion was exposed (see the SDP portion in FIG. 4).

  Furthermore, the metal thin film 12 in the gate wiring pad portion was exposed by this etching (see the GP portion in FIG. 4). Next, the second resist 32 was peeled off.

  The state after such processing is shown in FIG. However, in FIG. 4, the insulating protective film 30 is not drawn in three dimensions, and the position where the insulating protective film 30 is provided is indicated by hatching. It will be understood from FIG. 4 that the insulating protective film 30 is provided in a region other than the through hole provided in the gate pad portion (GP portion) and the source / drain pad portion (SDP portion).

(C) Treatment Using Third Mask Next, an indium oxide-zinc oxide-tin oxide based transparent conductive film 24 was deposited to a thickness of 120 nm by sputtering as a transparent conductive film. Subsequently, Mo / Al films were formed to a thickness of 50 nm and 250 nm, respectively, and an auxiliary conductive film 26 was formed. Subsequently, SiNx was deposited to 200 nm by the above-described method, and the insulating film 40 was formed. Subsequently, a third resist film 28 was formed.

  Here, using the third mask, the third resist 28 was formed into a desired 3a resist pattern by halftone exposure.

  After the third resist 28 is formed in the resist pattern 3a, the insulating film 40, the auxiliary conductive film 26, and the transparent conductive film in portions other than the pixel electrode portion PD, the source / drain wiring portion SDW, and the gate wiring pad portion GP. The film 24 was etched (see FIGS. 5 and 6). The auxiliary conductive film 26 is a Mo / Al laminated film as described above.

  The state after this etching is shown in FIG. 6 is a diagram in which the pixel electrode portion PD, the source / drain wiring portion SDW, and the gate wiring pad portion GP are hatched on the same diagram as FIG.

  In FIG. 5, the third resist is omitted and not shown, but the third resist covers portions other than the pixel electrode portion PD, the source / drain wiring portion SDW and the gate wiring pad portion GP shown in FIG. This shape is the 3a resist pattern.

  5 and 6, the insulating protective film 30 (the position of which is shown in FIG. 4) is not shown for the sake of convenience in order to make it easier to see the underlying structure.

  In the above etching, the auxiliary conductive film 26, which is a Mo / Al laminated film, was etched using a phosphoric acid / acetic acid / nitric acid / water (9: 8: 1: 2 volume ratio) etching solution as described above. . The insulating film 40 was etched using dry etching using CHF gas. The transparent conductive film 24 was etched with an oxalic acid aqueous solution.

  Thereafter, the resist pattern was re-formed by ashing to re-form the resist pattern 3b.

  Next, using the third resist 28 of the 3b resist pattern, the insulating film 40 and the auxiliary conductive film 26 (Mo / Al film) in the following regions were etched.

(A) Pixel electrode part PD
(A) Source / drain wiring pad part SDWP
(C) Gate wiring pad part GP
The insulating film 40 and the auxiliary conductive film 26 (Mo / Al film) located in these regions were etched. In FIG. 7, these areas are indicated by hatching. The insulating film 40 was etched using dry etching using CHF gas. The auxiliary conductive film 26 was etched using a phosphoric acid / acetic acid / nitric acid / water (9: 8: 1: 2 volume ratio) -based etching solution.

  By such etching, the transparent pixel electrode 50, the source / drain wiring pad 52, and the gate wiring pad 54 were formed. This is shown in FIG. However, in FIG. 8, the third resist 28 is not shown in order to show the state of lamination. As will be described later, FIG. 8 can also be said to be a state in which the third resist is removed.

  The transparent pixel electrode 50 represents an “electrode”, and the pixel electrode portion PD represents an “area / location” where the transparent pixel electrode is located. The source / drain wiring pad represents a “pad”, and the source / drain wiring pad portion SDWP represents a “region / location” where the source / drain wiring pad is located. The gate wiring pad also represents a “pad”, and the gate wiring pad portion GP represents a “region / location” where the gate wiring pad is located.

  Finally, the third resist 28 was removed, and a desired TFT substrate was obtained. The result is shown in FIG.

"Example 2"
Next, Example 2 will be described. In Example 2, the insulation between adjacent source / drain wirings is improved.

(A) Processing Using First Mask Since the processing using the first mask in the second embodiment is the same as that in the first embodiment, refer to the first embodiment.

(B) Treatment Using Second Mask Next, an insulating protective film 30 that is a silicon nitride (SiNx) film is deposited to a thickness of 250 nm by glow discharge CVD. As the discharge gas, a mixed gas of SiH ₄ —NH ₃ —N ₂ was used. Further, a second resist 32 was applied.
Next, by using halftone exposure, the second resist 32 was formed with the second mask to form a predetermined second-a resist pattern.

  Then, the insulating protective film 30 was etched by dry etching using CHF gas to expose the metal thin film 12 of the gate wiring pad portion (GP) (see the GP portion in FIG. 9).

  Further, the second resist pattern was ashed and re-formed into a second resist pattern. Using the second resist 32 formed into the second b resist pattern, the following two locations were etched.

  (First location) First, the insulating protective film 30 of the source / drain wiring pad portion (SDP in FIG. 9) was etched to form a through hole in the source / drain wiring pad portion. The formation of the through hole exposes the barrier metal 20.

  (Second location) Further, the α-Si: H (i) film (first silicon layer) 16 is etched in order to ensure insulation between the plurality of source / drain wirings. The etching place is the W portion in FIG. FIG. 9 is a plan view showing the state after the etching. In FIG. 9, in order to clearly show the structure of each layer, the second resist 32 and the insulating protective film 30 are not shown. FIG. 10 shows a cross-sectional view of the A-A ′ portion and the B-B ′ portion of FIG. 9.

  In the second embodiment, the α-Si: H (i) film (first silicon layer) 16 in the W portion is etched to ensure insulation between source / drain wirings to be arranged later. Yes. This significance will be described with reference to FIG.

Insulation between source / drain wirings As the name suggests, the TFT array substrate manufactured in Example 2 is a substrate in which a plurality of TFTs (thin film transistors) are arranged in an array. A part of the situation is shown in FIG. FIG. 11 is an explanatory diagram showing a state where four TFTs (thin film transistors) are arranged in a “field-shaped” shape. The rectangle in which this one TFT is arranged is called UNIT60. Actually, a large number of such UNITs 60 are arranged vertically and horizontally. For convenience, in FIG. 11, the four UNITs 60 are referred to as UNIT 60a, UNIT 60b, UNIT 60c, and UNIT 60d.

  As shown in FIG. 11, the UNITs 60a, 60b, 60c, and 60d are provided with source / drain wirings 70a, 70b, 70c, and 70d, respectively. The source / drain wiring 70 is connected between the UNITs 60 adjacent in the horizontal direction. That is, the source / drain wiring 70a is connected to the source / drain wiring 70d of the UNIT 60d in the lateral direction. Further, the source / drain wiring 70b is connected to the source / drain wiring 70c of the UNIT 60c in the lateral direction. In this way, the source / drain wiring 70 employs a configuration that is continuous in the horizontal direction.

  On the other hand, each of the UNITs 60a, 60b, 60c, 60d is provided with a gate wiring 72a, 72b, 72c, 72d, respectively. The gate wiring 72 is connected between the UNITs 60 adjacent in the vertical direction. That is, the gate wiring 72a is connected to the gate wiring 72b of the UNIT 60b in the vertical direction. The gate wiring 72d is connected to the gate wiring 72c of the UNIT 60c in the vertical direction. Thus, the gate wiring 72 employs a configuration that is continuous in the vertical direction.

  What is characteristic in the second embodiment is that the α-Si: H (i) film (first silicon layer) 16 is removed by etching in the W portion of the gate wiring 72, and the gate insulating film 14 therebelow is removed. It is a point that is exposed. As a result, the electrical connection in the vertical direction of the α-Si: H (i) film 16 is cut off, and insulation between the adjacent source / drain wirings 70 can be ensured.

  In other words, the presence of the α-Si: H (i) film 16 may not ensure insulation between the source / drain wiring 70a and the source / drain wiring 70b, and may cause cross talk. In Example 2, such fear is reduced.

  As described above, since the vertical connection of the α-Si: H (i) film 16 in the gate wiring 72 is cut off, the portion where the α-Si: H (i) film 16 is etched may be anywhere. Absent. In the second embodiment, the portion W that overlaps with the source / drain wiring 70 is selected as the portion to be etched, but other portions may be used. In short, it does not matter where the vertical connection is broken.

  FIG. 12 shows a cross-sectional view of C-C ′ (that is, the W portion) of FIG. 9 in order to show such a state of etching of the W portion. FIG. 12 shows a cross-sectional view of both (1) before etching and (2) after etching.

  As described above, in the second embodiment, a part of the α-Si: H (i) film 16 positioned between the source / drain wirings 70 belonging to other adjacent TFTs is removed by etching, thereby removing the source. The insulation between the drain wirings 70 can be ensured, and effects such as reduction of crosstalk can be obtained.

  Therefore, if the TFT substrate according to Example 2 is used, a high-quality TFT liquid crystal substrate, a high-quality organic EL substrate, and a high-quality inorganic EL light emitting device can be configured.

(C) Treatment Using Third Mask Next, an indium oxide-zinc oxide-tin oxide transparent conductive film 124 was deposited as a transparent conductive film to a thickness of 120 nm by sputtering. Subsequently, Mo / Al films were formed to a thickness of 50 nm and 250 nm, respectively, and an auxiliary conductive film 126 was formed. Subsequently, 200 nm of SiNx was deposited by the method described above to form an insulating protective film 140. Subsequently, a third resist film 128 was formed.

  A cross-sectional view showing the state of such deposition is shown in FIG. FIG. 13 shows a state in which the above layers are deposited from the state of FIG. However, the last third resist 128 is omitted and not shown.

  Here, the third resist 128 was formed into a desired 3a resist pattern by halftone exposure using the third mask.

  After the third resist 28 is formed in the resist pattern 3a, the insulating protective film 140, the auxiliary conductive film 126, and the transparent portion other than the pixel electrode portion PD, the source / drain wiring portion SDW, and the gate wiring pad portion GP are formed. The conductive film 124 was etched (see FIGS. 14 and 16). The auxiliary conductive film 26 is a Mo / Al laminated film as described above.

  The state after this etching is shown in FIG. FIG. 15 is a cross-sectional view taken along lines D-D ′, E-E ′, and F-F ′ in FIG. FIG. 16 is a diagram showing the pixel electrode portion PD, the source / drain wiring portion SDW, and the gate wiring pad portion GP by hatching on the same diagram as FIG.

  In FIG. 14, the third resist 128 is omitted and not shown, but the portions other than the pixel electrode portion PD, the source / drain wiring portion SDW and the gate wiring pad portion GP shown in FIG. This shape is the 3a resist pattern.

  14 and 16, the insulating protective film 30 (the position thereof is the same as the position shown in FIG. 4 described above) is not shown for the sake of convenience in order to make it easier to see the underlying structure. Also, in the cross-sectional view 15, the insulating protective film 30 is omitted and not shown.

  In the above etching, the auxiliary conductive film 126, which is a Mo / Al laminated film, was etched using a phosphoric acid / acetic acid / nitric acid / water (9: 8: 1: 2 volume ratio) etching solution as described above. . The insulating protective film 140 was etched using dry etching using CHF gas. The transparent conductive film 124 was etched with an oxalic acid aqueous solution.

  Thereafter, the resist pattern was re-formed by ashing to re-form the resist pattern 3b.

  Next, using the third resist 128 of the 3b resist pattern, the insulating protective film 140 and the auxiliary conductive film 126 (Mo / Al film) in the following regions were etched.

(A) Pixel electrode part PD
(A) Source / drain wiring pad part SDWP
(C) Gate wiring pad part GP
The insulating protective film 140 and the auxiliary conductive film 126 (Mo / Al film) located in these regions were etched. In FIG. 17, these areas are indicated by hatching.

  Moreover, the state after etching is shown in FIG. Further, FIG. 19 shows sectional views taken along lines G-G ′, H-H ′, and I-I ′ in FIG. 18.

  The insulating protective film 140 was etched using dry etching using CHF gas. The auxiliary conductive film 126 was etched using a phosphoric acid / acetic acid / nitric acid / water (9: 8: 1: 2 volume ratio) etching solution.

  By such etching, the transparent pixel electrode 150, the source / drain wiring pad 152, and the gate wiring pad 154 were formed. This is shown in FIG. A cross-sectional view thereof is shown in FIG. However, in FIG. 18, the third resist 128 is not shown in order to show the state of lamination. In other words, FIG. 18 can be said to be a diagram after the third resist is removed.

  Finally, the third resist 128 was removed to obtain a desired TFT substrate. The result is shown in FIG. 18 described above.

(D) Consideration about etching Here, the indium oxide-zinc oxide-tin oxide based transparent conductive film 24 (124) used as the transparent conductive film 24 (124) in this embodiment can be etched with oxalic acid, but phosphoric acid. -With acetic acid / nitric acid based etchants, the etching rate is slow and etching is not performed.

  Moreover, this transparent conductive film 24 (124) can exhibit selective etching property by controlling the content of zinc oxide-tin oxide. The content of zinc oxide-tin oxide is required to be 20% by weight or more, and the remainder may be indium oxide. The zinc oxide content is preferably 10 to 40% by weight, and the tin oxide content is preferably 10 to 40% by weight. This is because if it is less than 10% by weight, the resistance to the phosphoric acid / acetic acid / nitric acid etching solution may be lost. On the other hand, if it is 40% by weight or more, the specific resistance may increase.

  Preferably, a configuration in which zinc oxide is 10 to 30% by weight, tin oxide is 15 to 30% by weight, and the remainder is indium oxide is suitable.

  In the present embodiment, an indium oxide-zinc oxide-tin oxide based transparent conductive film is used as the transparent conductive film 24 (124). However, the present invention is not limited to this, and other types of transparent conductive films are used. But it ’s okay.

  Any transparent conductive film can be used as long as it can be etched with an aqueous oxalic acid solution and does not dissolve in a mixed acid of phosphoric acid, acetic acid and nitric acid. In addition, for example, in an amorphous state, it dissolves in an aqueous oxalic acid solution or a mixed acid of phosphoric acid / acetic acid / nitric acid, but brings about a film quality change such as crystallization by heating, etc. A transparent conductive film can also be used.

  As described above, examples of the transparent conductive film that can be used by performing a treatment such as heating include indium oxide added with one or more metal oxides selected from the following metal oxide group.

Metal oxide group: {tin oxide, germanium oxide, zirconium oxide, tungsten oxide, molybdenum oxide, lanthanoid metal oxide}
Examples of the lanthanoid experience genus oxide include cerium oxide.

  Among these, combinations of {indium oxide and tin oxide}, {indium oxide and tungsten oxide}, and {indium oxide and lanthanoid oxide elements (for example, cerium oxide)} are particularly preferably used.

  The amount of metal to be added is 1 to 20 wt%, preferably 3 to 15 wt% with respect to indium oxide. If it is less than 1 wt%, it may crystallize during film formation and may not be dissolved in an aqueous oxalic acid solution, or the specific resistance may increase, making it unsuitable for use as a transparent conductive film. On the other hand, if it exceeds 20 wt%, when film quality changes such as crystallization are caused by heating or the like, the film quality does not change, but it dissolves in a mixed acid of phosphoric acid / acetic acid / nitric acid, which makes it difficult to form pixel electrodes. May occur.

(E) Transparent conductive film for protection It is also preferable to provide a transparent conductive layer for protecting a metal thin film on a metal thin film, or to provide a transparent conductive layer for protecting a barrier metal on a barrier metal layer.

  By adopting such a configuration, when the through hole is formed in the interlayer insulating film, the metal thin film as the underlayer and the barrier metal layer are not damaged. Therefore, the TFT substrate finally obtained will operate more stably, and it is expected that a liquid crystal display device or an electroluminescent device produced using the TFT substrate will also operate stably. Is done.

  In addition, it is preferable to use the same material as the transparent conductive film as the transparent conductive layer for protecting the metal thin film and the transparent conductive layer for protecting the barrier metal. By using the same material, it can prevent that the kind of material increases. Note that the material may be selected from etching characteristics, protective film characteristics, and the like.

It is sectional drawing which shows a mode that the predetermined | prescribed film | membrane was laminated | stacked on the glass substrate. It is a top view after the first etching was completed using the first mask. It is a top view which shows a mode that the channel was formed. It is a top view which shows the mode after the etching using a 2nd mask. It is a top view which shows the mode after the etching using a 2nd mask. In FIG. 5, the pixel electrode part PD, the source / drain wiring part SDW, and the gate wiring pad part GP are hatched. FIG. 5 is a plan view showing a pixel electrode part PD, a source / drain wiring pad part SDWP, and a gate wiring pad part GP by hatching. It is a top view which shows a mode that the transparent pixel electrode, the source / drain wiring pad, and the gate wiring pad were formed. 6 is a plan view showing a state after etching using the second mask of Example 2. FIG. FIG. 10 is a cross-sectional view taken along lines A-A ′ and B-B ′ of FIG. 9. It is explanatory drawing which shows the state by which four TFT (thin film transistor) is arrange | positioned at a "field shape" type | mold. FIG. 10 is a cross-sectional view of C-C ′ (W portion) of FIG. 9. In Example 2, it is sectional drawing which shows a mode that the transparent conductive film, the auxiliary conductive film, and the insulating protective film were deposited. It is a top view after the etching using a 3rd mask. It is sectional drawing of FIG. In FIG. 14, the pixel electrode portion PD, the source / drain wiring portion SDW, and the gate wiring pad portion GP are hatched. FIG. 8 is a diagram showing hatching of a pixel electrode portion PD, a source / drain wiring pad portion SDWP, and a gate wiring pad portion GP in Example 2. 6 is a plan view showing a state after etching using a third mask of Example 2. FIG. It is sectional drawing of FIG. It is a cross-sectional schematic diagram for demonstrating the conventional method using five masks.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Glass substrate 12 Metal thin film 14 Gate insulating film 16 α-Si: H (i) film 18 α-Si: H (n) film 20 Barrier metal 22 First resist film 24 Transparent conductive film 26 Auxiliary conductive film 28 Third Resist 30 insulating protective film 32 second resist 40 insulating film 50 transparent pixel electrode 52 source / drain wiring pad 54 gate wiring pad 60 UNIT
70 Source / drain wiring 72 Gate wiring 100 Container 124 Transparent conductive film 126 Auxiliary conductive film 128 Third resist (film)
140 Insulating protective film 150 Transparent pixel electrode 152 Source / drain wiring pad 154 Gate wiring pad 210 Glass substrate 212 Gate electrode 213 Gate insulating film 214 α-Si: H (i) film 215 Channel protective layer 216 α-Si: H (i ) Film 217a source electrode 217b drain electrode 218 interlayer insulating film 219 transparent electrode GP gate wiring pad part PD pixel electrode part SDW source drain wiring part SDWP source drain wiring pad part

Claims (20)

A gate wiring and a gate insulating film;
A first silicon layer and a second silicon layer;
Source / drain wiring and source / drain electrodes;
A pixel electrode electrically connected to the source / drain electrode;
A TFT substrate comprising:
The first silicon layer;
The second silicon layer;
A first metal film;
An interlayer insulating film;
A transparent electrode layer connected to the first metal film through a through hole of the interlayer insulating film;
A second metal film;
Having a laminated film laminated in the order of
A TFT substrate, wherein all or part of the laminated film is the source / drain electrode. A gate wiring and a gate insulating film;
A first silicon layer and a second silicon layer;
Source / drain wiring and source / drain electrodes;
A pixel electrode electrically connected to the source / drain electrode;
And a TFT substrate provided with a gate wiring take-out portion for connecting the gate wiring to an external circuit on the gate wiring, and
The gate wiring;
The gate insulating film;
The first silicon layer;
A transparent electrode layer connected to the gate wiring through a through hole opened in the gate insulating film and a through hole opened in the first silicon layer;
Having a laminated film laminated in the order of
A TFT substrate, wherein all or part of the laminated film is all or part of the gate wiring extraction portion. A gate wiring and a gate insulating film;
A first silicon layer and a second silicon layer;
A source / drain wiring that can be a source wiring or a drain wiring, and a source / drain electrode that can be a source electrode or a drain electrode;
A transparent electrode electrically connected to the source / drain electrodes;
A TFT substrate comprising:
A first metal film;
A first transparent conductive film;
A second metal film;
A second transparent conductive film;
Having a laminated film laminated in the order of
A TFT substrate, wherein a part or all of the laminated film is all or part of the source electrode or the drain electrode.   4. The TFT substrate according to claim 3, wherein a protective transparent conductive layer is provided on any one of the gate wiring, the source / drain wiring, and the source / drain electrode. Forming a first metal film, a gate insulating film, a first silicon layer, a second silicon layer, a second metal film, and a first resist in this order on the substrate; When,
Forming the first resist into the 1a resist pattern using a halftone exposure technique;
Forming a gate wiring and a gate electrode using the first resist formed in the first resist pattern;
Re-forming the first resist into a 1b resist pattern;
Removing the second metal film on the gate wiring and the gate electrode and the second silicon layer by using the first resist of the 1b resist pattern, and forming a channel; ,
Forming an interlayer insulating film and a second resist in this order on the substrate;
Forming the second resist into a second resist pattern;
Forming a gate wiring pad portion using the second resist of the second resist pattern, and further forming a through hole in the interlayer insulating film;
Forming a transparent conductive film, an auxiliary conductive layer, an insulating film, and a third resist in this order on the interlayer insulating film;
Using the third mask to form the third resist into the 3a resist pattern by a halftone exposure technique;
Using the third resist of the 3a resist pattern, a region where the source / drain wiring is located, a region where the source / drain electrode is located, the pixel electrode portion, the gate wiring pad portion, And etching the insulating film, the auxiliary conductive layer, and the transparent conductive film in a region that is not covered by the third resist,
Re-forming the third resist into a 3b resist pattern;
Using the third resist of the 3b resist pattern, the insulating film of the pixel electrode portion and the auxiliary conductive layer are etched to form a transparent pixel electrode, source / drain wiring pads, and gate wiring. Forming a pad;
A method for manufacturing a TFT substrate, comprising: On the substrate, a first metal film, a first transparent conductive layer for protecting the metal film, a gate insulating film, a first silicon layer, a second silicon layer, a second metal film, A step of depositing the transparent conductive layer for protecting the metal film and the first resist in this order;
Forming the first resist into the 1a resist pattern using a halftone exposure technique;
Forming a gate wiring and a gate electrode using the first resist formed in the pattern of the 1a;
Re-forming the first resist into a 1b resist pattern;
Removing the second metal film on the gate wiring and the gate electrode and the second silicon layer by using the first resist of the 1b resist pattern, and forming a channel; ,
Forming an interlayer insulating film and a second resist in this order on the substrate;
Forming the second resist into a second resist pattern by an exposure technique using a second mask;
Forming a gate wiring pad portion using the second resist of the second resist pattern, and further forming a through hole in the interlayer insulating film;
Forming a transparent conductive film, an auxiliary conductive layer, an insulating film, and a third resist in this order on the interlayer insulating film;
Using the third mask to form the third resist into the 3a resist pattern by a halftone exposure technique;
The third resist of the 3a resist pattern is used to cover the source / drain wiring, the source / drain electrode, the pixel electrode portion, and the gate wiring pad portion, and Etching the insulating film, the auxiliary conductive layer, and the transparent conductive film in a region not covered with a resist;
Re-forming the third resist into a 3b resist pattern;
Using the third resist of the 3b resist pattern, the gate wiring pad, the source / drain wiring pad, the insulating film of the pixel electrode portion, and the auxiliary conductive layer are etched and transparent Forming a pixel electrode, a source / drain wiring pad, and a gate wiring pad;
A method for manufacturing a TFT substrate, comprising: A gate wiring metal film and a gate insulating film;
A first silicon layer and a second silicon layer;
A plurality of source / drain wirings and source / drain electrodes;
A pixel electrode electrically connected to the source / drain electrode;
Further comprising
The first silicon layer;
The second silicon layer;
A third metal film;
An interlayer insulating film;
A transparent electrode layer connected to the third metal film through a through hole of the interlayer insulating film;
A metal layer;
Including a laminate formed by laminating in this order,
Part or all of the laminate is part or all of the source / drain electrodes,
Further, the first silicon layer is a part or all of the source / drain wiring,
The TFT array substrate, wherein the first silicon layer of any one of the source / drain wirings is electrically insulated from the first silicon layer of another source / drain wiring. A gate wiring metal film and a gate insulating film;
A first silicon layer and a second silicon layer;
A plurality of source / drain wirings and source / drain electrodes;
A pixel electrode electrically connected to the source / drain electrode;
Further comprising
The first silicon layer;
The second silicon layer;
A third metal layer;
An interlayer insulating film;
A transparent electrode layer connected to the third metal film through a through hole of the interlayer insulating film;
A metal layer;
Including a first laminated body formed by laminating in this order,
All or part of the first stacked body is part or all of the source / drain electrode part,
The first silicon layer of any one of the source / drain wirings is electrically insulated from the first silicon layer of the other source / drain wirings;
The gate wiring metal film;
A transparent electrode layer connected to the source / drain wiring through a through hole opened in the gate insulating film and a through hole opened in the first silicon layer;
Having a second laminated body laminated in this order,
A TFT array substrate, wherein all or part of the second stacked body is all or part of a gate wiring pad. A gate wiring metal film and a gate insulating film;
A first silicon layer and a second silicon layer;
A plurality of source / drain wirings and source / drain electrodes;
A pixel electrode electrically connected to the source / drain electrode;
Further comprising
The first silicon layer;
The second silicon layer;
A third metal layer;
An interlayer insulating film;
A transparent conductive layer connected to the third metal layer through a through hole in the interlayer insulating film;
A metal layer;
A transparent conductive layer;
Including a first laminated body formed by laminating in this order,
All or part of the first stacked body is all or part of the source / drain electrode part,
A first silicon layer of any one of the source / drain wirings is electrically insulated from the first silicon layer of the other source / drain wirings;
The third metal layer;
A transparent conductive film;
A metal layer;
The transparent conductive film;
A second laminated body laminated in this order,
A TFT array substrate, wherein all or part of at least one of the source / drain electrodes is all or part of the second stacked body.   The TFT array substrate according to claim 7, wherein a transparent conductive layer for protecting a metal thin film is provided on the metal film.   The TFT array substrate according to any one of claims 7 to 9, wherein a third metal layer protecting transparent conductive layer is provided on the third metal layer.   10. The TFT array substrate according to claim 7, wherein a transparent conductive layer for protecting the metal layer is provided on the metal layer. Forming a gate wiring metal film, a gate insulating film, a first silicon layer, a second silicon layer, a third metal film, and a first resist on the substrate in this order; ,
Using the first mask and using the halftone exposure technique to form the first resist in the resist pattern 1a;
Etching the gate wiring metal film using the first resist formed in the resist pattern of 1a, and forming the gate wiring metal film to be a gate wiring and a gate electrode;
Re-forming the first resist into a resist pattern 1b;
A step of forming a channel by removing the third metal film and the second silicon layer on the gate wiring and the gate electrode using the first resist formed in the first b resist pattern. When,
The substrate including the gate wiring, the gate electrode, and the gate insulating film, wherein the second silicon layer on the gate electrode and the gate insulating film, the first silicon layer, Forming an interlayer insulating film and a second resist in this order on the substrate having the source / drain electrodes made of the third metal film;
Using the second mask and forming the desired second resist pattern on the second resist using a halftone exposure technique;
Forming a through hole in a gate wiring pad portion, which is a region where a gate wiring pad is provided, using the second resist formed in the second a resist pattern;
Re-forming the second resist of the 2a resist pattern into a 2b resist pattern;
Using the second resist formed in the second b resist pattern, forming a through hole in the interlayer insulating film of the source / drain electrode portion which is a region where the source / drain electrode is provided;
Etching and removing the first silicon layer between the source and drain wirings;
Forming a transparent conductive film, a metal layer, an insulating film, and a third resist in this order;
Using a third mask and forming a third resist pattern on the third resist using a halftone exposure technique;
Using the third resist formed in the 3a resist pattern, the source / drain wiring, the source / drain electrode, a pixel electrode portion in which the pixel electrode is located, and the gate wiring Etching and removing the insulating film, the metal layer, and the transparent conductive film except for a pad portion;
Re-forming the third mask into a 3b resist pattern;
Using the third mask formed in the 3b resist pattern, the insulating film and the metal located in the gate wiring pad part, the source / drain wiring pad part, and the pixel electrode part Etching and removing the layer;
A method for producing a TFT array substrate, comprising: On the substrate, a gate wiring metal film, a transparent conductive layer for protecting the metal film, a gate insulating film, a first silicon layer, a second silicon layer, a third metal film, and a third metal film Forming a protective transparent conductive layer and a first resist in this order;
Using the first mask and using the halftone exposure technique to form the first resist in the resist pattern 1a;
Etching the gate wiring metal film using the first resist formed in the resist pattern of 1a, and forming the gate wiring metal film to be a gate wiring and a gate electrode;
Re-forming the first resist into a resist pattern 1b;
Using the first resist formed in the resist pattern of 1b, the third metal film protective transparent conductive layer on the gate wiring and the gate electrode, the third metal film, Removing the second silicon layer to form a channel;
The substrate including the gate wiring, the gate electrode, and the gate insulating film, wherein the second silicon layer on the gate electrode and the gate insulating film, the first silicon layer, An interlayer insulating film and a second resist are formed in this order on the substrate having a source / drain electrode composed of a third metal film and the third metal film protecting transparent conductive layer. Process,
Using the second mask and forming the desired second resist pattern on the second resist using a halftone exposure technique;
Forming a through hole in a gate wiring pad portion, which is a region where a gate wiring pad is provided, using the second resist formed in the second a resist pattern;
Re-forming the second resist of the 2a resist pattern into a 2b resist pattern;
Using the second resist formed in the 2a resist pattern, forming a through hole in the interlayer insulating film of the source / drain electrode portion which is a region where the source / drain electrode is provided;
Etching and removing the first silicon layer between the source and drain wirings;
Forming a transparent conductive film, a metal layer, a transparent conductive layer for protecting the metal layer, an insulating film, and a third resist in this order;
Using the third mask and forming the third resist in the 3a resist pattern using a halftone exposure technique;
Using the third resist formed in the 3a resist pattern, the source / drain wiring, the source / drain electrode, a pixel electrode portion in which the pixel electrode is located, and the gate wiring Etching and removing the insulating film, the metal layer protecting transparent conductive layer, the metal layer, and the transparent conductive film, except for the pad portion;
After the third resist is re-formed into a 3b resist pattern, the gate wiring pad portion and the source / drain wiring pad portion are formed using the third resist formed in the 3b resist pattern. Etching and removing the insulating film located in the pixel electrode portion, the transparent conductive layer for protecting the metal layer, and the metal layer;
A method for producing a TFT array substrate, comprising: The transparent conductive film is
Indium oxide;
One or more metal oxides selected from a first metal oxide group consisting of zinc oxide and tin oxide and germanium oxide and zirconium oxide and tungsten oxide and molybdenum oxide and lanthanoid oxide elements;
The TFT substrate or TFT array substrate according to any one of claims 1 to 4, or 7 to 9.   The TFT substrate or TFT array substrate according to claim 15, wherein the content of the metal oxide added to the indium oxide in the transparent conductive film is 1 to 20 wt% with respect to indium oxide. The transparent conductive layer for protecting the metal film and the transparent conductive layer for protecting the barrier metal film are:
Indium oxide;
One or more metal oxides selected from a second metal oxide group consisting of zinc oxide and tin oxide and tungsten oxide and cerium oxide and lanthanoid oxides;
Including
13. The composition ratio of indium oxide, zinc oxide, tin oxide, tungsten oxide, and cerium oxide in the transparent conductive film is 1 to 20 wt% with respect to indium oxide. The TFT substrate or TFT array substrate according to any one of the above. The transparent conductive film is
Indium oxide;
One or more metal oxides selected from the first metal oxide group consisting of tin oxide, germanium oxide, zirconium oxide, tungsten oxide, molybdenum oxide and lanthanoid oxide elements;
15. The method for manufacturing a TFT substrate or a TFT array substrate according to claim 5, wherein the TFT substrate or the TFT array substrate is included.   The method for manufacturing a TFT substrate or a TFT array substrate according to claim 18, wherein the content of the metal oxide added to the indium oxide in the transparent conductive film is 1 to 20 wt% with respect to indium oxide. . The first transparent conductive layer for protecting a metal film and the second transparent conductive layer for protecting a metal film are:
Indium oxide;
One or more metal oxides selected from a second metal oxide group consisting of zinc oxide and tin oxide and tungsten oxide and cerium oxide and lanthanoid oxides;
Including
The composition ratio of indium oxide, zinc oxide, tin oxide, tungsten oxide, and cerium oxide in the transparent conductive film is 1 to 20 wt% with respect to indium oxide, according to claim 5, 6, 13, or 14. The manufacturing method of the TFT substrate or TFT array substrate in any one.

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