JP2007258675A - Tft substrate, reflective tft substrate, and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a TFT substrate, a reflective TFT substrate, and a method of manufacturing the same which can enable stable operations for an extended period of time, prevent crosstalk, and remarkably reduce the manufacturing cost by reducing the number of steps in a manufacturing process. <P>SOLUTION: A reflective TFT substrate 1a comprises a glass substrate 10, a gate electrode 23 and gate wiring 24 which are insulated by a gate insulating film 30 covering the top surfaces of the gate electrode 23 and the gate wiring 24 and an interlayer insulating film 50 covering the sides of the gate electrode 23 and the gate wiring 24, an n-type oxide semiconductor layer 40 formed on the gate insulating film 30 on the gate electrode 23, a reflective metal layer 60a formed on the n-type oxide semiconductor layer 40 via a channel portion 44, and a channel guard 500 for protecting the channel portion 44. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a TFT substrate, a reflective TFT substrate, and a method for manufacturing the same, and more particularly, a gate electrode and a gate wiring insulated by a gate insulating film and an interlayer insulating film, and an activity of a TFT (thin film transistor) formed on the gate electrode. By providing an n-type oxide semiconductor layer as a layer, a channel guard made of an interlayer insulating film formed on the channel portion, and a drain electrode and a source electrode formed in a pair of openings of the interlayer insulating film, TFT substrate and reflection that can operate stably over a long period of time, can reduce the manufacturing cost by reducing the manufacturing cost, and can eliminate the concern that the gate wirings interfere with each other (crosstalk). The present invention relates to a type TFT substrate and a manufacturing method thereof.

  LCDs (liquid crystal display devices) and organic EL display devices are widely used for reasons such as display performance and energy saving. In particular, it has become almost mainstream as a display device for mobile phones, PDAs (personal personal digital assistants), personal computers, laptop computers, televisions, and the like. In these display devices, a TFT substrate (including a reflective TFT substrate) is generally used.

  For example, a liquid crystal display device is configured to fill a display material such as liquid crystal between a TFT substrate and a counter substrate, and to selectively apply a voltage to the display material for each pixel. Here, the TFT substrate refers to a substrate on which a TFT (thin film transistor) made of a semiconductor thin film (also referred to as a semiconductor film) is disposed. In general, a TFT substrate is also called a “TFT array substrate” because TFTs are arranged in an array.

  Note that in a TFT substrate used for a liquid crystal display device or the like, a set of TFTs and one pixel of a screen of the liquid crystal display device (this is called one unit) is arranged vertically and horizontally on a glass substrate. In the TFT substrate, gate wirings are arranged at regular intervals in the vertical direction on a glass substrate, and source wirings or drain wirings are arranged at regular intervals in the horizontal direction. Further, a gate electrode, a source electrode, and a drain electrode are provided in each of the units constituting each pixel.

<Conventional manufacturing method of TFT substrate>
As a manufacturing method of this TFT substrate, there are generally known a five-mask process using five masks, a four-mask process in which the number of masks is reduced to four using a halftone exposure technique, and the like. .
By the way, since such a TFT substrate manufacturing method uses five or four masks, the manufacturing process tends to have a large number of steps. For example, even in the case of a four-mask process, it is known that a process exceeding 35 steps (processes) and in the case of a five-mask process requires more than 40 steps (processes). If the number of processes increases in this way, the manufacturing yield may be reduced. In addition, if the number of processes is large, the process tends to be complicated, and the manufacturing cost may increase.

(Manufacturing method using five masks)
FIGS. 29A and 29B are schematic views for explaining a conventional TFT substrate manufacturing method, in which FIG. 29A is a cross-sectional view in which a gate electrode is formed, and FIG. 29B is a cross-sectional view in which an etch stopper is formed. (C) is a sectional view in which a source electrode and a drain electrode are formed, (d) is a sectional view in which an interlayer insulating film is formed, and (e) is a sectional view in which a transparent electrode is formed.
In FIG. 2A, a gate electrode 212 is formed on a glass substrate 210 using a first mask (not shown). That is, first, a metal (for example, Al (aluminum) or the like) is deposited on the glass substrate 210 by sputtering, and then a resist is formed by a photolithography method using a first mask and etched into a desired shape. Thus, the gate electrode 212 is formed and the resist is ashed.

  Next, as shown in FIG. 2B, a gate insulating film 213 to be a SiN film (silicon nitride film) and an α-Si: H (i) film 214 are formed on the glass substrate 210 and the gate electrode 212. Laminate in order. Subsequently, a SiN film (silicon nitride film) serving as a channel protective layer is deposited, and a resist is formed by photolithography using a second mask (not shown), and the SiN film is formed using CHF gas. Dry etching is performed into a desired shape, an etch stopper 215 is formed, and the resist is ashed.

Next, as shown in FIG. 3C, an α-Si: H (n) film 216 is deposited on the α-Si: H (i) film 214 and the etch stopper 215, and further, Cr is formed thereon. A / Al bilayer film is deposited by vacuum evaporation or sputtering. Subsequently, a resist is formed by photolithography using a third mask (not shown), and the Cr (chromium) / Al bilayer film is etched to form a source electrode 217a and a drain electrode 217b having desired shapes. To do. This etching is performed by photoetching using H ₃ PO ₄ —CH ₃ COOH—HNO ₃ for Al, and by photoetching using an aqueous solution of ceric ammonium nitrate for Cr. Done. Further, the α-Si: H film (216 and 214) is etched by using both dry etching using CHF gas and wet etching using a hydrazine aqueous solution (NH ₂ NH ₂ .H ₂ O). The α-Si: H (n) film 216 and the α-Si: H (i) film 214 are formed, and the resist is ashed.

  Next, as shown in FIG. 4D, before forming the transparent electrode 219, an interlayer insulating film 218 is deposited on the gate insulating film 213, the etch stopper 215, the source electrode 217a and the drain electrode 217b. Subsequently, a resist is formed by photolithography using a fourth mask (not shown), the interlayer insulating film 218 is etched, and the source electrode 217a is electrically connected to the transparent electrode 219 described below. The opening 218a is formed and the resist is ashed.

Next, as shown in FIG. 4E, the amorphous transparent conductive material mainly composed of indium oxide and zinc oxide is formed on the interlayer insulating film 218 in the region where the pattern of the source electrode 217a and the drain electrode 217b is formed. A film is deposited by sputtering. Subsequently, a resist is formed by photolithography using a fifth mask (not shown), photo-etching is performed using an amorphous transparent conductive film as an etchant with an aqueous solution of 4% by weight of oxalic acid, and the source electrode 217a. And patterning into a shape that is electrically connected to the resist, and ashing the resist. Thereby, the transparent electrode 219 is formed.
Thus, according to the manufacturing method of the TFT substrate according to this conventional example, five masks are required.

(Manufacturing method using three masks)
As a technique for improving the conventional technique, various techniques for manufacturing a TFT substrate by a method in which the number of masks is reduced (for example, from 5 to 3) and the manufacturing process is further reduced have been proposed. For example, Patent Documents 1 to 7 listed below describe a method for manufacturing a TFT substrate using three masks.
Japanese Patent Laid-Open No. 2004-317685 JP 2004-319655 A JP-A-2005-017669 JP 2005-019664 A JP 2005-049667 A JP 2005-106881 A JP 2005-108912 A

However, the method of manufacturing a TFT substrate using the three masks described in Patent Documents 1 to 7 is a very complicated manufacturing process such that an anodizing step for a gate insulating film is added, and is practical. There is a problem that it is a technology that is difficult to provide.
Moreover, in an actual TFT substrate (including a reflective TFT substrate) production line, quality (for example, avoiding problems such as long-term operation stability and interference between gate wirings (crosstalk)) is high. There has been a demand for a practical technique that is important and can improve quality and productivity.
Furthermore, it has been desired to improve the quality and productivity of a reflective TFT substrate.

  The present invention has been made in view of such problems, and can be stably operated over a long period of time by a channel guard and can prevent crosstalk, and can reduce manufacturing costs by reducing the number of manufacturing steps. An object of the present invention is to propose a TFT substrate, a reflective TFT substrate, and a method for manufacturing them, which can greatly reduce the thickness of the substrate.

In order to achieve the above object, a TFT substrate of the present invention includes a substrate, a gate electrode and a gate wiring formed above the substrate, a gate insulating film formed above the gate electrode and the gate wiring, The oxide layer formed above the gate electrode and above the gate insulating film, the side of the gate electrode and the gate wiring, and the top and side of the oxide layer. Further, an interlayer insulating film in which an opening for a source electrode and an opening for a drain electrode are respectively formed at a position separated by a channel portion of the oxide layer, and a source electrode formed in the opening for the source electrode And a drain electrode formed in the drain electrode opening.
In this case, the oxide layer serving as the channel portion is protected by the interlayer insulating film, so that it can operate stably over a long period of time. In addition, since the channel portion, the drain electrode, and the source electrode are reliably and easily manufactured, the yield can be improved and the manufacturing cost can be reduced. Note that the interlayer insulating film above the oxide layer protects the channel portion and is also referred to as a channel guard.

In the TFT substrate of the present invention, the source electrode and the drain electrode are made of the same conductor layer, and the conductor layer is made of metal.
In this way, it is possible to provide a reflective TFT substrate that can operate stably over a long period of time, can improve the yield, and can reduce the manufacturing cost.

In the TFT substrate of the present invention, the source electrode and the drain electrode are made of the same conductor layer, and the conductor layer also serves as at least a pixel electrode.
If it does in this way, the number of masks used at the time of manufacturing can be reduced, and a manufacturing process can be reduced, thereby improving production efficiency and reducing the cost of manufacturing. In general, the conductor layer has a structure that also serves as a source wiring, a drain wiring, a source electrode, a drain electrode, and a pixel electrode. In this way, the source wiring, the drain wiring, the source electrode, the drain electrode, and the pixel electrode are made efficient. Can be manufactured well.
Note that “the conductor layer also serves as at least the pixel electrode” means that the formed conductor layer has at least a function as a pixel electrode.

In the TFT substrate of the present invention, the oxide layer is an n-type oxide semiconductor layer.
As described above, by using an oxide semiconductor layer as an active layer of a TFT, the oxide semiconductor layer is stable even when a current flows, and is useful for an organic electroluminescence device that operates by current control.

In the TFT substrate of the present invention, the oxide layer is formed at predetermined positions corresponding to the channel portion, the source electrode, and the drain electrode.
In this way, since the oxide layer is usually formed only at a predetermined position, it is possible to eliminate the concern that the gate wirings interfere with each other (crosstalk).

In the TFT substrate of the present invention, the upper portion of the substrate is covered with a protective insulating film, and the protective insulating film has openings at positions corresponding to the pixel electrodes, source / drain wiring pads, and gate wiring pads. It is set as the structure which has.
In this case, since the TFT substrate itself has a structure including a protective insulating film, it is possible to provide a TFT substrate capable of easily manufacturing display means and light emitting means using liquid crystal or organic EL material.
The source / drain wiring pads refer to source wiring pads or drain wiring pads.

In order to achieve the above object, a reflective TFT substrate of the present invention is formed by forming a substrate and an upper surface of the substrate, the upper surface is covered with a gate insulating film, and the side surfaces are covered with an interlayer insulating film. Gate electrode and gate wiring, an oxide layer formed above the gate insulating film above the gate electrode, and a reflective metal layer formed above the oxide layer and separated by a channel portion And a channel guard formed above the channel portion and protecting the channel portion.
In this case, since the oxide layer serving as the channel portion is protected by the channel guard, it can operate stably over a long period of time.

In the reflective TFT substrate of the present invention, the channel guard is made of the interlayer insulating film, and a drain electrode and a source electrode are formed in a pair of openings of the interlayer insulating film, respectively.
In this way, the channel part, the drain electrode, and the source electrode are reliably and easily manufactured, so that the yield can be improved and the manufacturing cost can be reduced.

In the reflective TFT substrate of the present invention, the reflective metal layer also serves as at least a pixel electrode.
If it does in this way, the number of masks used at the time of manufacturing can be reduced, and a manufacturing process can be reduced, thereby improving production efficiency and reducing the cost of manufacturing. In addition, the reflective metal layer usually has a structure that also serves as a source wiring, a drain wiring, a source electrode, a drain electrode, and a pixel electrode, and in this way, the source wiring, the drain wiring, the source electrode, the drain electrode, and the pixel electrode are made efficient. Can be manufactured well.
Note that “the reflective metal layer also serves as at least the pixel electrode” means that the formed reflective metal layer has at least a function as a pixel electrode.

In the reflective TFT substrate of the present invention, the oxide layer is an n-type oxide semiconductor layer.
As described above, by using an oxide semiconductor layer as an active layer of a TFT, the oxide semiconductor layer is stable even when a current flows, and is useful for an organic electroluminescence device that operates by current control.

In the reflective TFT substrate of the present invention, the oxide layer is formed at predetermined positions corresponding to the channel portion, the source electrode, and the drain electrode.
In this way, since the oxide layer is usually formed only at a predetermined position, it is possible to eliminate the concern that the gate wirings interfere with each other (crosstalk).

In the reflective TFT substrate of the present invention, the upper portion of the substrate is covered with a protective insulating film, and the protective insulating film is located at a position corresponding to the pixel electrode, the source / drain wiring pad, and the gate wiring pad. The configuration has an opening.
In this case, since the reflective TFT substrate itself has a structure including a protective insulating film, a reflective TFT substrate capable of easily manufacturing display means and light emitting means using liquid crystal or organic EL material is provided. be able to.

The reflective TFT substrate of the present invention is a metal layer protecting oxide transparent conductor layer, wherein the reflective TFT substrate includes a reflective metal layer and / or a metal thin film, and protects the reflective metal layer and / or the metal thin film. It is set as the structure which has.
If it does in this way, while being able to prevent corrosion of a reflective metal layer and / or a metal thin film, durability can be improved. For example, when a metal thin film is used as the gate wiring, the metal surface can be prevented from being exposed when the opening for the gate wiring pad is formed, and the connection reliability can be improved. Further, for the reflective metal layer, discoloration of the reflective metal layer can be prevented, and problems such as a decrease in the reflectance of the reflective metal layer can be prevented. Furthermore, since it is transparent, the amount of light transmission does not decrease, and a display device with excellent luminance can be provided.

In the reflective TFT substrate of the present invention, the energy gap of the oxide layer is 3.0 eV or more.
In this way, by setting the energy gap to 3.0 eV or more, malfunction due to light can be prevented. In general, the energy gap may be 3.0 eV or more, preferably 3.2 eV or more, and more preferably 3.4 eV or more. Thus, by increasing the energy gap, malfunction due to light can be prevented more reliably.

In the reflective TFT substrate of the present invention, the reflective metal layer is composed of a thin film made of aluminum, silver or gold, or an alloy layer containing aluminum, silver or gold.
If it does in this way, more light can be reflected and the brightness | luminance by reflected light can be improved.

In order to achieve the above object, a method for manufacturing a TFT substrate according to the present invention includes a gate electrode and a thin film for wiring that becomes a gate wiring, a gate insulating film, an oxide layer, A step of laminating one resist, a step of forming the first resist into a predetermined shape by halftone exposure using a first halftone mask, the gate electrode / wiring thin film, a gate insulating film, Etching the oxide layer to form the gate electrode and gate wiring; re-forming the first resist into a predetermined shape; and etching the oxide layer to form a channel portion. Etching the interlayer insulating film, a step of laminating the interlayer insulating film and the second resist, a step of forming the second resist into a predetermined shape using a second mask, and Forming a source electrode opening and a drain electrode opening in a portion to be a source electrode and a drain electrode, and etching the interlayer insulating film and a gate insulating film to form a gate wiring pad portion in a portion to be a gate wiring pad; A step of forming an opening, a step of laminating a conductor layer and a third resist, a step of forming the third resist into a predetermined shape using a third mask, and the conductor layer. Etching to form a source electrode, a drain electrode, a source wiring, a drain wiring, a pixel electrode, and a gate wiring pad.
As described above, the present invention is also effective as a method for manufacturing a TFT substrate. By using three masks, a VIA hole channel TFT substrate can be manufactured, and the number of masks is reduced and the manufacturing process is reduced. As a result, the production efficiency can be improved and the manufacturing cost can be reduced. In addition, a channel guard made of an interlayer insulating film having a pair of openings in which a drain electrode and a source electrode are formed is formed on the oxide layer in the channel portion, and the channel guard protects the channel portion. It can be operated stably over a period of time. Further, since the oxide layer is usually formed only at a predetermined position (a predetermined position corresponding to the channel portion, the source electrode and the drain electrode), there is a concern that the gate wirings interfere with each other (crosstalk). Can be eliminated.

In order to achieve the above object, a method for manufacturing a TFT substrate according to the present invention includes a gate electrode and a thin film for wiring that becomes a gate wiring, a gate insulating film, an oxide layer, A step of laminating one resist, a step of forming the first resist into a predetermined shape by halftone exposure using a first halftone mask, the gate electrode / wiring thin film, a gate insulating film, Etching the oxide layer to form the gate electrode and gate wiring; re-forming the first resist into a predetermined shape; and etching the oxide layer to form a channel portion. Etching the interlayer insulating film, a step of laminating the interlayer insulating film and the second resist, a step of forming the second resist into a predetermined shape using a second mask, and Forming a source electrode opening and a drain electrode opening in a portion to be a source electrode and a drain electrode, and etching the interlayer insulating film and the gate insulating film to form a gate wiring pad portion in a portion to be a gate wiring pad; A step of forming an opening, a step of laminating a conductor layer and a third resist, a step of forming the third resist into a predetermined shape using a third mask, and the conductor layer. Etching, forming a source electrode, a drain electrode, a source wiring, a drain wiring, a pixel electrode, and a gate wiring pad; a step of stacking a protective insulating film and a fourth resist; and And the etching of the protective insulating film to expose the source / drain wiring pad, the pixel electrode, and the gate wiring pad. There as a method having a degree.
In this case, the source electrode, the source electrode, the source wiring, and the drain wiring are covered with the protective insulating film so as not to be exposed, and the TFT substrate itself has a protective insulating film. It is possible to provide a TFT substrate capable of easily manufacturing display means and light emitting means using the above.

In order to achieve the above object, a manufacturing method of a reflective TFT substrate according to the present invention includes a gate electrode and a thin film for wiring that becomes a gate wiring, a gate insulating film, an oxide layer, A step of laminating a first resist, a step of forming the first resist into a predetermined shape by halftone exposure using a first halftone mask, and the gate electrode / wiring thin film, gate insulation Etching the film and the oxide layer to form the gate electrode and the gate wiring;
A step of re-forming the first resist into a predetermined shape; a step of etching the oxide layer to form a channel portion; a step of stacking an interlayer insulating film and a second resist; A step of forming the second resist into a predetermined shape using a mask, and etching the interlayer insulating film to form an opening for a source electrode and an opening for a drain electrode in a portion to be a source electrode and a drain electrode Forming and etching the interlayer insulating film and the gate insulating film to form a gate wiring pad opening in a portion to be a gate wiring pad; and laminating a reflective metal layer and a third resist; A step of forming the third resist into a predetermined shape using a third mask, and etching the reflective metal layer to form a source electrode, a drain electrode, a source wiring, and a drain. Down lines, it is a method and a step of forming a pixel electrode and the gate wire pad.
As described above, the present invention is also effective as a method for manufacturing a reflective TFT substrate, and a VIA hole channel type reflective TFT substrate can be manufactured using three masks, thereby reducing the number of masks. By reducing the manufacturing process, the production efficiency can be improved and the manufacturing cost can be reduced. In addition, a channel guard made of an interlayer insulating film having a pair of openings in which a drain electrode and a source electrode are formed is formed on the oxide layer in the channel portion, and the channel guard protects the channel portion. It can be operated stably over a period of time. Further, since the oxide layer is usually formed only at a predetermined position (a predetermined position corresponding to the channel portion, the source electrode and the drain electrode), there is a concern that the gate wirings interfere with each other (crosstalk). Can be eliminated.

In order to achieve the above object, a manufacturing method of a reflective TFT substrate according to the present invention includes a gate electrode and a thin film for wiring that becomes a gate wiring, a gate insulating film, an oxide layer, A step of laminating a first resist, a step of forming the first resist into a predetermined shape by halftone exposure using a first halftone mask, and the gate electrode / wiring thin film, gate insulation Etching the film and the oxide layer to form the gate electrode and the gate wiring;
Re-forming the first resist into a predetermined shape; etching the oxide layer to form a channel portion; laminating an interlayer insulating film and a second resist; A step of forming the second resist into a predetermined shape using a mask, and etching the interlayer insulating film to form a source electrode opening and a drain electrode opening in a portion to be a source electrode and a drain electrode. Forming a gate wiring pad opening in a portion to be a gate wiring pad by etching the interlayer insulating film and the gate insulating film, and forming a reflective metal layer, a protective insulating film, and a third resist. A step of laminating, a step of forming the third resist in a predetermined shape by halftone exposure using a third halftone mask, and the reflective metal layer and protective insulating layer. Etching the film to form a source electrode, a drain electrode, a source wiring, a drain wiring, a pixel electrode, and a gate wiring pad; a step of re-forming the third resist into a predetermined shape; and the protective insulation Etching the film to expose the source / drain wiring pad, the pixel electrode and the gate wiring pad.
In this case, the upper portions of the source electrode, the source electrode, the source wiring, and the drain wiring are covered with the protective insulating film, so that the operational stability can be improved.
The source / drain wiring pads refer to source wiring pads or drain wiring pads.

In order to achieve the above object, a manufacturing method of a reflective TFT substrate according to the present invention includes a gate electrode and a thin film for wiring that becomes a gate wiring, a gate insulating film, an oxide layer, A step of laminating a first resist, a step of forming the first resist into a predetermined shape by halftone exposure using a first halftone mask, and the gate electrode / wiring thin film, gate insulation Etching the film and the oxide layer to form the gate electrode and the gate wiring;
A step of re-forming the first resist into a predetermined shape; a step of etching the oxide layer to form a channel portion; a step of stacking an interlayer insulating film and a second resist; A step of forming the second resist into a predetermined shape using a mask, and etching the interlayer insulating film to form an opening for a source electrode and an opening for a drain electrode in a portion to be a source electrode and a drain electrode Forming and etching the interlayer insulating film and the gate insulating film to form a gate wiring pad opening in a portion to be a gate wiring pad; and laminating a reflective metal layer and a third resist; A step of forming the third resist into a predetermined shape using a third mask, and etching the reflective metal layer to form a source electrode, a drain electrode, a source wiring, and a drain. Down lines, and forming a pixel electrode and the gate wire pad, and laminating a protective insulating film and a fourth resist,
The method includes a step of forming the fourth resist in a predetermined shape and a step of etching the protective insulating film to expose the source / drain wiring pad, the pixel electrode, and the gate wiring pad.
In this case, the source electrode, the source electrode, the source wiring, and the drain wiring are covered with a protective insulating film so as not to be exposed, and the reflective TFT substrate itself has a protective insulating film. A reflective TFT substrate capable of easily manufacturing display means and light emitting means using an EL material or the like can be provided.

Moreover, the manufacturing method of the reflective TFT substrate of the present invention is a method of laminating an oxide conductor layer between the oxide layer and the reflective metal layer.
In this way, the switching speed of the TFT can be increased and the durability of the TFT can be improved.

Moreover, the manufacturing method of the reflective TFT substrate of the present invention is a method of laminating an oxide transparent conductor layer for protecting a metal layer above the reflective metal layer.
If it does in this way, while preventing corrosion of a reflective metal layer, durability can be improved, discoloration of a reflective metal layer, etc. can be prevented, and the malfunction that the reflectance of a reflective metal layer falls can be prevented. Can do.

Also, the reflective TFT substrate manufacturing method of the present invention is a method in which the gate electrode / wiring thin film has a metal layer, and an oxide transparent conductor layer for protecting the metal layer is laminated above the metal layer. is there.
In this case, for example, when a metal layer is used as the gate wiring, the metal surface can be prevented from being exposed when the opening for the gate wiring pad is formed, and the connection reliability can be improved.

  According to the TFT substrate and the reflective TFT substrate and the manufacturing method thereof in the present invention, the VIA hole channel TFT substrate and the reflective TFT substrate can be manufactured using three or four masks. By reducing the number and manufacturing processes, the production efficiency can be improved and the manufacturing cost can be reduced. In addition, a channel guard made of an interlayer insulating film having a pair of openings in which a drain electrode and a source electrode are formed is formed on the oxide layer in the channel portion, and the channel guard protects the channel portion. It can be operated stably over a period of time. Further, since the oxide layer is usually formed only at a predetermined position (a predetermined position corresponding to the channel portion, the source electrode and the drain electrode), there is a concern that the gate wirings interfere with each other (crosstalk). Can be eliminated.

[First Embodiment in Manufacturing Method of TFT Substrate]
FIG. 1 is a schematic flowchart for explaining a method of manufacturing a TFT substrate according to the first embodiment of the present invention. The manufacturing method according to the present embodiment corresponds to claim 16.
In the figure, first, a metal layer 20 as a gate electrode / wiring thin film, an oxide transparent conductor layer 26 for protecting a metal layer, a gate insulating film 30, and an n-type oxide semiconductor layer as an oxide layer are formed on a substrate. 40 and the first resist 41 are laminated in this order, and the first resist 41 is formed into a predetermined shape by the first halftone mask 42 and halftone exposure (step S1).
Next, processing using the first halftone mask 42 will be described with reference to the drawings.

(Process using the first halftone mask)
FIG. 2 is a schematic view for explaining the process using the first halftone mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention, wherein (a) is a metal layer deposition / metal Layer protection oxide transparent conductor layer deposition / gate insulating film deposition / n-type oxide semiconductor layer deposition / first resist coating / halftone exposure / developed cross-sectional view, (b) is the first (C) is a cross-sectional view of the second etching / first resist removed.
In FIG. 1A, first, a translucent glass substrate 10 is prepared.
In addition, the plate-shaped member used as the base material of TFT substrate 1 is not limited to the said glass substrate 10, For example, resin-made plate-shaped members, a sheet-like member, etc. may be sufficient. Moreover, it is not limited to the translucent glass substrate 10, For example, light-shielding property and a semi-transparent glass substrate may be sufficient.

  Next, Al and Mo (molybdenum) are laminated on the glass substrate 10 in this order using a high-frequency sputtering method to have a film thickness of about 250 nm and 50 nm, respectively, and a metal for forming the gate electrode 23 and the gate wiring 24. Layer 20 is formed. That is, the metal layer 20 is composed of an Al thin film layer and a Mo thin film layer (not shown). First, using an Al target, an Al thin film layer is formed under a condition of 100% argon by high frequency sputtering. Form. Subsequently, using a Mo target, a Mo thin film layer is formed by high-frequency sputtering under the condition of 100% argon.

Subsequently, a sputtering target made of indium oxide-zinc oxide (generally called IZO. In ₂ O ₃ : ZnO = 90: 10 wt%) is used on the metal layer 20 with a predetermined oxygen: argon ratio. An oxide transparent conductor layer 26 for protecting a metal layer having a thickness of about 100 nm is formed under the condition of a substrate temperature of about 150 ° C. while maintaining the state (about 1:99 Vol.%). Under this condition, the metal thin film protective oxide conductive layer 26 is obtained as an amorphous film. As described above, the transparent conductive film such as IZO is disposed on the surface of the gate wiring 24 as the oxide transparent conductor layer 26 for protecting the metal layer, because the gate insulating film 30 is opened to form the gate wiring pad 25. This is because the metal surface used for the gate wiring 24 is not exposed when the portion 251 is formed. Accordingly, corrosion of the metal layer 20 can be prevented, durability can be improved, and a highly reliable connection is possible. Therefore, the operational stability of the TFT substrate 1 is improved, and a liquid crystal display device, an electroluminescence device, etc. (not shown) using the TFT substrate 1 operate stably. Further, an insulating material such as SiN _X , SiON _X , or SiO ₂ is used as the gate insulating film 30, and the opening 251 is formed in the gate insulating film 30 by a reactive ion etching method using CHF (CF ₄ , CHF _3, or the like). When a transparent conductive film such as IZO is used as a protective film for the metal layer (Al / Mo layer) 20, damage to the metal layer 20 due to CHF can be reduced.

The oxide conductor layer 26 for protecting the metal layer may be any conductive metal oxide that can be etched simultaneously with a mixed acid (generally also referred to as PAN) that is an etching solution for the Al thin film layer. -It is not limited to zinc oxide. That is, as the composition of indium oxide-zinc oxide, any composition that can be etched simultaneously with Al by PAN can be used, but In / (In + Zn) = 0.5 to 0.95 (weight ratio), preferably 0.7 to 0.9 (weight ratio) is preferable. The reason for this is that if it is less than 0.5 (weight ratio), the durability of the conductive metal oxide itself may be low, and if it exceeds 0.95 (weight ratio), simultaneous etching with Al may be difficult. Because there is a case to do. In the case of etching at the same time as Al, the conductive metal oxide is desirably amorphous. This is because in the case of a crystallized film, simultaneous etching with Al may be difficult.
The thickness of the oxide conductor layer 26 for protecting the metal layer may be 10 to 200 nm. Preferably it is 15-150 nm, More preferably, it is 20-100 nm. This is because if the thickness is less than 10 nm, the effect as a protective film may be small, and if it exceeds 200 nm, it is economically disadvantageous.

  As a material replacing IZO, a material obtained by adding a lanthanoid element to ITO or a material added with a refractory metal oxide such as Mo or W can be used. The addition amount is about 30 atomic% or less, preferably about 1 to 20 atomic%, based on all metal elements. The reason for this is that if it exceeds about 30 atomic%, the etching rate with a mixed acid composed of an aqueous oxalic acid solution, phosphoric acid, acetic acid and nitric acid may decrease. The film thickness is about 20 nm to 500 nm, preferably about 30 nm to 300 nm. The reason is that if it is less than about 20 nm, a pinhole may be formed and it may not be used as a protective film. If it exceeds about 500 nm, it takes time for film formation and etching, and economic loss increases. Because it does.

  Mo on Al is used for the purpose of lowering the contact resistance with the oxide transparent conductor layer 26 for protecting the metal layer. If the contact resistance is low enough not to bother, the Mo layer is formed. It does not have to be. Moreover, Ti (titanium), Cr (chromium), etc. can be used instead of Mo. Also, a metal thin film such as Ag (silver) or Cu (cylinder) or an alloy thin film can be used as the gate wiring 24. In the present embodiment, the Mo thin film layer is formed. In particular, if Mo is used, etching can be performed by the same PAN as the Al thin film layer and the oxide transparent conductor layer 26 for protecting the metal layer. This is preferable because it is possible. The thickness of the metal thin film such as Mo, Ti or Cr may be 10 to 200 nm. Preferably it is 15-100 nm, More preferably, it is 20-50 nm. This is because if the thickness is less than 10 nm, the effect of reducing the contact resistance may be small, and if it exceeds 200 nm, it is economically disadvantageous.

Al may be pure Al (almost 100% purity Al), but metals such as Nd (neodymium), Ce (cerium), Mo, W (tungsten), and Nb (niobium) may be added. Further, Ce, W, Nb and the like are suitable for suppressing the battery reaction with the oxide transparent conductor layer 60, for example. Although the addition amount can be selected as appropriate, it is preferably about 0.1 to 2 wt%.
In the present embodiment, the metal layer 20 and the oxide transparent conductor layer 26 for protecting the metal layer are used as the gate electrode / wiring thin film. However, the present invention is not limited to this. For example, an oxide transparent conductor layer made of indium oxide-tin oxide (In ₂ O ₃ : SnO = about 90:10 wt%) or the like may be used.

Furthermore, the same material as that of the oxide transparent conductor layer 60 described later may be used as the material of the oxide conductor layer 26 for protecting the metal layer. If it does in this way, the kind of material to be used can be reduced and the desired TFT substrate 1 can be obtained suitably. The material of the oxide conductor layer 26 for protecting the metal layer is selected based on etching characteristics, protective film characteristics, and the like.
The metal conductor protecting oxide layer 26 is not limited to being formed on the metal layer 20 as a gate electrode / wiring thin film. For example, although not shown, when an auxiliary conductive layer made of a metal is laminated above the oxide transparent conductor layer 60, it may be formed on the auxiliary conductive layer.

Next, a gate insulating film 30, which is a silicon nitride (SiN _x ) film, is deposited on the metal transparent oxide layer 26 for protecting the metal layer by a glow discharge CVD (chemical vapor deposition) method to a thickness of about 300 nm. In the present embodiment, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used as the discharge gas.

In the present embodiment, a silicon nitride film such as SiN _X is used for the gate insulating film 30, but an oxide insulator can also be used for the insulating film. In this case, a larger dielectric constant of the oxide insulating film is advantageous for the operation of the thin film transistor. Moreover, the one where insulation is high is preferable. As an example that satisfies these requirements, an oxide having an oxide superlattice structure is also a preferable oxide insulating film. Further, an amorphous oxide insulating film can be used. In the case of an amorphous oxide insulating film, the deposition temperature can be maintained at a low temperature, which is advantageous in the case of a substrate having poor heat resistance such as a plastic substrate.
For _{example, ScAlMgO 4, ScAlZnO 4, ScAlCoO} 4, ScAlMnO 4, ScGaZnO 4, ScGaMgO 4, _{or, ScAlZn 3 O 6, ScAlZn 4} O 7, ScAlZn 7 O 10, _{or, ScGaZn 3 O 6, ScGaZn 5} O 8, ScGaZn ₇ O ₁₀ , ScFeZn ₂ O ₅ , ScFeZn ₃ O ₆ , ScFeZn ₆ O ₉ or the like can also be used.
In addition, oxides such as alumina oxide, titanium oxide, hafnium oxide, and lanthanoid oxide, and composite oxides having a superlattice structure can be used.

Next, an indium oxide-zinc oxide (In ₂ O ₃ : ZnO = about 97: 3 wt%) target is used on the gate insulating film 30 to obtain a predetermined oxygen: argon ratio (about 10:90 Vol.%) State. The n-type oxide semiconductor layer 40 having a film thickness of about 150 nm is formed under the condition that the substrate temperature is about 150 ° C. while maintaining. Under this condition, the n-type oxide semiconductor layer 40 is obtained as an amorphous film. Note that the n-type oxide semiconductor layer 40 is obtained as an amorphous film when formed at a low temperature of about 200 ° C. or lower, and is obtained as a crystalline film when formed at a high temperature exceeding 200 ° C. The amorphous film can also be crystallized by heat treatment. In this embodiment, the n-type oxide semiconductor layer 40 is formed as an amorphous film and then crystallized for use.
The n-type oxide semiconductor layer 40 is not limited to the oxide semiconductor layer made of indium oxide-zinc oxide. For example, an indium oxide-gallium oxide-zinc oxide system, indium oxide-samarium oxide, An oxide semiconductor layer made of zinc oxide-magnesium oxide or the like may be used.

Further, the indium oxide-zinc oxide thin film had a carrier density of 10 ⁺¹⁶ cm ⁻³ or less, and was a region that sufficiently operated as a semiconductor. The hole mobility was 25 cm ² / V · sec. Usually, if the carrier density is less than about 10 ⁺¹⁷ cm ⁻³ , the n-type oxide semiconductor layer 40 is sufficiently active region and the mobility is more than 10 times that of amorphous silicon. Is a sufficiently useful semiconductor thin film.

  The n-type oxide semiconductor layer 40 needs to be transparent, and therefore an oxide having an energy gap of 3.0 eV or more is preferably used. Preferably it is 3.2 eV or more, More preferably, it is 3.4 eV or more. The energy gap of the n-type oxide semiconductor layer made of indium oxide-zinc oxide system, indium oxide-gallium oxide-zinc oxide system, indium oxide-samarium oxide, zinc oxide-magnesium oxide, etc. is 3.2 eV or more. Yes, it is preferably used. In addition, when these thin films (n-type oxide semiconductor layers) are amorphous, they can be dissolved in an aqueous oxalic acid solution or a mixed acid composed of phosphoric acid, acetic acid, and nitric acid (appropriately abbreviated as mixed acid). By making it crystallize, it becomes insoluble in oxalic acid aqueous solution or mixed acid and becomes resistant. The crystallization temperature can be controlled by the amount of zinc oxide added.

  Next, as shown in FIG. 6A, a first resist 41 is applied on the n-type oxide semiconductor layer 40, and the first resist 41 is obtained by first halftone mask 42 and halftone exposure. Are formed in a predetermined shape (step S1). That is, the first resist 41 covers the gate electrode 23 and the gate wiring 24, and the halftone mask portion 421 forms a portion covering the gate wiring 24 in a shape thinner than other portions.

Next, as shown in FIG. 4B, as the first etching, first, the n-type oxide semiconductor layer 40 is etched with the first resist 41 and an etching solution (aqueous oxalic acid solution). The gate insulating film 30 is dry-etched using one resist 31 and an etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)), and further, the metal layer is protected by the first resist 41 and an etching solution (mixed acid). The oxide transparent conductor layer 26 and the metal layer 20 are etched to form the gate electrode 23 and the gate wiring 24 (step S2).
Subsequently, the first resist 41 is ashed so that the n-type oxide semiconductor layer 40 above the gate wiring 24 is exposed and the n-type oxide semiconductor layer 40 above the gate electrode 23 is covered. Then, the first resist 41 is re-formed (step S3).

Next, as shown in FIG. 2C, the n-type oxide on the exposed gate wiring 24 is used as the second etching by using the re-formed first resist 41 and the etching solution (oxalic acid aqueous solution). The semiconductor layer 40 is removed by etching to form a channel portion 44 made of the n-type oxide semiconductor layer 40 (step S4).
Subsequently, when the re-formed first resist 41 is ashed, as shown in FIG. 3, the gate insulating film 30 and the gate insulating film 30 stacked on the gate wiring 24 on the glass substrate 10. The channel part 44 formed through the 30 is exposed. The gate electrode 23 and the channel part 44 shown in FIG. 2C show the AA cross section in FIG. 3, and the gate wiring 24 shows the BB cross section.

As described above, by using the n-type oxide semiconductor layer 40 as the active layer of the TFT, it is stable even when a current flows, and is useful for an organic electroluminescence device that operates by current control.
In the present invention, since the n-type oxide semiconductor layer 40 is formed only at predetermined positions corresponding to the channel portion 44, the source electrode 63, and the drain electrode 64, the gate wiring 24 interferes (cross). Talk) can be eliminated.

Next, as shown in FIG. 1, an interlayer insulating film 50 and a second resist 51 are stacked in this order on the glass substrate 10, the gate insulating film 30, and the n-type oxide semiconductor layer 40, and a second mask 52 is formed. Is used to form the second resist 51 in a predetermined shape (step S5).
Next, processing using the second mask 52 will be described with reference to the drawings.

(Process using the second mask)
FIG. 4 is a schematic view for explaining a process using the second mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention, and FIG. (B) shows a third etched cross-sectional view, and (c) shows a cross-sectional view after the second resist is peeled off.
In FIG. 2A, first, an interlayer that is a silicon nitride (SiN _x ) film is formed on the exposed glass substrate 10, gate insulating film 30, and n-type oxide semiconductor layer 40 by glow discharge CVD (chemical vapor deposition). An insulating film 50 is deposited to a thickness of about 200 nm. In the present embodiment, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used as the discharge gas.

  Next, as shown in FIG. 5A, a second resist 51 is applied on the interlayer insulating film 50, and the second resist 51 is formed into a predetermined shape using the second mask 52. (Step S5). That is, the second resist 51 is formed on the interlayer insulating film 50 except for portions corresponding to the source electrode 63 and the drain electrode 64 to be formed in a later process and above the gate wiring pad portion 250. The gate wiring 24 and the gate electrode 23 are insulated by having the upper surface covered with the gate insulating film 30 and the side surfaces covered with the interlayer insulating film 50.

Subsequently, using the second resist 51 and an etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)), a portion of the interlayer insulating film 50 corresponding to the source electrode 63 and the drain electrode 64, and a gate wiring pad portion The gate insulating film 30 and the interlayer insulating film 50 above 250 are etched to form a pair of openings 631 and 641 for the source electrode 63 and drain electrode 64 and an opening 251 for the gate wiring pad 25 (step). S6). At this time, since the etching rate of the n-type oxide semiconductor layer 40 in CHF is extremely low, the n-type oxide semiconductor layer 40 is not damaged. Further, since the channel portion 44 is protected by the channel guard 500 made of the interlayer insulating film 50 formed on the channel portion 44, the operational stability of the TFT substrate 1 can be improved.

Next, when the second resist 51 is ashed, as shown in FIG. 5C, the interlayer insulating film 50, the n-type oxide semiconductor layer 40, and the oxide transparent conductive film for protecting the metal layer are formed above the glass substrate 10. The body layer 26 is exposed (see FIG. 5). The n-type oxide semiconductor layer 40 is exposed through the openings 631 and 641, and the metal layer protecting oxide transparent conductor layer 26 is exposed through the opening 251. 4C, the gate electrode 23, the channel portion 44, and the openings 631, 641 show the CC cross section in FIG. 5, and the gate wiring pad portion 250 and the opening 251 have the DD cross section. Is shown.
The shape and size of the openings 631, 641, 251 are not particularly limited.

Next, as shown in FIG. 1, an oxide transparent conductor layer 60 as a conductor layer and a third resist 61 are laminated in this order above the glass substrate 10 on which the openings 631, 641, and 251 are formed. Then, the third resist 61 is formed in a predetermined shape using the third mask 62 (step S7).
In this embodiment, the oxide transparent conductor layer 60 is used as the conductor layer. However, the present invention is not limited to this. For example, a conductive metal layer, a semi-transparent or non-transparent layer is used. An oxide conductor layer or the like may be used. For example, the conductor layer may be made of a metal. In this way, the conductor layer can operate stably over a long period of time, and the yield can be improved and the manufacturing cost can be reduced. A reflective TFT substrate can be provided.
Next, processing using the third mask 62 will be described with reference to the drawings.

(Process using third mask)
FIG. 6 is a schematic view for explaining a process using a third mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention, and (a) shows formation of an oxide transparent conductor layer. / Third resist coating / exposure / development cross-sectional view, (b) shows a fourth etching / third resist stripped cross-sectional view.
In FIG. 6A, on the exposed interlayer insulating film 50, n-type oxide semiconductor layer 40, and metal transparent oxide layer 26 for protecting the metal layer, indium oxide-zinc oxide (In ₂ O ₃ : ZnO = about 90:10 wt%) target and a transparent oxide layer having a thickness of about 120 nm under the condition of a substrate temperature of about 150 ° C. while maintaining a predetermined oxygen: argon ratio (about 10:90 Vol.%) State. 60 is deposited. Under this condition, the oxide transparent conductor layer 60 is obtained as an amorphous film. The amorphous indium oxide-zinc oxide thin film is etched with a mixed acid and oxalic acid aqueous solution.

The oxide transparent conductor layer 60 is not limited to the oxide conductor layer made of indium oxide-zinc oxide. For example, indium oxide-tin oxide, indium oxide-tin oxide-zinc oxide, indium oxide- Oxide conductor layer consisting of tin oxide-samarium oxide, or indium oxide-zinc oxide, indium oxide-tin oxide, indium oxide-tin oxide-zinc oxide, indium oxide-tin oxide-samarium oxide, etc. It is good also as an added oxide conductor layer.
In the present embodiment, the oxide transparent conductor layer 60 also serves as the source electrode 63, the drain electrode 64, the source wiring 65, the drain wiring 66, and the pixel electrode 67, and therefore, it is preferable to use a material having excellent conductivity. .

  Moreover, since the oxide transparent conductor layer 60 needs transparency, the energy gap is set to an oxide of 3.0 eV or more. Preferably it is 3.2 eV or more, More preferably, it is 3.4 eV or more. An oxide conductor layer composed of indium oxide-zinc oxide, indium oxide-tin oxide, indium oxide-tin oxide-zinc oxide, indium oxide-tin oxide-samarium oxide, or indium oxide-zinc oxide, indium oxide- An oxide conductor layer in which a lanthanoid element is added to tin oxide, indium oxide-tin oxide-zinc oxide, indium oxide-tin oxide-samarium oxide, etc. has an energy gap of 3.2 eV or more and is preferably used. The

  Next, as shown in FIG. 6A, a third resist 61 is applied on the oxide transparent conductor layer 60, and the third resist 61 is formed into a predetermined shape using a third mask 62. (Step S7). That is, the third resist 61 is formed in a shape covering the drain electrode 64, the source electrode 63, the source wiring 65, the drain wiring 66, the pixel electrode 67, and the gate wiring pad 25 (see FIG. 5B). In the present embodiment, the pixel electrode 67 and the source electrode 63 are connected via the source wiring 65, but the pixel electrode 67 and the drain electrode may be connected via the drain wiring.

Next, as shown in FIG. 4B, as the fourth etching, the oxide transparent conductor layer 60 is etched using the third resist 61 and the oxalic acid aqueous solution, and the drain electrode 64, the source electrode 63, Source wiring 65, pixel electrode 67, drain wiring 66 and gate wiring pad 25 are formed (step S8).
Thus, the source electrode 63 and the drain electrode 64 made of the oxide transparent conductor layer 60 are formed in the pair of openings 631 and 641 of the interlayer insulating film 50, respectively. The channel guard 500 and the channel part 44 are surely separated from each other. That is, since the channel guard 500, the channel portion 44, the source electrode 63 and the drain electrode 64 are reliably and easily manufactured, the yield can be improved and the manufacturing cost can be reduced. The TFT substrate 1 having such a structure is referred to as a VIA hole channel TFT substrate.

Also, the drain electrode 64, the source electrode 63, the source wiring 65, the pixel electrode 67, and the drain wiring 66 made of the oxide transparent conductor layer 60 are efficiently formed by the fourth etching. That is, the number of masks used in manufacturing can be reduced, and the number of manufacturing processes can be reduced, whereby the production efficiency can be improved and the manufacturing cost can be reduced.
Further, since the drain electrode 64, the source electrode 63, the source wiring 65, the pixel electrode 67, and the drain wiring 66 are made of the oxide transparent conductor layer 60, the amount of light transmission is increased, so that a display device with excellent luminance is obtained. Can be provided.

  Next, when the third resist 61 is ashed, the drain electrode 64, the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring 66, and the gate wiring pad 25 made of the oxide transparent conductor layer 60 are exposed. A drain electrode 64, a gate electrode 23, a channel portion 44, a source electrode 63, a source wiring 65, and a pixel electrode 67 shown in FIG. 6B show a cross section taken along line EE in FIG. The FF cross section is shown, and the gate wiring pad 25 shows the GG cross section.

Thus, according to the manufacturing method of the TFT substrate 1 of the present embodiment, the oxide semiconductor layer (n-type oxide semiconductor layer 40) is formed on the active semiconductor layer using the three masks 42, 52, and 62. The used VIA hole channel TFT substrate 1 can be manufactured, the manufacturing process can be reduced, and the manufacturing cost can be reduced. Further, since the channel portion 44 is protected by the channel guard 500, it can be stably operated over a long period of time. Further, since the n-type oxide semiconductor layer 40 is formed only at predetermined positions (predetermined positions corresponding to the channel portion 44, the source electrode 63, and the drain electrode 64), the gate wirings 24 interfere with each other. (Crosstalk) can be eliminated.
In this embodiment, the metal layer 20, the metal layer protecting oxide transparent conductor layer 26, the gate insulating film 30, the n-type oxide semiconductor layer 40, and the first resist 41 are formed on the glass substrate 10. In addition, the interlayer insulating film 50 and the second resist 51 are further laminated, and further, the oxide transparent conductor layer 60 and the third resist 61 are laminated. Each layer may be laminated via other layers (for example, without impairing the functions and effects of the present embodiment or assisting other functions and effects). The same applies to the embodiments described later.

[Application Example of First Embodiment in Manufacturing Method of TFT Substrate]
FIG. 8 is a schematic flowchart for explaining an application example of the manufacturing method of the TFT substrate according to the first embodiment of the present invention. The manufacturing method of this application example corresponds to claim 16.
In the manufacturing method of the TFT substrate 1 ′ according to this application example shown in the figure, the protective insulating film 70 and the fourth resist 71 are laminated on the TFT substrate 1 of the first embodiment described above (step S 9), and The fourth resist 71 is different in that the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 are exposed (step S10).
Therefore, other processes are substantially the same as those in the first embodiment, and the same processes are denoted by the same reference numerals as those in the first embodiment in the drawings, and detailed description thereof is omitted.

The processes using the first halftone mask, the second mask, and the third mask shown in FIG. 8 are substantially the same as those in the first embodiment.
Next, as shown in FIG. 8, the protective insulating film 70 and the fourth resist 71 are laminated, and the fourth resist 71 is formed into a predetermined shape using the fourth mask 72 (step S9). .
Next, processing using the fourth mask 72 will be described with reference to the drawings.

(Process using the fourth mask)
FIG. 9 is a schematic diagram for explaining a process using a fourth mask of an application example of the method for manufacturing a TFT substrate according to the first embodiment of the present invention, and FIG. The film / fourth resist coating / exposure / development sectional view is shown, and (b) shows the fifth etching / fourth resist stripped sectional view.
In FIG. 2A, first, a protective insulating film 70, which is a silicon nitride (SiN _x ) film, is formed on the interlayer insulating film 50 and the oxide transparent conductor layer 60 by glow discharge CVD (chemical vapor deposition). Deposit about 200 nm thick. In the present embodiment, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used as the discharge gas.
Next, a fourth resist 71 is applied on the protective insulating film 70, and the fourth resist 71 is formed into a predetermined shape using the fourth mask 72 (step S9). That is, the fourth resist 71 is formed in a shape that exposes the protective insulating film 70 above the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 (step S9).

Next, as shown in FIG. 5B, the exposed protective insulating film 70 is used as the fifth etching by using the fourth resist 71 and an etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)). Is dry-etched to expose the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 (step S10). Subsequently, when the fourth resist 71 is ashed, the protective insulating film 70 is exposed on the glass substrate 10 as shown in FIG. The drain electrode 64, the gate electrode 23, the channel part 44, the source electrode 63, the source wiring 65, and the pixel electrode 67 shown in FIG. 9B show the E'-E 'cross section in FIG. Reference numeral 68 denotes an F′-F ′ cross section, and the gate wiring pad 25 denotes a G′-G ′ cross section.

As described above, according to the manufacturing method of the TFT substrate 1 ′ of this application example, there are almost the same effects as the first embodiment, and the source electrode 63, the drain electrode 64, the source wiring 65 and the drain wiring 66 are not exposed. Thus, since the TFT substrate 1 ′ itself has a structure including the protective insulating film 70 and is covered with the protective insulating film 70, display means and light emitting means using liquid crystal or organic EL material can be easily manufactured. A TFT substrate 1 'can be provided.
In this application example, the source electrode 63, the drain electrode 64, the drain electrode 64, and the drain wiring 66 are substantially covered with the upper surface and side surfaces. However, as shown in the second embodiment of the manufacturing method of the reflective TFT substrate 1b. Alternatively, a method of substantially covering the upper surfaces of the source electrode 63, the drain electrode 64, the drain electrode 64, and the drain wiring 66 may be employed.

[First Embodiment in Method for Manufacturing Reflective TFT Substrate]
FIG. 11 is a schematic flowchart for explaining a method for manufacturing a reflective TFT substrate according to the first embodiment of the present invention. The manufacturing method according to this embodiment corresponds to claim 18.
In the manufacturing method of the reflective TFT substrate 1a according to the present embodiment shown in the figure, instead of step S7 in the first embodiment of the TFT substrate 1 described above, a reflective metal layer 60 and a third resist 61 are laminated, The third mask 61 is different in that the third resist 61 is formed (step S7a).
Accordingly, the other steps are substantially the same as those of the first embodiment of the method for manufacturing the TFT substrate 1, and the same steps are denoted by the same reference numerals in the drawing and detailed description thereof is omitted.

The processing using the first halftone mask and the second mask shown in FIG. 11 is substantially the same as that of the first embodiment of the method for manufacturing the TFT substrate 1.
Next, as shown in FIG. 11, a reflective metal layer 60a and a third resist 61 are laminated in this order above the glass substrate 10 on which the openings 631, 641, and 251 are formed, and a third mask 62 is formed. The third resist 61 is formed into a predetermined shape by using it (step S7a).
Next, processing using the third mask 62 will be described with reference to the drawings.

(Process using third mask)
FIG. 12 is a schematic view for explaining a process using a third mask in the method for manufacturing a reflective TFT substrate according to the first embodiment of the present invention, and (a) is an oxide transparent conductor layer. FIG. 4B shows a cross-sectional view after film formation / third resist coating / exposure / development, and FIG. 4B shows a cross-sectional view after fourth etching / third resist peeling.
In FIG. 5A, Al is deposited to a thickness of about 120 nm on the exposed interlayer insulating film 50, the n-type oxide semiconductor layer 40, and the metal transparent oxide layer 26 for protecting the metal layer, and a reflection made of Al. A metal layer 60a is formed. That is, an Al thin film layer is formed using an Al target by high-frequency sputtering under the condition of 100% argon. Note that the reflectance of the reflective metal layer 60a is preferably 80% or more, and in this way, a reflective TFT substrate 1a having excellent luminance can be provided. Further, instead of the reflective metal layer 60a made of Al, a metal thin film such as Ag or Au may be used. In this way, more light can be reflected and the luminance can be improved.

  Next, as shown in FIG. 6A, a third resist 61 is applied on the reflective metal layer 60a, and the third resist 61 is formed into a predetermined shape using the third mask 62. (Step S7a). That is, the third resist 61 is formed in a shape covering the drain electrode 64, the source electrode 63, the source wiring 65, the drain wiring 66, the pixel electrode 67, and the gate wiring pad 25 (see FIG. 5B). In the present embodiment, the pixel electrode 67 and the source electrode 63 are connected via the source wiring 65, but the pixel electrode 67 and the drain electrode may be connected via the drain wiring.

Next, as shown in FIG. 4B, as the fourth etching, the reflective metal layer 60a is etched using the third resist 61 and mixed acid, and the drain electrode 64, the source electrode 63, the source wiring 65, Pixel electrode 67, drain wiring 66 and gate wiring pad 25 are formed (step S8).
In this case, the source electrode 63 and the drain electrode 64 made of the reflective metal layer 60a are formed in the pair of openings 631 and 641 of the interlayer insulating film 50, respectively. 500 and the channel part 44 are formed to be surely separated from each other. That is, since the channel guard 500, the channel portion 44, the source electrode 63 and the drain electrode 64 are reliably and easily manufactured, the yield can be improved and the manufacturing cost can be reduced. The reflective TFT substrate 1a having such a structure is referred to as a VIA hole channel type reflective TFT substrate.

  In addition, the drain electrode 64, the source electrode 63, the source wiring 65, the pixel electrode 67, and the drain wiring 66 made of the reflective metal layer 60a are efficiently formed by the fourth etching. That is, the number of masks used in manufacturing can be reduced, and the number of manufacturing processes can be reduced, whereby the production efficiency can be improved and the manufacturing cost can be reduced.

  Next, when the third resist 61 is ashed, the drain electrode 64, the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring 66, and the gate wiring pad 25 made of the reflective metal layer 60a are exposed. The drain electrode 64, the gate electrode 23, the channel portion 44, the source electrode 63, the source wiring 65 and the pixel electrode 67 shown in FIG. 12B show the HH cross section in FIG. The II cross section is shown, and the gate wiring pad 25 shows the JJ cross section.

  Thus, according to the manufacturing method of the reflective TFT substrate 1a of the present embodiment, an oxide semiconductor layer (n-type oxide semiconductor layer 40) is formed on the active semiconductor layer using the three masks 42, 52, and 62. VIA hole channel type reflective TFT substrate 1a can be manufactured, the manufacturing process can be reduced, and the manufacturing cost can be reduced. Further, since the channel portion 44 is protected by the channel guard 500, it can be stably operated over a long period of time. Further, since the n-type oxide semiconductor layer 40 is formed only at predetermined positions (predetermined positions corresponding to the channel portion 44, the source electrode 63, and the drain electrode 64), the gate wirings 24 interfere with each other. (Crosstalk) can be eliminated.

[Second Embodiment in Method for Manufacturing Reflective TFT Substrate]
FIG. 14 is a schematic flowchart for explaining a manufacturing method of the reflective TFT substrate according to the second embodiment of the present invention. The manufacturing method according to the present embodiment corresponds to claim 19.
The manufacturing method of the reflective TFT substrate 1b according to the present embodiment shown in the figure is the same as the reflective TFT substrate 1a in place of the reflective metal layer 60a, the protection metal layer 60a, and the protective metal layer 60a. Insulating film 70b and third resist 71b are laminated, and third resist 71b is formed by third halftone mask 72b (step S7b). Using third resist 71b, drain electrode 64, source The electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring 66, and the gate wiring pad 25 are formed (step S8b), the third resist 71b is re-formed (step S9b), and the re-formed third The pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 are exposed using the resist 71b (step 10b) points are different.
Accordingly, the other steps are almost the same as those in the first embodiment of the method for manufacturing a reflective TFT substrate, and the same steps are denoted by the same reference numerals as those in the first embodiment in the drawing, and detailed description will be given. Is omitted.

The processing using the first halftone mask and the second mask shown in FIG. 14 is substantially the same as in the first embodiment.
Subsequently, as shown in FIG. 14, the reflective metal layer 60a, the protective insulating film 70b, and the third resist 71b are stacked, and the third resist 71b is predetermined by a third halftone mask 72b and halftone exposure. (Step S7b).
Next, processing using the third halftone mask 72b will be described with reference to the drawings.

(Processing using a third halftone mask)
FIG. 15 is a schematic view for explaining a process using a third halftone mask in the method for manufacturing a reflective TFT substrate according to the second embodiment of the present invention, and FIG. Film / protective insulating film formation / third resist coating / halftone exposure / development sectional view, (b) shows a fourth etched sectional view.
In FIG. 1A, first, the exposed interlayer insulating film 50, the n-type oxide semiconductor layer 40, and the oxide transparent conductor layer for protecting the metal layer, as in the first embodiment of the manufacturing method of the reflective TFT substrate. On the layer 26, Al is laminated to a thickness of about 120 nm to form a reflective metal layer 60a made of Al.

Subsequently, a protective insulating film 70b, which is a silicon nitride (SiN _x ) film, is deposited on the reflective metal layer 60a by a glow discharge CVD (chemical vapor deposition) method to a thickness of about 200 nm. In the present embodiment, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used as the discharge gas.

  Next, as shown in FIG. 5A, a third resist 71b is applied on the protective insulating film 70b, and the third resist 71b is applied to the third resist 71b by a third halftone mask 72b and halftone exposure. (Step S7b). That is, the third resist 71 b covers the drain electrode 64, the source electrode 63, the source wiring 65, the drain wiring 66, the pixel electrode 67 and the gate wiring pad 25, and the half-tone mask portion 721 b causes the pixel electrode 67, drain A portion covering the wiring pad 68 and the gate wiring pad 25 is formed in a thinner shape than the other portions (see FIG. 5B).

Next, as shown in FIG. 5B, as the fourth etching, first, a third resist 71b and an etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)) are used to expose the protective insulation. The film 70b is dry-etched, and the reflective metal layer 60a is etched with a third resist 71b and an etchant (mixed acid) to obtain a drain electrode 64, a source electrode 63, a source wiring 65, a pixel electrode 67, a drain wiring 66, and A gate wiring pad 25 is formed (step S8b).

FIG. 16 is a schematic view for explaining a process using a third halftone mask in the method for manufacturing a reflective TFT substrate according to the second embodiment of the present invention, and FIG. (B) shows a cross-sectional view of the fifth etching / third resist stripped.
In FIG. 6A, the third resist 71b is ashed so that the protective insulating film 70 above the pixel electrode 67, the drain wiring pad 68 and the gate wiring pad 25 is exposed. Re-formation is performed (step S9b).

Next, as shown in FIG. 5B, as the fifth etching, exposed protection is performed using the re-formed third resist 71b and etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)). The insulating film 70b is dry etched to expose the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 (step S10b). Subsequently, when the re-formed third resist 71b is ashed, as shown in FIG. 17, the protection laminated on the drain electrode 64, the source electrode 63, the source wiring 65, and the drain wiring 66 on the glass substrate 10 is performed. The insulating film 70b is exposed. The drain electrode 64, the gate electrode 23, the channel portion 44, the source electrode 63, the source wiring 65, and the pixel electrode 67 shown in FIG. 16B show the Hb-Hb cross section in FIG. The Ib-Ib cross section is shown, and the gate wiring pad 25 shows the Jb-Jb cross section.

Thus, according to the manufacturing method of the reflective TFT substrate 1b of the present embodiment, the same effect as that of the first embodiment of the manufacturing method of the reflective TFT substrate is obtained, and the source electrode 63, the drain electrode 64, and the source By covering the upper portions of the wiring 65 and the drain wiring 66 with the protective insulating film 70b, the operational stability of the TFT can be improved.
In this embodiment, the protective insulating film 70b is formed on the source electrode 63 and the source wiring 65. However, a method in which this protective insulating film 70b is not formed may be used. In this case, since the upper surfaces of the source electrode 63 and the source wiring 65 also function as a reflective layer, the amount of reflected light can be increased and the luminance can be improved.

In this embodiment, the side portions of the source electrode 63, the drain electrode 64, the source wiring 65, and the drain wiring 66 are exposed, but these side portions can be covered with the protective insulating film 70c.
Next, a manufacturing method in which the side portions of the source electrode 63, the drain electrode 64, the source wiring 65, and the drain wiring 66 are also covered with the protective insulating film 70c will be described with reference to the drawings.

[Third embodiment of the manufacturing method of the reflective TFT substrate]
FIG. 18 is a schematic flowchart for explaining a manufacturing method of the reflective TFT substrate according to the third embodiment of the present invention. The manufacturing method according to the present embodiment corresponds to claim 20.
In the manufacturing method of the reflective TFT substrate 1c according to the present embodiment shown in the figure, the protective insulating film 70c and the fourth resist 71c are laminated on the reflective TFT substrate 1a of the first embodiment described above (step S9c). Further, the fourth resist 71c is used to expose the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 (step S10c).
Therefore, the other steps are almost the same as those of the first embodiment of the manufacturing method of the reflective TFT substrate 1a, and the same steps are denoted by the same reference numerals as those of the first embodiment in the drawing, and are described in detail. Description is omitted.

The processes using the first halftone mask, the second mask, and the third mask shown in FIG. 18 are substantially the same as those in the first embodiment.
Next, as shown in FIG. 18, the protective insulating film 70c and the fourth resist 71c are stacked, and the fourth resist 71c is formed into a predetermined shape using the fourth mask 72c (step S9c). .
Next, processing using the fourth mask 72c will be described with reference to the drawings.

(Process using the fourth mask)
FIG. 19 is a schematic view for explaining a process using a fourth mask in the method for manufacturing a reflective TFT substrate according to the third embodiment of the present invention. FIG. / 4th resist coating / exposure / development sectional view, (b) shows a fifth etching / fourth resist stripped sectional view.
In FIG. 6A, first, a protective insulating film 70c, which is a silicon nitride (SiN _x ) film, is formed on the interlayer insulating film 50 and the reflective metal layer 60a by a glow discharge CVD (chemical vapor deposition) method. Deposit. In the present embodiment, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used as the discharge gas.
Next, a fourth resist 71c is applied on the protective insulating film 70c, and the fourth resist 71c is formed into a predetermined shape using the fourth mask 72c (step S9c). That is, the fourth resist 71c is formed in a shape exposing the protective insulating film 70 above the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 (step S9c). .
In the present embodiment, the source electrode 63 and the source wiring 65 are also exposed. However, the present invention is not limited to this method, and at least the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 may be exposed. .

Next, as shown in FIG. 5B, the exposed protective insulating film 70c is used as the fifth etching by using the fourth resist 71 and an etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)). Then, the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring pad 68 and the gate wiring pad 25 are exposed (step S10c). Subsequently, when the fourth resist 71c is ashed, the protective insulating film 70c is exposed on the glass substrate 10 as shown in FIG. The drain electrode 64, the gate electrode 23, the channel part 44, the source electrode 63, the source wiring 65, and the pixel electrode 67 shown in FIG. 19B show the Hc-Hc cross section in FIG. The Ic-Ic cross section is shown, and the gate wiring pad 25 shows the Jc-Jc cross section.

  As described above, according to the manufacturing method of the reflective TFT substrate 1c of this embodiment, the protective insulating film 70 has the same effect as that of the first embodiment and prevents the drain electrode 64 and the drain wiring 66 from being exposed. Since the reflective TFT substrate 1c itself has a structure including the protective insulating film 70c, the reflective TFT substrate 1c capable of easily manufacturing display means and light emitting means using liquid crystal or organic EL material is provided. Can be provided.

[Fourth Embodiment in Manufacturing Method of Reflective TFT Substrate]
FIG. 21 is a schematic flowchart for explaining a manufacturing method of the reflective TFT substrate according to the fourth embodiment of the present invention. The manufacturing method of this embodiment corresponds to claim 19 + 22.
The manufacturing method of the reflective TFT substrate 1d according to this embodiment shown in the figure is for protecting the metal layer above the reflective metal layer 60a as compared with the second embodiment of the manufacturing method of the reflective TFT substrate 1b described above. The difference is that the oxide transparent conductor layer 69 is stacked (step S7d).
Therefore, the other steps are almost the same as those in the second embodiment of the manufacturing method of the reflective TFT substrate 1b, and the same steps are denoted by the same reference numerals as those in the second embodiment in the drawing, and are described in detail. Description is omitted.

The processing using the first halftone mask and the second mask shown in FIG. 21 is substantially the same as in the second embodiment.
Next, processing using the third halftone mask 72d will be described with reference to the drawings.

(Processing using a third halftone mask)
FIG. 22 is a schematic view for explaining a process using a third halftone mask in the method for manufacturing a reflective TFT substrate according to the fourth embodiment of the present invention. FIG. Film / Metal layer protecting oxide transparent conductor film forming / Protecting insulating film forming / third resist coating / halftone exposure / developed cross-sectional view, (b) fourth etched cross section The figure is shown.
In FIG. 6A, first, Al is deposited to a thickness of about 120 nm on the exposed interlayer insulating film 50, the n-type oxide semiconductor layer 40, and the metal layer protecting oxide transparent conductor layer 26. A reflective metal layer 60a is formed. That is, an Al thin film layer is formed using an Al target by high-frequency sputtering under the condition of 100% argon.

Subsequently, a sputtering target made of indium oxide-zinc oxide (generally called IZO, In ₂ O ₃ : ZnO = 90: 10 wt%) is used on the reflective metal layer 60a, and a predetermined oxygen: argon An oxide transparent conductor layer 69 for protecting the metal layer having a film thickness of about 50 nm is formed under the condition of the substrate temperature of about 150 ° C. while maintaining the ratio (about 1:99 Vol.%). Under this condition, the metal thin film protecting oxide conductive layer 69 is obtained as an amorphous film. This makes it possible to perform batch etching together with the reflective metal layer 60a using a mixed acid, thereby improving production efficiency.

Subsequently, a protective insulating film 70b, which is a silicon nitride (SiN _x ) film, is deposited on the metal layer protective oxide transparent conductor layer 69 by a glow discharge CVD (chemical vapor deposition) method to a thickness of about 200 nm. In the present embodiment, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used as the discharge gas.

  Next, as shown in FIG. 6A, a third resist 71d is applied on the protective insulating film 70b, and the third resist 71d is applied to the predetermined pattern by the third halftone mask 72d and halftone exposure. (Step S7d). That is, the third resist 71d covers the drain electrode 64, the source electrode 63, the source wiring 65, the drain wiring 66, the pixel electrode 67, and the gate wiring pad 25, and the halftone mask portion 721d allows the source electrode 63 and the source A portion covering the wiring 65, the pixel electrode 67, the drain wiring pad 68 and the gate wiring pad 25 is formed in a thinner shape than the other portions (see FIG. 4B).

Next, as shown in FIG. 4B, as the fourth etching, first, a third resist 71d and an etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)) are used to expose the protective insulation. The film 70b is dry-etched, and the metal transparent protective oxide layer 69 and the reflective metal layer 60a are collectively etched with the third resist 71b and an etching solution (mixed acid) to obtain a drain electrode 64 and a source electrode 63. , Source wiring 65, pixel electrode 67, drain wiring 66 and gate wiring pad 25 are formed (step S8d).

FIG. 23 is a schematic view for explaining a process using a third halftone mask in the method for manufacturing a reflective TFT substrate according to the fourth embodiment of the present invention. FIG. (B) is a cross-sectional view of the fifth etching / third resist stripped.
In FIG. 6A, the third resist 71d is ashed to expose the protective insulating film 70 above the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25. Then, the third resist 71b is re-formed (step S9d).

Next, as shown in FIG. 5B, as the fifth etching, exposed protection is performed using the re-formed third resist 71d and an etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)). The insulating film 70b is dry etched to expose the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 (step S10d). Subsequently, when the re-formed third resist 71b is ashed, the protective insulating film 70b laminated on the drain electrode 64 and the drain wiring 66 is exposed on the glass substrate 10, as shown in FIG. The drain electrode 64, the gate electrode 23, the channel part 44, the source electrode 63, the source wiring 65, and the pixel electrode 67 shown in FIG. 23B show the Hd-Hd cross section in FIG. The Id-Id cross section is shown, and the gate wiring pad 25 shows the Jd-Jd cross section.

Thus, according to the manufacturing method of the reflective TFT substrate 1d of the present embodiment, the same effect as that of the second embodiment of the manufacturing method of the reflective TFT substrate is obtained, and corrosion of the reflective metal layer 60a is prevented. And durability can be improved. Moreover, discoloration etc. of the reflective metal layer 60a can be prevented, and the malfunction that the reflectance of the reflective metal layer 60a falls can be prevented. Furthermore, in the present embodiment, the protective insulating film 70b is not formed on the source electrode 63 and the source wiring 65, and the source electrode 63 and the source wiring 65 are exposed, so that the upper surfaces of the source electrode 63 and the source wiring 65 are exposed. Also functions as a reflective layer, the amount of reflected light can be increased, and the luminance can be improved.
In addition, the oxide transparent conductor layer 69 for protecting a metal layer formed in the present embodiment can be molded also in the first embodiment and the third embodiment of the manufacturing method of the reflective TFT substrate described above. The same effect as the embodiment can be exhibited.

[Fifth embodiment of the manufacturing method of the reflective TFT substrate]
FIG. 25 is a schematic flowchart for explaining a method for manufacturing a reflective TFT substrate according to the fifth embodiment of the present invention. The manufacturing method according to this embodiment corresponds to claim 19 + 21.
The manufacturing method of the reflective TFT substrate 1e according to the present embodiment shown in the same drawing is compared with the fourth embodiment in the manufacturing method of the reflective TFT substrate 1d described above, and the n-type oxide semiconductor layer 40 and the reflective metal layer 60a. Is different in that the oxide transparent conductor layer 60 is laminated (step S7e).
Accordingly, the other steps are substantially the same as those in the fourth embodiment in the method of manufacturing the reflective TFT substrate 1d, and the same steps are denoted by the same reference numerals as those in the fourth embodiment in the drawing, and are described in detail. Description is omitted.

The processing using the first halftone mask and the second mask shown in FIG. 25 is substantially the same as that of the fourth embodiment.
Next, processing using the third halftone mask 72d will be described with reference to the drawings.

(Processing using a third halftone mask)
FIG. 26 is a schematic view for explaining a process using a third halftone mask in the method for manufacturing a reflective TFT substrate according to the fifth embodiment of the present invention, and FIG. Body layer film formation / reflection metal layer film formation / metal layer protection oxide transparent conductor layer film formation / protection insulating film film formation / third resist coating / halftone exposure / development sectional view (b) ) Shows a fourth etched cross-sectional view.
In FIG. 2A, first, indium oxide-zinc oxide (generally, IZO and the like are formed on the exposed interlayer insulating film 50, the n-type oxide semiconductor layer 40, and the metal layer protecting oxide transparent conductor layer 26. Using a sputtering target composed of In ₂ O ₃ : ZnO = 90: 10 wt%, the substrate temperature is maintained at about 150 ° C. while maintaining a predetermined oxygen: argon ratio (about 1:99 Vol.%) State. Thus, the oxide transparent conductor layer 60 having a thickness of about 50 nm is formed. Under this condition, the metal thin film protecting oxide conductive layer 69 is obtained as an amorphous film. If it does in this way, it will become possible to etch collectively with the oxide transparent conductor layer 69 for metal layer protection and the reflective metal layer 60e using a mixed acid, and it can improve production efficiency.

  Next, Mo and Al are laminated on the n-type oxide semiconductor layer 60 in this order using a high frequency sputtering method to have a film thickness of about 50 nm and 250 nm, respectively, thereby forming a reflective metal layer 60e. That is, although not shown, the reflective metal layer 60e is composed of a Mo thin film layer and an Al thin film layer. First, using a Mo target, the Mo thin film layer is subjected to high-frequency sputtering under a condition of 100% argon. Form. Subsequently, using an Al target, an Al thin film layer is formed under a condition of 100% argon by high frequency sputtering.

Subsequently, a sputtering target made of indium oxide-zinc oxide (generally called IZO, In ₂ O ₃ : ZnO = 90: 10 wt%) is used on the reflective metal layer 60e, and a predetermined oxygen: argon An oxide transparent conductor layer 69 for protecting the metal layer having a film thickness of about 50 nm is formed under the condition of the substrate temperature of about 150 ° C. while maintaining the ratio (about 1:99 Vol.%).

Subsequently, a protective insulating film 70b, which is a silicon nitride (SiN _x ) film, is deposited on the metal layer protective oxide transparent conductor layer 69 by a glow discharge CVD (chemical vapor deposition) method to a thickness of about 100 nm. In the present embodiment, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used as the discharge gas.

  Next, as shown in FIG. 6A, a third resist 71d is applied on the protective insulating film 70b, and the third resist 71d is applied to the predetermined pattern by the third halftone mask 72d and halftone exposure. (Step S7e). That is, the third resist 71d covers the drain electrode 64, the source electrode 63, the source wiring 65, the drain wiring 66, the pixel electrode 67, and the gate wiring pad 25, and the halftone mask portion 721d allows the source electrode 63 and the source A portion covering the wiring 65, the pixel electrode 67, the drain wiring pad 68 and the gate wiring pad 25 is formed in a thinner shape than the other portions (see FIG. 4B).

Next, as shown in FIG. 4B, as the fourth etching, first, a third resist 71d and an etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)) are used to expose the protective insulation. The film 70b is dry etched, and the oxide transparent conductor layer 69 for protecting the metal layer, the reflective metal layer 60a, and the oxide transparent conductor layer 60 are collectively etched with the third resist 71b and an etching solution (mixed acid). Then, the drain electrode 64, the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring 66, and the gate wiring pad 25 are formed (step S8e).

FIG. 27 is a schematic view for explaining a process using a third halftone mask in the method for manufacturing a reflective TFT substrate according to the fifth embodiment of the present invention, and FIG. (B) shows a cross-sectional view of the fifth etching / third resist stripped.
In FIG. 6A, the third resist 71d is ashed to expose the protective insulating film 70 above the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25. Then, the third resist 71b is re-formed (step S9e).

Next, as shown in FIG. 5B, as the fifth etching, exposed protection is performed using the re-formed third resist 71d and an etching gas (CHF (CF ₄ , CHF ₃ gas, etc.)). The insulating film 70b is dry etched to expose the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25 (step S10e). Subsequently, when the re-formed third resist 71b is ashed, the protective insulating film 70b laminated on the drain electrode 64 and the drain wiring 66 is exposed on the glass substrate 10, as shown in FIG. The drain electrode 64, the gate electrode 23, the channel portion 44, the source electrode 63, the source wiring 65, and the pixel electrode 67 shown in FIG. 27B show the He-He cross section in FIG. The Ie-Ie cross section is shown, and the gate wiring pad 25 shows the Je-Je cross section.

Thus, according to the manufacturing method of the reflective TFT substrate 1e of the present embodiment, the same effect as that of the fourth embodiment of the manufacturing method of the reflective TFT substrate can be obtained, and the switching speed of the TFT can be increased. In addition, the durability of the TFT can be improved.
In addition, the oxide transparent conductor layer 60 formed in this embodiment can be formed also in the first embodiment and the third embodiment of the manufacturing method of the reflective TFT substrate described above, and is the same as this embodiment. The effect of can be demonstrated.

[First embodiment of TFT substrate]
Next, an embodiment of the TFT substrate 1 of the present invention will be described.
As shown in FIGS. 6B and 7, the TFT substrate 1 according to the first embodiment includes a glass substrate 10, a gate electrode 23 and a gate wiring 24 formed on the glass substrate 10, and the gate electrode 23. And a gate insulating film 30 that is formed above the gate wiring 24 and insulates the upper surfaces of the gate electrode 23 and the gate wiring 24, and an n formed above the gate electrode 23 and above the gate insulating film 30. Formed on the side of the n-type oxide semiconductor layer 40, the side of the gate electrode 23 and the gate wiring 24, and above and on the side of the n-type oxide semiconductor layer 40. Insulating the type oxide semiconductor layer 40 and further separating the source electrode opening 631 and the drain electrode at positions separated by the channel part 44 of the n type oxide semiconductor layer 40, respectively. An interlayer insulating film 50 mouth 641 is formed, and a source electrode 63 formed on the source electrode opening 631, and a drain electrode 64 formed on the drain electrode opening 641.

Further, in the TFT substrate 1, the same oxide transparent conductor layer 60 is formed as a conductor layer to be the source electrode 63 and the drain electrode 64, and the oxide transparent conductor layer 60 also serves as at least the pixel electrode 67. As a configuration. In this embodiment, the oxide transparent conductor layer 60 is used as the conductor layer. However, the present invention is not limited to this. For example, a conductor layer made of metal may be used. Therefore, it is possible to provide a reflective TFT substrate that can operate stably over a long period of time, can improve the yield, and can reduce the manufacturing cost.
Further, the TFT substrate 1 uses an n-type oxide semiconductor layer 40 as an oxide layer, and by using the n-type oxide semiconductor layer 40 as an active layer of a TFT, the TFT substrate 1 is stable even when a current is passed. Yes, it is useful for organic electroluminescent devices that operate by current control.

  The TFT substrate 1 has a configuration in which the n-type oxide semiconductor layer 40 is formed at predetermined positions corresponding to the channel portion 44, the source electrode 63, and the drain electrode 64. In this way, since the n-type oxide semiconductor layer 40 is normally formed only at a predetermined position, it is possible to eliminate the concern that the gate wirings 24 interfere with each other (crosstalk).

  As described above, according to the TFT substrate 1 of the present embodiment, the n-type oxide semiconductor layer 40 that becomes the channel portion 44 is protected by the interlayer insulating film 50, and thus can operate stably over a long period of time. Further, since the channel portion 44, the drain electrode 64, and the source electrode 63 are reliably and easily manufactured, the yield can be improved and the manufacturing cost can be reduced. Further, the number of masks used in manufacturing can be reduced and the number of manufacturing processes can be reduced, so that the production efficiency can be improved and the manufacturing cost can be reduced.

The TFT substrate 1 has various application examples. For example, as shown in FIGS. 9B and 10, the upper side of the glass substrate 10 is covered with a protective insulating film 70 and is protected. The insulating film 70 may have an opening at a position corresponding to the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25. In this way, since the TFT substrate 1 ′ itself has a structure including the protective insulating film 70, a TFT substrate 1 ′ that can easily manufacture display means and light emitting means using liquid crystal or organic EL material is provided. can do.
In the present embodiment, the metal layer 20, the gate insulating film 30, and the n-type oxide semiconductor layer 40 are stacked on the glass substrate 10, and the interlayer insulating film 50 and the oxide transparent conductor layer 60 are further stacked. However, the present invention is not limited to this. For example, another layer (for example, does not impair the function or effect of the present embodiment or assists another function or effect) between the layers. It is good also as a structure laminated | stacked via. The same applies to the embodiments described later.

[First Embodiment of Reflective TFT Substrate]
Next, a first embodiment of the reflective TFT substrate 1a of the present invention will be described.
As shown in FIGS. 12B and 13, the reflective TFT substrate 1 a according to the first embodiment is formed on the glass substrate 10 and the glass substrate 10, and the upper surface is covered with the gate insulating film 30. The gate electrode 23 and the gate wiring 24 which are insulated by covering the side surfaces with the interlayer insulating film 50, and the oxide layer formed above the gate electrode 23 and above the gate insulating film 30. Formed on the n-type oxide semiconductor layer 40, the reflective metal layer 60a formed on the n-type oxide semiconductor layer 40 and separated by the channel portion 44, and on the channel portion 44 of the n-type oxide semiconductor layer 40. And a channel guard 500 that protects the channel portion 44.
The channel guard 500 includes an interlayer insulating film 50 in which a pair of openings 631 and 641 are formed. A source electrode 63 and a drain electrode 64 each having a reflective metal layer 60a are formed in the openings 631 and 641.
In this way, the upper portion of the n-type oxide semiconductor layer 40 in the channel portion 44 is protected by the channel guard 500, and thus operates stably over a long period of time. Further, since the channel guard 500, the channel portion 44, the drain electrode 64, and the source electrode 63 are reliably and easily manufactured, the yield can be improved and the manufacturing cost can be reduced.

  Preferably, the reflective metal layer 60a is made of a thin film made of aluminum, silver or gold or an alloy layer containing aluminum, silver or gold. In this way, more light can be reflected, and the brightness due to the reflected light can be improved.

  In the reflective TFT substrate 1 a, the channel guard 500 is made of the interlayer insulating film 50, and the drain electrode 64 and the source electrode 63 are formed in the pair of openings 641 and 631 of the interlayer insulating film 50, respectively. In this way, the channel portion 44, the drain electrode 64, and the source electrode 63 are reliably and easily manufactured, so that the yield can be improved and the manufacturing cost can be reduced.

In the reflective TFT substrate 1a, the reflective metal layer 60a also serves as the source wiring 65, the drain wiring 66, the source electrode 63, the drain electrode 64, and the pixel electrode 67. As described above, the source wiring 65, the drain wiring, and the like. 66, the source electrode 63, the drain electrode 64, and the pixel electrode 67 are efficiently manufactured. That is, the number of masks used in manufacturing can be reduced, and the number of manufacturing processes can be reduced, whereby the production efficiency can be improved and the manufacturing cost can be reduced.
Further, the reflective TFT substrate 1 a has an oxide layer as an n-type oxide semiconductor layer 40. Thus, by using an oxide semiconductor layer as the active layer of the TFT, it is stable even when a current is passed, and is useful for an organic electroluminescent device that operates by current control. Furthermore, since the energy gap of the n-type oxide semiconductor layer 40 is 3.0 eV or more, malfunction due to light can be prevented.

  In the reflective TFT substrate 1a, the n-type oxide semiconductor layer 40 is formed only at predetermined positions corresponding to the channel portion 44, the source electrode 63, and the drain electrode 64, and the gate wirings 24 interfere with each other ( Cross-talk) can be eliminated.

  In addition, the reflective TFT substrate 1a includes the gate electrode 23 and the gate wiring 24 which are composed of the metal layer 20 and the oxide transparent conductor layer 26 for protecting the metal layer, and prevents corrosion of the metal layer 20 and has durability. Can be improved. In this way, when the opening 251 for the gate wiring pad 25 is formed, it is possible to prevent the metal surface from being exposed and to improve the connection reliability.

  As described above, according to the reflective TFT substrate 1a of the present embodiment, the channel guard 500 protects the upper part of the n-type oxide semiconductor layer 40 of the channel portion 44, so that it operates stably over a long period of time. Further, since the channel guard 500, the channel portion 44, the drain electrode 64, and the source electrode 63 are reliably and easily manufactured, the yield can be improved and the manufacturing cost can be reduced.

[Second Embodiment of Reflective TFT Substrate]
Next, a second embodiment of the reflective TFT substrate 1b of the present invention will be described.
Compared with the reflective TFT substrate 1a of the first embodiment, the reflective TFT substrate 1b according to the second embodiment has a source electrode 63, a source wiring 65, and a drain electrode, as shown in FIGS. 64 and the drain wiring 66 is provided with a protective insulating film 70 b that covers the upper surfaces of the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25. Other configurations are substantially the same as those of the reflective TFT substrate 1a.

As described above, according to the reflective TFT substrate 1b of the present embodiment, the upper part of the source electrode 63, the drain electrode 64, the source wiring 65 and the drain wiring 66 is covered with the protective insulating film 70b. Can be improved.
In this embodiment, the protective insulating film 70b is formed on the source electrode 63 and the source wiring 65. However, the protective insulating film 70b may not be formed. In this case, since the upper surfaces of the source electrode 63 and the source wiring 65 also function as a reflective layer, the amount of reflected light can be increased and the luminance can be improved.

[Third embodiment of a reflective TFT substrate]
Next, a third embodiment of the reflective TFT substrate 1c of the present invention will be described.
Compared with the reflective TFT substrate 1a of the first embodiment, the reflective TFT substrate 1c according to the third embodiment protects almost all of the upper side of the glass substrate 10 as shown in FIGS. The protective insulating film 70c is covered by the protective insulating film 70c and has openings at positions corresponding to the source electrode 63, the source wiring 65, the pixel electrode 67, the drain wiring pad 68, and the gate wiring pad 25. To do. Other configurations are substantially the same as those of the reflective TFT substrate 1a.

As described above, according to the reflective TFT substrate 1c of the present embodiment, the reflective TFT substrate 1c itself has a structure including a protective insulating film. Therefore, display means and light emitting means using liquid crystal, organic EL material, or the like. It is possible to provide a reflective TFT substrate 1c that can be easily manufactured.
The reflective TFT substrate of the present invention has various application examples in addition to the above embodiment. For example, the reflective TFT substrate 1d shown in FIGS. 23B and 24 includes a reflective metal layer. An oxide transparent conductor layer 69 for protecting the metal layer that protects the reflective metal layer 60a is provided on 60a. If it does in this way, discoloration etc. of reflective metal layer 60a can be prevented, and the malfunction that the reflectance of reflective metal layer 60a falls can be prevented. Furthermore, since it is transparent, the amount of light transmission does not decrease, and a display device with excellent luminance can be provided.
As one application example, for example, the reflective TFT substrate 1e shown in FIGS. 27B and 28 includes an oxide transparent conductor layer between the n-type oxide semiconductor layer 40 and the reflective metal layer 60a. 60. In this way, the switching speed of the TFT can be increased and the durability of the TFT can be improved.

  The TFT substrate and the reflective TFT substrate of the present invention and the manufacturing method thereof have been described with reference to the preferred embodiments. The TFT substrate and the reflective TFT substrate according to the present invention and the manufacturing method thereof have been described above. Needless to say, the present invention is not limited to the embodiments, and various modifications can be made within the scope of the present invention.

  The TFT substrate and the reflective TFT substrate of the present invention and the manufacturing method thereof are not limited to the TFT substrate and the reflective TFT substrate used in LCDs (liquid crystal display devices) and organic EL display devices and the manufacturing methods thereof. For example, the present invention can be applied to a display device other than an LCD (liquid crystal display device) or an organic EL display device, or a TFT substrate and a reflective TFT substrate used for other purposes, and a manufacturing method thereof. Is possible.

The schematic flowchart figure for demonstrating the manufacturing method of the TFT substrate concerning 1st embodiment of this invention is shown. It is the schematic for demonstrating the process using the 1st halftone mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is metal layer film-forming / gate insulating film film-forming / N-type oxide semiconductor layer film formation / first resist application / halftone exposure / developed cross-sectional view, (b) a first etching / first resist re-formed cross-sectional view ( c) shows a cross-sectional view of the second etching / first resist stripped. In the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, the schematic plan view of the principal part of the TFT substrate after the 1st resist is peeled is shown. It is the schematic for demonstrating the process using the 2nd mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is interlayer insulation film film formation / 2nd resist application / The exposed / developed cross-sectional view, (b) shows the third etched cross-sectional view, and (c) shows the second resist-removed cross-sectional view. In the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, the schematic plan view of the principal part of the TFT substrate after the 2nd resist is peeled is shown. It is the schematic for demonstrating the process using the 3rd mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is oxide transparent conductor layer film-forming / 3rd FIG. 4B is a cross-sectional view after resist coating / exposure / development, and FIG. 4B is a cross-sectional view after the fourth etching / third resist peeling. In the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, the schematic plan view of the principal part of the TFT substrate after the 3rd resist is peeled is shown. The schematic flowchart figure for demonstrating the application example of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention is shown. It is the schematic for demonstrating the process using the 4th mask of the application example of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is film-forming of a protective insulating film / 4th. FIG. 5B is a cross-sectional view of the resist applied / exposed / developed, and FIG. 5B is a cross-sectional view of the fifth etched / fourth resist stripped. In the application example of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, the schematic plan view of the principal part of the TFT substrate after a 4th resist is peeled is shown. The schematic flowchart figure for demonstrating the manufacturing method of the reflection type TFT substrate concerning 1st embodiment of this invention is shown. It is the schematic for demonstrating the process using the 3rd mask of the manufacturing method of the reflection type TFT substrate concerning 1st embodiment of this invention, (a) is oxide transparent conductor layer film-forming / 1st. 3 shows a cross-sectional view after resist application / exposure / development, and (b) shows a cross-sectional view after the fourth etching / third resist is removed. In the manufacturing method of the reflective TFT substrate concerning 1st embodiment of this invention, the schematic plan view of the principal part of the reflective TFT substrate after a 3rd resist is peeled is shown. The schematic flowchart figure for demonstrating the manufacturing method of the reflection type TFT substrate concerning 2nd embodiment of this invention is shown. It is the schematic for demonstrating the process using the 3rd halftone mask of the manufacturing method of the reflection type TFT substrate concerning 2nd embodiment of this invention, (a) is for reflection metal layer film-forming / protection Insulating film formation / third resist coating / halftone exposure / development sectional view, (b) shows a fourth etched sectional view. It is the schematic for demonstrating the process using the 3rd halftone mask of the manufacturing method of the reflection type TFT substrate concerning 2nd embodiment of this invention, (a) is re-formation of the 3rd resist. (B) is a sectional view of the fifth etching / third resist stripped. In the manufacturing method of the reflective TFT substrate concerning 2nd embodiment of this invention, the schematic plan view of the principal part of the reflective TFT substrate after a 3rd resist is peeled is shown. The schematic flowchart figure for demonstrating the manufacturing method of the reflection type TFT substrate concerning 3rd embodiment of this invention is shown. It is the schematic for demonstrating the process using the 4th mask of the manufacturing method of the reflection type TFT substrate concerning 3rd embodiment of this invention, (a) is film-forming of a protective insulating film / 4th FIG. 5B is a cross-sectional view after resist coating / exposure / development, and FIG. 5B is a cross-sectional view after fifth etching / fourth resist peeling. In the manufacturing method of the reflective TFT substrate concerning 3rd embodiment of this invention, the schematic plan view of the principal part of the reflective TFT substrate after a 4th resist is peeled is shown. The schematic flowchart figure for demonstrating the manufacturing method of the reflection type TFT substrate concerning 4th embodiment of this invention is shown. It is the schematic for demonstrating the process using the 3rd halftone mask of the manufacturing method of the reflection type TFT substrate concerning 4th embodiment of this invention, (a) is reflective metal layer film-forming / metal layer Protective oxide transparent conductor layer deposition / protective insulating film deposition / third resist coating / halftone exposure / development cross-sectional view, (b) shows a fourth etched cross-sectional view Yes. It is the schematic for demonstrating the process using the 3rd halftone mask of the manufacturing method of the reflection type TFT substrate concerning 4th embodiment of this invention, (a) is re-formation of the 3rd resist. (B) is a sectional view of the fifth etching / third resist stripped. In the manufacturing method of the reflective TFT substrate concerning 4th embodiment of this invention, the schematic plan view of the principal part of the reflective TFT substrate after a 3rd resist is peeled is shown. The schematic flowchart figure for demonstrating the manufacturing method of the reflection type TFT substrate concerning 5th embodiment of this invention is shown. It is the schematic for demonstrating the process using the 3rd halftone mask of the manufacturing method of the reflection type TFT substrate concerning 5th embodiment of this invention, (a) is oxide transparent conductor layer film-forming / Reflective metal layer formation / Metal layer protection oxide transparent conductor layer formation / Protection insulation film formation / Third resist coating / Halftone exposure / Developed sectional view, (b) is the fourth FIG. 4 shows an etched cross-sectional view of the. It is the schematic for demonstrating the process using the 3rd halftone mask of the manufacturing method of the reflection type TFT substrate concerning 5th embodiment of this invention, (a) is re-formation of the 3rd resist. (B) is a sectional view of the fifth etching / third resist stripped. In the manufacturing method of the reflective TFT substrate concerning 5th embodiment of this invention, the schematic plan view of the principal part of the reflective TFT substrate after a 3rd resist is peeled is shown. It is the schematic for demonstrating the manufacturing method of the TFT substrate concerning a prior art example, (a) is sectional drawing in which the gate electrode was formed, (b) is sectional drawing in which the etch stopper was formed, (c). Is a cross-sectional view in which a source electrode and a drain electrode are formed, (d) is a cross-sectional view in which an interlayer insulating film is formed, and (e) is a cross-sectional view in which a transparent electrode is formed.

Explanation of symbols

1,1 ′ TFT substrate 1a, 1b, 1c, 1d, 1e Reflective TFT substrate 10 Glass substrate 20 Metal layer 25 Gate wiring pad 26 Metal layer protecting oxide transparent conductor layer 30 Gate insulating film 40 n-type oxide semiconductor Layer 41 First resist 42 First halftone mask 44 Channel portion 50 Interlayer insulating film 51 Second resist 52 Second mask 60 Oxide transparent conductor layer 60a Reflective metal layers 61, 61a ′ Third resist 62 , 62a ′ Third mask 63 Source electrode 64 Drain electrode 65 Source wiring 66 Drain wiring 67 Pixel electrode 68 Drain wiring pad 69 Oxide transparent conductor layers 70, 70b, 70c for metal layer protection Insulating films 71, 71c for protection Fourth resist 71b, 71d Third resist 72, 72c Fourth mask 72b, 72d Third half toe Mask 210 Glass substrate 212 Gate electrode 213 Gate insulating film 214 α-Si: H (i) film 215 Etch stopper 216 α-Si: H (n) film 217a Source electrode 217b Drain electrode 218 Interlayer insulating film 218a Opening 219 Transparent electrode 250 Gate wiring pad portions 251, 631, 641 Openings 721b, 721d Halftone mask portions

Claims (23)

A substrate,
A gate electrode and a gate wiring formed above the substrate;
A gate insulating film formed above the gate electrode and the gate wiring;
An oxide layer formed above the gate electrode and above the gate insulating film;
A source electrode opening and a drain electrode are formed on the sides of the gate electrode and the gate wiring, above and on the side of the oxide layer, and further separated by the channel portion of the oxide layer, respectively. An interlayer insulating film in which an opening is formed;
A source electrode formed in the source electrode opening;
And a drain electrode formed in the drain electrode opening.   2. The TFT substrate according to claim 1, wherein the source electrode and the drain electrode are made of the same conductor layer, and the conductor layer is made of metal.   3. The TFT substrate according to claim 1, wherein the source electrode and the drain electrode are made of the same conductor layer, and the conductor layer also serves as at least a pixel electrode.   The TFT substrate according to claim 1, wherein the oxide layer is an n-type oxide semiconductor layer.   5. The TFT substrate according to claim 1, wherein the oxide layer is formed at a predetermined position corresponding to the channel portion, the source electrode, and the drain electrode.   The upper surface of the substrate is covered with a protective insulating film, and the protective insulating film has openings at positions corresponding to pixel electrodes, source / drain wiring pads, and gate wiring pads. The TFT substrate according to any one of 1 to 5. A substrate,
A gate electrode and a gate wiring which are formed above the substrate and are insulated by covering an upper surface with a gate insulating film and a side surface with an interlayer insulating film;
An oxide layer formed above the gate insulating film above the gate electrode;
A reflective metal layer formed above the oxide layer and separated by a channel portion;
A reflective TFT substrate, comprising: a channel guard formed above the channel portion and protecting the channel portion.   8. The reflective TFT substrate according to claim 7, wherein the channel guard is made of the interlayer insulating film, and a drain electrode and a source electrode are respectively formed in a pair of openings of the interlayer insulating film.   9. The reflective TFT substrate according to claim 7, wherein the reflective metal layer also serves as at least a pixel electrode.   The reflective TFT substrate according to any one of claims 7 to 9, wherein the oxide layer is an n-type oxide semiconductor layer.   11. The reflective TFT substrate according to claim 7, wherein the oxide layer is formed at a predetermined position corresponding to the channel portion, the source electrode, and the drain electrode.   The upper surface of the substrate is covered with a protective insulating film, and the protective insulating film has openings at positions corresponding to pixel electrodes, source / drain wiring pads, and gate wiring pads. The reflective TFT substrate according to any one of 7 to 11.   The reflective TFT substrate includes a reflective metal layer and / or a metal thin film, and has an oxide transparent conductor layer for protecting the metal layer that protects the reflective metal layer and / or the metal thin film. 13. The reflective TFT substrate according to any one of 12 above.   14. The reflective TFT substrate according to claim 7, wherein an energy gap of the oxide layer is 3.0 eV or more.   15. The reflective TFT substrate according to claim 7, wherein the reflective metal layer is a thin film made of aluminum, silver or gold, or an alloy layer containing aluminum, silver or gold. . A step of laminating a gate electrode and a thin film for wiring serving as a gate wiring, a gate insulating film, an oxide layer, and a first resist above the substrate;
Forming the first resist into a predetermined shape by halftone exposure using a first halftone mask;
Etching the gate electrode / wiring thin film, gate insulating film and oxide layer to form the gate electrode and gate wiring;
Re-forming the first resist into a predetermined shape;
Etching the oxide layer to form a channel portion;
Laminating an interlayer insulating film and a second resist;
Using the second mask to form the second resist into a predetermined shape;
The interlayer insulating film is etched to form a source electrode opening and a drain electrode opening in a portion to be a source electrode and a drain electrode, and the interlayer insulating film and the gate insulating film are etched to form a gate wiring pad. Forming a gate wiring pad opening in the portion to be,
Laminating a conductor layer and a third resist;
Using a third mask to form the third resist in a predetermined shape;
And etching the conductive layer to form a source electrode, a drain electrode, a source wiring, a drain wiring, a pixel electrode, and a gate wiring pad. A step of laminating a gate electrode and a thin film for wiring serving as a gate wiring, a gate insulating film, an oxide layer, and a first resist above the substrate;
Forming the first resist into a predetermined shape by halftone exposure using a first halftone mask;
Etching the gate electrode / wiring thin film, gate insulating film and oxide layer to form the gate electrode and gate wiring;
Re-forming the first resist into a predetermined shape;
Etching the oxide layer to form a channel portion;
Laminating an interlayer insulating film and a second resist;
Using the second mask to form the second resist into a predetermined shape;
The interlayer insulating film is etched to form a source electrode opening and a drain electrode opening in a portion to be a source electrode and a drain electrode, and the interlayer insulating film and the gate insulating film are etched to form a gate wiring pad. Forming a gate wiring pad opening in the portion to be,
Laminating a conductor layer and a third resist;
Using a third mask to form the third resist in a predetermined shape;
Etching the conductor layer to form a source electrode, a drain electrode, a source wiring, a drain wiring, a pixel electrode, and a gate wiring pad;
Laminating a protective insulating film and a fourth resist;
Forming the fourth resist into a predetermined shape;
Etching the protective insulating film to expose the source / drain wiring pads, the pixel electrodes, and the gate wiring pads. A step of laminating a gate electrode and a thin film for wiring serving as a gate wiring, a gate insulating film, an oxide layer, and a first resist above the substrate;
Forming the first resist into a predetermined shape by halftone exposure using a first halftone mask;
Etching the gate electrode / wiring thin film, gate insulating film and oxide layer to form the gate electrode and gate wiring;
Re-forming the first resist into a predetermined shape;
Etching the oxide layer to form a channel portion;
Laminating an interlayer insulating film and a second resist;
Using the second mask to form the second resist into a predetermined shape;
The interlayer insulating film is etched to form a source electrode opening and a drain electrode opening in a portion to be a source electrode and a drain electrode, and the interlayer insulating film and the gate insulating film are etched to form a gate wiring pad. Forming a gate wiring pad opening in the portion to be,
Laminating a reflective metal layer and a third resist;
Using a third mask to form the third resist in a predetermined shape;
Etching the reflective metal layer to form a source electrode, a drain electrode, a source wiring, a drain wiring, a pixel electrode, and a gate wiring pad. A step of laminating a gate electrode and a thin film for wiring serving as a gate wiring, a gate insulating film, an oxide layer, and a first resist above the substrate;
Forming the first resist into a predetermined shape by halftone exposure using a first halftone mask;
Etching the gate electrode / wiring thin film, gate insulating film and oxide layer to form the gate electrode and gate wiring;
Re-forming the first resist into a predetermined shape;
Etching the oxide layer to form a channel portion;
Laminating an interlayer insulating film and a second resist;
Using the second mask to form the second resist into a predetermined shape;
The interlayer insulating film is etched to form a source electrode opening and a drain electrode opening in a portion to be a source electrode and a drain electrode, and the interlayer insulating film and the gate insulating film are etched to form a gate wiring pad. Forming a gate wiring pad opening in the portion to be,
Laminating a reflective metal layer, a protective insulating film and a third resist;
Using the third halftone mask, forming the third resist into a predetermined shape by halftone exposure;
Etching the reflective metal layer and the protective insulating film to form a source electrode, a drain electrode, a source wiring, a drain wiring, a pixel electrode, and a gate wiring pad;
Re-forming the third resist into a predetermined shape;
Etching the protective insulating film to expose the source / drain wiring pads, the pixel electrodes, and the gate wiring pads. A method of manufacturing a reflective TFT substrate, comprising: A step of laminating a gate electrode and a thin film for wiring serving as a gate wiring, a gate insulating film, an oxide layer, and a first resist above the substrate;
Forming the first resist into a predetermined shape by halftone exposure using a first halftone mask;
Etching the gate electrode / wiring thin film, gate insulating film and oxide layer to form the gate electrode and gate wiring;
Re-forming the first resist into a predetermined shape;
Etching the oxide layer to form a channel portion;
Laminating an interlayer insulating film and a second resist;
Using the second mask to form the second resist into a predetermined shape;
The interlayer insulating film is etched to form a source electrode opening and a drain electrode opening in a portion to be a source electrode and a drain electrode, and the interlayer insulating film and the gate insulating film are etched to form a gate wiring pad. Forming a gate wiring pad opening in the portion to be,
Laminating a reflective metal layer and a third resist;
Using a third mask to form the third resist in a predetermined shape;
Etching the reflective metal layer to form a source electrode, a drain electrode, a source wiring, a drain wiring, a pixel electrode and a gate wiring pad;
Laminating a protective insulating film and a fourth resist;
Forming the fourth resist into a predetermined shape;
Etching the protective insulating film to expose the source / drain wiring pads, the pixel electrodes, and the gate wiring pads. A method of manufacturing a reflective TFT substrate, comprising:   21. The method of manufacturing a reflective TFT substrate according to claim 18, wherein an oxide conductor layer is laminated between the oxide layer and the reflective metal layer.   The method for producing a reflective TFT substrate according to any one of claims 18 to 21, wherein an oxide transparent conductor layer for protecting a metal layer is laminated above the reflective metal layer.   23. The gate electrode / wiring thin film has a metal layer, and an oxide transparent conductor layer for protecting the metal layer is laminated above the metal layer. The manufacturing method of the reflection type TFT substrate of description.

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