WO2014077201A1 - Method for manufacturing semiconductor device and display device - Google Patents

Method for manufacturing semiconductor device and display device Download PDF

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Publication number
WO2014077201A1
WO2014077201A1 PCT/JP2013/080295 JP2013080295W WO2014077201A1 WO 2014077201 A1 WO2014077201 A1 WO 2014077201A1 JP 2013080295 W JP2013080295 W JP 2013080295W WO 2014077201 A1 WO2014077201 A1 WO 2014077201A1
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film
metal layer
oxide semiconductor
layer
insulating film
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PCT/JP2013/080295
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French (fr)
Japanese (ja)
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一秀 冨安
宮本　忠芳
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor layer and a display device having the semiconductor device manufactured by such a manufacturing method.
  • An active matrix substrate used for a liquid crystal display device, an organic EL display device, or the like includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
  • a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
  • TFT thin film transistor
  • amorphous silicon TFT a TFT having an amorphous silicon film as an active layer
  • polycrystalline silicon TFT a TFT having a polycrystalline silicon film as an active layer
  • oxide semiconductor TFT in place of amorphous silicon or polycrystalline silicon as a material for the active layer of a TFT.
  • a TFT is referred to as an “oxide semiconductor TFT”.
  • An oxide semiconductor has higher mobility than amorphous silicon. For this reason, the oxide semiconductor TFT can operate at a higher speed than the amorphous silicon TFT.
  • the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area.
  • Patent Document 1 discloses a method for manufacturing an oxide semiconductor TFT having a channel etch type bottom gate structure.
  • a source electrode and a drain electrode are formed from a conductive film by patterning the conductive film and the oxide semiconductor film in a photolithography process using a multi-tone mask, and an oxide is formed. A part of the semiconductor film is removed to form a recess (finally a channel region) in the oxide semiconductor film.
  • a multi-tone mask the number of photomasks in the TFT manufacturing process can be reduced.
  • a multi-tone mask is a photomask including regions having different transmittances of three levels (minimum value, maximum value, and intermediate value therebetween) or more. Typically, the minimum value of transmittance is zero.
  • a multi-tone mask is sometimes called a halftone mask or a graytone mask.
  • the conductive film for forming the source electrode and the drain electrode and the oxide semiconductor film are patterned using the same resist mask (formed using a multi-tone mask). Therefore, an oxide semiconductor film exists under the conductive film except for a region where a depression is formed in the oxide semiconductor film.
  • an oxide semiconductor layer exists under the conductive film. Accordingly, at the place where the source metal layer and the gate metal layer are electrically connected (hereinafter referred to as “source / gate contact portion” or “S / G contact portion”), the source metal layer and the gate metal layer are An oxide semiconductor layer is present between them.
  • a main object of the present invention is to provide a semiconductor device having a structure in which an oxide semiconductor layer does not exist between a source metal layer and a gate metal layer at a place where the source metal layer and the gate metal layer are connected. It is to provide a method of manufacturing without increasing the number.
  • a method of manufacturing a semiconductor device includes a step (a) of forming a gate metal layer by depositing a first conductive film on a substrate and patterning the first conductive film, and the gate metal layer A step (b) of depositing a first insulating film on the substrate, a step (c) of depositing an oxide semiconductor film on the first insulating film, and the oxide semiconductor film and the first insulating film. Forming a first contact hole penetrating through and exposing a part of the surface of the gate metal layer; and forming a second conductive film on the oxide semiconductor film and the part of the gate metal layer.
  • the oxide semiconductor layer having a predetermined pattern, and the first contact hole Comprising the step (e) forming a source metal layer having a contact portion in contact with said gate metal layer within.
  • a step (f) of forming a second insulating film on the oxide semiconductor layer and the source metal layer, and penetrating the second insulating film and on the part of the gate metal layer A step (g) of forming a second contact hole exposing a part of the surface of the formed source metal layer.
  • the step (d) includes a step of wet etching the oxide semiconductor film and a step of dry etching the first insulating film.
  • the oxide semiconductor film includes an In—Ga—Zn—O-based oxide.
  • a display device includes a semiconductor device manufactured by any one of the semiconductor device manufacturing methods described above and a display medium layer.
  • a method for manufacturing a semiconductor device having a structure in which an oxide semiconductor layer does not exist between a source metal layer and a gate metal layer at a location where the source metal layer and the gate metal layer are connected without increasing the number of photomasks. Can be provided.
  • FIGS. 7A to 7C are cross-sectional views for explaining an example of a manufacturing method of the semiconductor device 100A according to the embodiment of the present invention. It is typical sectional drawing of the liquid crystal display device 100 provided with the semiconductor device 100B by embodiment of this invention.
  • (A)-(d) is sectional drawing for demonstrating an example of the manufacturing method of 200 A of semiconductor devices by a comparative example, respectively.
  • (A)-(d) is sectional drawing for demonstrating an example of the manufacturing method of 200 A of semiconductor devices by a comparative example, respectively.
  • the semiconductor device 100A exemplified here is a TFT substrate 100A having a plurality of TFTs on the substrate.
  • the TFT substrate can be used in a display device such as a liquid crystal display device or an organic EL display device.
  • An example of a display device according to an embodiment of the present invention will be described later with reference to FIG.
  • FIG. 1 and FIG. 2 also show a TFT portion, a location where the source metal layer and the gate metal layer are electrically connected (“S / G contact portion”), and a terminal portion in the TFT substrate 100A. ing.
  • the gate metal layer refers to a layer including electrodes, wirings, terminals, and the like formed by patterning a conductive film that forms a gate electrode and a gate bus line.
  • lines for example, CS bus lines, CS electrodes, and the like may be included.
  • the source metal layer is a layer including electrodes, wirings, terminals, and the like formed by patterning a conductive film that forms a source electrode, a drain electrode, and a source bus line.
  • a drain lead-out wiring / electrode (a wiring / electrode facing the CS bus line or the CS electrode and forming a CS capacitor) is included.
  • the S / G contact portion is formed to connect jumper wiring (wiring straddling other wiring).
  • jumper wiring wiring straddling other wiring.
  • the conductive film forming the gate metal layer and the source metal layer is not limited to a metal film, and may be, for example, a metal nitride film, a single layer film, or a laminated film. Good.
  • the structure in which the source metal layer and the gate metal layer are connected to each other can also be formed in the gate terminal portion and / or the source terminal portion.
  • the terminals shown in the following figures are, for example, gate terminals or source terminals.
  • the laminated structure of the gate terminal and the source terminal need not be the same as each other, or the laminated structures may be the same as or different from the laminated structure of the S / G contact portion. Good.
  • a first conductive film (also referred to as a gate metal film) 12 is deposited on a substrate 11, and the first conductive film 12 is patterned to form a gate metal layer 12.
  • the first conductive film 12 and the gate metal layer 12 formed by patterning the first conductive film 12 are denoted by the same reference numerals.
  • the first conductive film 12 is deposited on almost the entire surface of the substrate 11.
  • the thickness of the first conductive film is, for example, not less than 50 nm and not more than 300 nm.
  • the gate metal layer 12 includes a gate electrode 12g, a gate contact layer 12c, and a gate terminal layer 12t.
  • the gate metal layer 12 may include a gate bus line formed integrally with the gate electrode 12g and a CS bus line formed integrally with the CS electrode and the CS electrode (all not shown).
  • a glass substrate for example, a glass substrate, a silicon substrate, or a heat-resistant plastic substrate (also referred to as a resin substrate) can be used.
  • a material for the plastic substrate polyethylene terephthalate (PET), polyethylene naphthalate substrate, polyethersulfone, acrylic, polyimide, or the like can be used.
  • PET polyethylene terephthalate
  • polyethylene naphthalate substrate polyethylene naphthalate substrate
  • polyethersulfone acrylic, polyimide, or the like
  • a glass substrate is used.
  • the material of the first conductive film 12 examples include metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu), or these metals.
  • An alloy containing at least one or a metal nitride thereof can be used.
  • the first conductive film 12 may be not only a single layer film formed from the above material but also a laminated film formed from the above material.
  • the first conductive film 12 film thickness: 300 nm
  • the first conductive is performed using a photolithography process.
  • a gate metal layer 12 including a gate electrode and the like is formed.
  • a first insulating film (also referred to as a gate insulating film) 14 is deposited on the gate metal layer 12.
  • the first insulating film 14 is also deposited on almost the entire surface of the substrate 11.
  • the material of the first insulating film 14 is, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y , x> y), silicon nitride oxide (SiN x O y , x>) y) can be used.
  • the first insulating film 14 may also be a single layer film or a laminated film.
  • the lower insulating film for example, silicon nitride (SiN x) or silicon nitride oxide (SiN x O y, formed using x> y)
  • the upper insulating film for example, silicon oxide (SiO x) is preferably formed using a silicon oxynitride (SiO x N y, x> y).
  • a rare gas such as argon
  • a dense insulating film can be deposited at a relatively low temperature.
  • a dense insulating film can have an effect of reducing gate leakage current.
  • a silicon nitride film having a thickness of 100 nm to 400 nm is formed as a lower insulating film by a sputtering method using SiH 4 and NH 3 as a reaction gas, and a thickness of the upper insulating film is formed thereon.
  • an oxide semiconductor film 16 is deposited on the first insulating film 14.
  • the oxide semiconductor film 16 is also deposited on almost the entire surface of the substrate 11.
  • the thickness of the oxide semiconductor film 16 is, for example, not less than 30 nm and not more than 100 nm.
  • Examples of the material of the oxide semiconductor film 16 include InGaO 3 (ZnO) 5 , magnesium zinc oxide (Mg x Zn 1-x O), cadmium zinc oxide (Cd x Zn 1-x O), cadmium oxide (CdO), An In—Ga—Zn—O-based oxide semiconductor can be used.
  • In—Ga—Zn—O is an oxide of In (indium), Ga (gallium), or Zn (zinc), and may be either amorphous or crystalline.
  • a crystalline In—Ga—Zn—O film in which the c-axis is oriented substantially perpendicular to the film surface is preferable.
  • Such a crystal structure of the In—Ga—Zn—O film is disclosed in, for example, Japanese Patent Laid-Open No. 2012-134475.
  • the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference.
  • ZnO to which one or more impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element or Group 17 element are added, or an amorphous state, a polycrystalline state, or A microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can also be used.
  • a first resist mask 42 having first openings 42a and 42b exposing a part of the surface of the oxide semiconductor film 16 is formed.
  • the two first openings 42a and 42b of the first resist mask 42 are respectively a first contact hole 14a for forming an S / G contact portion and a first contact hole for forming a terminal portion.
  • 14b is an opening for forming 14b.
  • the first resist mask 42 is formed by a known method using a known photoresist and a photomask having a predetermined pattern. The photoresist may be negative or positive.
  • the first contact holes 14a and 14b are formed by using the first resist mask 42 having the first openings 42a and 42b as shown in FIG. It is formed by etching the film 14. Etching of the oxide semiconductor film 16 is performed by, for example, wet etching, and etching of the first insulating film 14 is performed by, for example, dry etching.
  • the formation of the first resist mask 42 using a photoresist and the formation of the first contact holes 14a and 14b by etching using the first resist mask 42 are called a photolithography process.
  • a second conductive film (also referred to as a source metal film) 18 is deposited on the oxide semiconductor film 16 and the part of the gate metal layer 12.
  • the second conductive film 18 is also deposited on almost the entire surface of the substrate 11.
  • the second conductive film 18 contacts the gate metal layer 12 in the first contact holes 14a and 14b.
  • the S / G contact portion is formed from the portion where the second conductive film 18 is in contact with the gate contact layer 12c in the first contact hole 14a, and the second conductive film 18 is in contact with the gate terminal layer 12t in the first contact hole 14b.
  • a terminal portion is formed from the formed portion.
  • the second conductive film 18 As a material of the second conductive film 18, a metal such as aluminum (Al), molybdenum (Mo), copper (Cu), titanium (Ti), an alloy including at least one of these, or a metal nitride thereof is used. Can be used. Further, the second conductive film 18 may be not only a single layer film formed from the above material but also a laminated film formed from the above material. Here, for example, the second conductive film 18 (film thickness: 400 nm) having a stacked structure of an aluminum (Al) film and a titanium (Ti) film is formed by a sputtering method.
  • Al aluminum
  • Mo molybdenum
  • Cu copper
  • Ti titanium
  • the oxide semiconductor film 16 and the second conductive film 18 are patterned by a photolithography process using a multi-tone mask to thereby form an oxide semiconductor having a predetermined pattern.
  • a source metal layer 18 having a contact portion in contact with the gate metal layer 12 in the layer 16 and the first contact hole 14a is formed.
  • the second resist mask 44 shown in FIG. 2B has second openings 44a and 44b and a recess 44c.
  • a region exposed at three different exposure amounts minimum value, maximum value, and intermediate value therebetween
  • the second resist mask 44 can be formed by forming and developing this.
  • the film thickness of the region with the largest exposure amount is the largest, and the openings 44a and 44b are formed in the region with the smallest exposure amount.
  • a recess 44c is formed on the surface.
  • the film thickness of the region with the smallest exposure amount is the largest, the openings 44a and 44b are formed in the region with the maximum exposure amount, and the recess 44c is formed in the region with the intermediate exposure amount.
  • the oxide semiconductor layer 16a having a predetermined pattern and the gate metal layer 12 (12c) in the first contact hole 14a.
  • the source metal layer 18 having a contact portion (which constitutes an S / G contact portion) in contact with the first contact hole 14b and a contact portion (which constitutes a terminal portion) which is in contact with the gate metal layer (12t) in the first contact hole 14b.
  • the source metal film 18 is removed by etching below the recess 44 c of the second resist mask 44, and the source electrode 18 s and the drain electrode 18 d are formed from the source metal film 18.
  • a region where the source metal film 18 on the oxide semiconductor layer 16a is removed becomes a channel region, and the TFT 10A is obtained.
  • the source metal portion 18c of the S / G contact portion and the source metal portion 18t of the terminal portion each have a predetermined pattern.
  • the cross-sectional structure is illustrated focusing on the laminated structure, but for example, the source metal portion 18c of the S / G contact portion can be formed integrally with the source electrode 18s and the source bus line (not shown). Further, the source metal portion 18t of the terminal portion may be formed integrally with the source electrode 18s and the source bus line (not shown). At this time, the terminal portion is a source terminal portion.
  • the gate terminal layer 12c of the terminal portion is formed integrally with the gate electrode 12g and the gate bus line (not shown)
  • the source metal portion 18t may be formed in an island shape.
  • a second insulating film 22 is formed on the oxide semiconductor layer 16 and the source metal layer 18, penetrates through the second insulating film 22, and covers a part (12 t) of the gate metal layer 12.
  • a second contact hole 22a that exposes a part of the surface of the source metal layer 18 is formed.
  • silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y , x> y), silicon nitride oxide (SiN x O y , x> y) ), TEOS (Tetraethyl orthosilicate) and other inorganic insulating materials and organic insulating materials can be used.
  • a photosensitive resin is used as the organic insulating material
  • the contact hole 22a that exposes the source metal portion 18t of the terminal portion can be formed without using a photoresist.
  • the surface of the substrate 11 can be planarized.
  • the second insulating film 22 may be not only a single layer film formed from the above material but also a laminated film formed from the above material.
  • a silicon oxide (SiO x ) film having a thickness of 5 nm to 500 nm is formed as a lower insulating film
  • a silicon nitride (SiN x ) film having a thickness of 5 nm to 500 nm is formed thereon as an upper insulating film.
  • the laminated film on which the film is formed is used as the second insulating film 22.
  • a step of heating the entire surface of the substrate 11 for example, 350 ° C.
  • the TFT substrate 100A is obtained.
  • a pixel electrode or the like is further formed on the TFT substrate 100A as necessary, and can be used, for example, as a TFT substrate of a liquid crystal display device.
  • the structure of the liquid crystal display device 100 according to the embodiment of the present invention will be described with reference to FIG.
  • the liquid crystal display device 100 includes a semiconductor device (TFT substrate) 100B according to an embodiment of the present invention.
  • the TFT substrate 100B is obtained by forming the pixel electrode 24 on the second insulating film 22 of the TFT substrate 100A shown in FIG.
  • the contact hole 22b for electrically connecting the pixel electrode 24 to the drain electrode 18d can be formed in the same process as the contact hole 22a shown in FIG. FIG. 3 schematically shows only the TFT 10A and the vicinity thereof for the sake of simplicity.
  • the liquid crystal display device 100 includes a TFT substrate 100B, a substrate (for example, a glass substrate) 61, and a liquid crystal layer 82.
  • a counter electrode 74 is formed on the liquid crystal layer 82 side of the substrate 61.
  • a voltage is applied to the liquid crystal layer 82 existing between the pixel electrode 24 and the counter electrode 74.
  • An alignment film (for example, a vertical alignment film) is formed on the pixel electrode 24 and the counter electrode 74 on the liquid crystal layer 82 side as necessary.
  • the liquid crystal display device 100 is, for example, a vertical alignment mode (VA mode) liquid crystal display device.
  • VA mode vertical alignment mode
  • the liquid crystal display device is not limited thereto, and has, for example, a pixel electrode and a counter electrode on a TFT substrate, for example, an In-Plane Switching (IPS) mode or a Ringe Field Switching (FFS).
  • IPS In-Plane Switching
  • FFS Ringe Field Switching
  • the present invention can also be applied to a liquid crystal display device in a horizontal electric field mode such as a mode. Since the structure of the TFT of the IPS mode or FFS mode liquid crystal display device is well known, description thereof is omitted.
  • the display device according to the embodiment of the present invention is not limited to the liquid crystal display device, and is widely applied to display devices having a TFT substrate such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device.
  • EL organic electroluminescence
  • the TFT substrate 200A of the comparative example has an oxide semiconductor layer 16 between the source metal layer 18 and the gate metal layer 12 in the S / G contact portion and the terminal portion. However, it is different from the TFT substrate 100A.
  • a first conductive film (gate metal film) 12 is deposited on a substrate 11 and the first conductive film 12 is patterned to form a gate metal layer 12.
  • a first insulating film (gate insulating film) 14 is deposited on the gate metal layer 12.
  • a first resist mask 52 having first openings 52a and 52b exposing a part of the surface of the first insulating film 14 is formed.
  • the two first openings 52a and 52b of the first resist mask 52 are respectively formed in the first contact hole 14a and the first contact hole for forming the terminal portion in order to form the S / G contact portion.
  • 14b is an opening for forming 14b.
  • the first contact holes 14a and 14b are formed by etching the first insulating film 14 using the first resist mask 52.
  • the first resist mask 52 is formed by etching the first insulating film 14 using the first resist mask 52.
  • an oxide semiconductor film 16 and a second conductive film 18 are deposited on the first insulating film 14.
  • the oxide semiconductor film 16 contacts the gate metal layer 12 in the first contact holes 14a and 14b.
  • An S / G contact portion is formed from a portion where the oxide semiconductor film 16 is in contact with the gate contact layer 12c in the first contact hole 14a, and the oxide semiconductor film 16 is in contact with the gate terminal layer 12t in the first contact hole 14b.
  • a terminal portion is formed from the formed portion.
  • the second conductive film 18 necessarily exists on the oxide semiconductor film 16.
  • the oxide semiconductor film 16 and the second conductive film 18 are patterned by a photolithography process using a multi-tone mask, thereby having an oxide semiconductor having a predetermined pattern. Layer 16 and source metal layer 18 are formed.
  • the oxide semiconductor layer 16a and the source metal layer 18 having a predetermined pattern are formed as shown in FIG. 5C.
  • the source metal layer 18 includes a contact portion (which constitutes an S / G contact portion) in contact with the gate metal layer 12 (12c) in the first contact hole 14a via the oxide semiconductor layer 16, and a first contact hole. 14b has a contact portion (constituting a terminal portion) in contact with the gate metal layer (12t).
  • the source metal film 18 is removed by etching under the recess 54 c of the second resist mask 54, and the source electrode 18 s and the drain electrode 18 d are formed from the source metal film 18.
  • a region where the source metal film 18 on the oxide semiconductor layer 16a is removed becomes a channel region, and a TFT is obtained.
  • both the source metal film 18 and the oxide semiconductor film 16 are removed, and the surface of the first insulating film 14 is exposed.
  • the source metal portion 18c of the S / G contact portion and the source metal portion 18t of the terminal portion each have a predetermined pattern.
  • a second insulating film 22 is formed on the oxide semiconductor layer 16 and the source metal layer 18, penetrates through the second insulating film 22, and covers a part (12 t) of the gate metal layer 12.
  • a second contact hole 22a that exposes a part of the surface of the source metal layer 18 is formed.
  • the TFT substrate 200A is obtained.
  • the manufacturing method of the TFT substrate 100A of the above-described embodiment includes a step of patterning the oxide semiconductor layer and the source metal layer by a photolithography process using a multi-tone mask, and the TFT substrate of the comparative example Compared with the manufacturing method of 200A, the number of photomasks has not increased.
  • Embodiments of the present invention can be widely applied to various semiconductor devices having an oxide semiconductor TFT and an oxide semiconductor TFT.
  • circuit boards such as active matrix substrates, liquid crystal display devices, display devices such as organic electroluminescence (EL) display devices and inorganic electroluminescence display devices, imaging devices such as image sensor devices, image input devices, fingerprint readers, etc. It can also be applied to other electronic devices.
  • circuit boards such as active matrix substrates, liquid crystal display devices, display devices such as organic electroluminescence (EL) display devices and inorganic electroluminescence display devices, imaging devices such as image sensor devices, image input devices, fingerprint readers, etc. It can also be applied to other electronic devices.
  • EL organic electroluminescence
  • imaging devices such as image sensor devices, image input devices, fingerprint readers, etc. It can also be applied to other electronic devices.

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  • Thin Film Transistor (AREA)

Abstract

A method for manufacturing a semiconductor device (100A) comprises: a step for forming a gate metal layer (12); a step for depositing a first insulating film (14) on the gate metal layer (12); a step for depositing an oxide semiconductor film (16) on the first insulating film; a step for forming a first contact hole (14a) which penetrates through the oxide semiconductor film and the first insulating film and exposes a part of the surface of the gate metal layer; and a step for forming an oxide semiconductor layer having a predetermined pattern and a source metal layer (18) having a contact part that is in contact with the gate metal layer in the first contact hole by depositing a second conductive film (18) on the oxide semiconductor film and the part of the gate metal layer and patterning the oxide semiconductor film and the second conductive film by a photolithography process using a multi-tone mask.

Description

半導体装置の製造方法および表示装置Semiconductor device manufacturing method and display device
　本発明は、酸化物半導体層を備える半導体装置の製造方法およびそのような製造方法で製造された半導体装置を有する表示装置に関する。 The present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor layer and a display device having the semiconductor device manufactured by such a manufacturing method.
　液晶表示装置や有機ＥＬ表示装置等に用いられるアクティブマトリクス基板は、画素毎に薄膜トランジスタ（Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒ；以下、「ＴＦＴ」）などのスイッチング素子を備えている。このようなスイッチング素子としては、従来から、アモルファスシリコン膜を活性層とするＴＦＴ（以下、「アモルファスシリコンＴＦＴ」）や多結晶シリコン膜を活性層とするＴＦＴ（以下、「多結晶シリコンＴＦＴ」）が広く用いられている。 2. Description of the Related Art An active matrix substrate used for a liquid crystal display device, an organic EL display device, or the like includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel. Conventionally, as such a switching element, a TFT having an amorphous silicon film as an active layer (hereinafter referred to as “amorphous silicon TFT”) or a TFT having a polycrystalline silicon film as an active layer (hereinafter referred to as “polycrystalline silicon TFT”). Is widely used.
　近年、ＴＦＴの活性層の材料として、アモルファスシリコンや多結晶シリコンに代わって、酸化物半導体を用いることが提案されている。このようなＴＦＴを「酸化物半導体ＴＦＴ」と称する。酸化物半導体は、アモルファスシリコンよりも高い移動度を有している。このため、酸化物半導体ＴＦＴは、アモルファスシリコンＴＦＴよりも高速で動作することが可能である。また、酸化物半導体膜は、多結晶シリコン膜よりも簡便なプロセスで形成されるため、大面積が必要とされる装置にも適用できる。 Recently, it has been proposed to use an oxide semiconductor in place of amorphous silicon or polycrystalline silicon as a material for the active layer of a TFT. Such a TFT is referred to as an “oxide semiconductor TFT”. An oxide semiconductor has higher mobility than amorphous silicon. For this reason, the oxide semiconductor TFT can operate at a higher speed than the amorphous silicon TFT. In addition, since the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area.
　特許文献１には、チャネルエッチ型のボトムゲート構造を有する酸化物半導体ＴＦＴの製造方法が開示されている。特許文献１に開示された方法は、多階調マスクを用いたフォトリソグラフィ工程で、導電膜および酸化物半導体膜をパターニングすることによって、導電膜からソース電極およびドレイン電極を形成するとともに、酸化物半導体膜の一部を除去して酸化物半導体膜に凹部（最終的に、チャネル領域となる）を形成する。多階調マスクを用いることによって、ＴＦＴの製造プロセスにおけるフォトマスクの枚数を低減することができる。 Patent Document 1 discloses a method for manufacturing an oxide semiconductor TFT having a channel etch type bottom gate structure. In the method disclosed in Patent Document 1, a source electrode and a drain electrode are formed from a conductive film by patterning the conductive film and the oxide semiconductor film in a photolithography process using a multi-tone mask, and an oxide is formed. A part of the semiconductor film is removed to form a recess (finally a channel region) in the oxide semiconductor film. By using a multi-tone mask, the number of photomasks in the TFT manufacturing process can be reduced.
　多階調マスクとは、３レベル（最小値、最大値およびこれらの間の中間値）以上の異なる透過率を有する領域を含むフォトマスクである。なお、典型的には、透過率の最小値はゼロである。多階調マスクは、ハーフトーンマスクまたはグレートーンマスクと呼ばれることもある。 A multi-tone mask is a photomask including regions having different transmittances of three levels (minimum value, maximum value, and intermediate value therebetween) or more. Typically, the minimum value of transmittance is zero. A multi-tone mask is sometimes called a halftone mask or a graytone mask.
特開２０１０－１２３９３２号公報JP 2010-123932 A
　特許文献１に記載されている製造方法では、ソース電極およびドレイン電極を形成するための導電膜と酸化物半導体膜とが同じレジストマスク（多階調マスクを用いて形成された）を用いてパターニングされるので、上述の酸化物半導体膜に凹部を形成する領域を除き、導電膜の下には酸化物半導体膜が存在する。例えば、特許文献１の図５および図６の左端に図示されているソース端子部は、導電膜の下に酸化物半導体層が存在している。従って、ソースメタル層とゲートメタル層とが電気的に接続される箇所（以下、「ソース・ゲートコンタクト部」あるいは「Ｓ／Ｇコンタクト部」という。）において、ソースメタル層とゲートメタル層との間に酸化物半導体層が存在することになる。 In the manufacturing method described in Patent Document 1, the conductive film for forming the source electrode and the drain electrode and the oxide semiconductor film are patterned using the same resist mask (formed using a multi-tone mask). Therefore, an oxide semiconductor film exists under the conductive film except for a region where a depression is formed in the oxide semiconductor film. For example, in the source terminal portion illustrated at the left end of FIGS. 5 and 6 of Patent Document 1, an oxide semiconductor layer exists under the conductive film. Accordingly, at the place where the source metal layer and the gate metal layer are electrically connected (hereinafter referred to as “source / gate contact portion” or “S / G contact portion”), the source metal layer and the gate metal layer are An oxide semiconductor layer is present between them.
　本発明者の検討によると、Ｓ／Ｇコンタクト部において、ソースメタル層とゲートメタル層との間に酸化物半導体層が存在すると、コンタクト抵抗が増大するという問題が生じることがあることが分かった。 According to the study of the present inventor, it has been found that when the oxide semiconductor layer exists between the source metal layer and the gate metal layer in the S / G contact portion, there is a problem that the contact resistance increases. .
　本発明の主な目的は、ソースメタル層とゲートメタル層とを接続する箇所において、ソースメタル層とゲートメタル層との間に酸化物半導体層が存在しない構成を有する半導体装置を、フォトマスクの数を増やすことなく製造する方法を提供することにある。 A main object of the present invention is to provide a semiconductor device having a structure in which an oxide semiconductor layer does not exist between a source metal layer and a gate metal layer at a place where the source metal layer and the gate metal layer are connected. It is to provide a method of manufacturing without increasing the number.
　本発明の実施形態の半導体装置の製造方法は、基板上に第１導電膜を堆積し、前記第１導電膜をパターニングすることによってゲートメタル層を形成する工程（ａ）と、前記ゲートメタル層の上に第１絶縁膜を堆積する工程（ｂ）と、前記第１絶縁膜の上に酸化物半導体膜を堆積する工程（ｃ）と、前記酸化物半導体膜と前記第１絶縁膜とを貫通し、前記ゲートメタル層の一部の表面を露出させる第１コンタクトホールを形成する工程（ｄ）と、前記酸化物半導体膜および前記ゲートメタル層の前記一部の上に第２導電膜を堆積し、前記酸化物半導体膜および前記第２導電膜を、多階調マスクを用いたフォトリソグラフィプロセスでパターニングすることによって、所定のパターンを有する酸化物半導体層および、前記第１コンタクトホール内で前記ゲートメタル層と接触したコンタクト部を有するソースメタル層を形成する工程（ｅ）とを包含する。 A method of manufacturing a semiconductor device according to an embodiment of the present invention includes a step (a) of forming a gate metal layer by depositing a first conductive film on a substrate and patterning the first conductive film, and the gate metal layer A step (b) of depositing a first insulating film on the substrate, a step (c) of depositing an oxide semiconductor film on the first insulating film, and the oxide semiconductor film and the first insulating film. Forming a first contact hole penetrating through and exposing a part of the surface of the gate metal layer; and forming a second conductive film on the oxide semiconductor film and the part of the gate metal layer. By depositing and patterning the oxide semiconductor film and the second conductive film by a photolithography process using a multi-tone mask, the oxide semiconductor layer having a predetermined pattern, and the first contact hole Comprising the step (e) forming a source metal layer having a contact portion in contact with said gate metal layer within.
　ある実施形態において、前記酸化物半導体層および前記ソースメタル層の上に第２絶縁膜を形成する工程（ｆ）と、前記第２絶縁膜を貫通し、前記ゲートメタル層の前記一部上に形成された前記ソースメタル層の一部の表面を露出させる第２コンタクトホールを形成する工程（ｇ）とをさらに包含する。 In one embodiment, a step (f) of forming a second insulating film on the oxide semiconductor layer and the source metal layer, and penetrating the second insulating film and on the part of the gate metal layer A step (g) of forming a second contact hole exposing a part of the surface of the formed source metal layer.
　ある実施形態において、前記工程（ｄ）は、前記酸化物半導体膜をウェットエッチングする工程と、前記第１絶縁膜をドライエッチングする工程とを包含する。 In one embodiment, the step (d) includes a step of wet etching the oxide semiconductor film and a step of dry etching the first insulating film.
　ある実施形態において、前記酸化物半導体膜は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系酸化物を含む。 In one embodiment, the oxide semiconductor film includes an In—Ga—Zn—O-based oxide.
　本発明の実施形態による表示装置は、上記のいずれかに記載の半導体装置の製造方法によって製造された半導体装置と、表示媒体層とを備える。 A display device according to an embodiment of the present invention includes a semiconductor device manufactured by any one of the semiconductor device manufacturing methods described above and a display medium layer.
　ソースメタル層とゲートメタル層とを接続する箇所において、ソースメタル層とゲートメタル層との間に酸化物半導体層が存在しない構成を有する半導体装置を、フォトマスク数を増やすことなく製造する方法を提供することができる。 A method for manufacturing a semiconductor device having a structure in which an oxide semiconductor layer does not exist between a source metal layer and a gate metal layer at a location where the source metal layer and the gate metal layer are connected without increasing the number of photomasks. Can be provided.
（ａ）～（ｅ）は、それぞれ、本発明の実施形態による半導体装置１００Ａの製造方法の一例を説明するための断面図である。(A) to (e) are cross-sectional views for explaining an example of a method for manufacturing the semiconductor device 100A according to the embodiment of the present invention. （ａ）～（ｃ）は、それぞれ、本発明の実施形態による半導体装置１００Ａの製造方法の一例を説明するための断面図である。FIGS. 7A to 7C are cross-sectional views for explaining an example of a manufacturing method of the semiconductor device 100A according to the embodiment of the present invention. 本発明の実施形態による半導体装置１００Ｂを備える液晶表示装置１００の模式的な断面図である。It is typical sectional drawing of the liquid crystal display device 100 provided with the semiconductor device 100B by embodiment of this invention. （ａ）～（ｄ）は、それぞれ、比較例による半導体装置２００Ａの製造方法の一例を説明するための断面図である。(A)-(d) is sectional drawing for demonstrating an example of the manufacturing method of 200 A of semiconductor devices by a comparative example, respectively. （ａ）～（ｄ）は、それぞれ、比較例による半導体装置２００Ａの製造方法の一例を説明するための断面図である。(A)-(d) is sectional drawing for demonstrating an example of the manufacturing method of 200 A of semiconductor devices by a comparative example, respectively.
　図１および図２を参照して、本発明の実施形態による半導体装置１００Ａ（図２（ｃ）参照）の製造方法を説明する。ここで例示する半導体装置１００Ａは、基板上に複数のＴＦＴを有するＴＦＴ基板１００Ａである。ＴＦＴ基板は、例えば、液晶表示装置または有機ＥＬ表示装置などの表示装置に用いられ得る。本発明による実施形態の表示装置の例は、図３を参照して後述する。 A method for manufacturing a semiconductor device 100A (see FIG. 2C) according to an embodiment of the present invention will be described with reference to FIGS. The semiconductor device 100A exemplified here is a TFT substrate 100A having a plurality of TFTs on the substrate. The TFT substrate can be used in a display device such as a liquid crystal display device or an organic EL display device. An example of a display device according to an embodiment of the present invention will be described later with reference to FIG.
　また、図１および図２には、ＴＦＴ基板１００ＡにおけるＴＦＴ部、ソースメタル層とゲートメタル層とが電気的に接続される箇所（「Ｓ／Ｇコンタクト部」）および端子部とを併せて示している。 FIG. 1 and FIG. 2 also show a TFT portion, a location where the source metal layer and the gate metal layer are electrically connected (“S / G contact portion”), and a terminal portion in the TFT substrate 100A. ing.
　なお、本明細書において、ゲートメタル層とは、ゲート電極およびゲートバスラインを形成する導電膜をパターニングすることによって形成された電極、配線および端子等を包含する層を指し、ゲート電極、ゲートバスラインの他、例えばＣＳバスライン、ＣＳ電極などを含むことがある。また、ソースメタル層とは、ソース電極、ドレイン電極およびソースバスラインを形成する導電膜をパターニングすることによって形成された電極、配線および端子等を包含する層であって、ソース電極、ドレイン電極およびソースバスラインの他、例えば、ドレイン引出配線・電極（ＣＳバスラインまたはＣＳ電極に対向し、ＣＳ容量を形成する配線・電極）等を含む。Ｓ／Ｇコンタクト部は、ジャンパー配線（他の配線を跨ぐ配線）を接続するために形成される。例えば、ソースメタル層内の２つの配線が交差する場合に、交差部の前後の２箇所において、一方の配線をゲートメタル層の配線（ジャンパー配線）に接続することによって、２つの配線を短絡させることなく交差させることができる。ここで、ゲートメタル層およびソースメタル層を形成する導電膜は、金属膜に限られず、例えば金属窒化物膜であってもよく、また、単層膜であっても、積層膜であってもよい。 Note that in this specification, the gate metal layer refers to a layer including electrodes, wirings, terminals, and the like formed by patterning a conductive film that forms a gate electrode and a gate bus line. In addition to lines, for example, CS bus lines, CS electrodes, and the like may be included. The source metal layer is a layer including electrodes, wirings, terminals, and the like formed by patterning a conductive film that forms a source electrode, a drain electrode, and a source bus line. In addition to the source bus line, for example, a drain lead-out wiring / electrode (a wiring / electrode facing the CS bus line or the CS electrode and forming a CS capacitor) is included. The S / G contact portion is formed to connect jumper wiring (wiring straddling other wiring). For example, when two wirings in the source metal layer intersect, the two wirings are short-circuited by connecting one wiring to the wiring (jumper wiring) of the gate metal layer at two places before and after the intersection. Can be crossed without Here, the conductive film forming the gate metal layer and the source metal layer is not limited to a metal film, and may be, for example, a metal nitride film, a single layer film, or a laminated film. Good.
　ソースメタル層とゲートメタル層とが互いに接続される構造は、ゲート端子部および／またはソース端子部においても形成され得る。以下の図に示す端子は、例えば、ゲート端子またはソース端子である。ゲート端子およびソース端子の積層構造は、互いに同じである必要はなく、または、それらの積層構造は、それぞれ独立に、Ｓ／Ｇコンタクト部の積層構造と同じであってもよいし、違ってもよい。 The structure in which the source metal layer and the gate metal layer are connected to each other can also be formed in the gate terminal portion and / or the source terminal portion. The terminals shown in the following figures are, for example, gate terminals or source terminals. The laminated structure of the gate terminal and the source terminal need not be the same as each other, or the laminated structures may be the same as or different from the laminated structure of the S / G contact portion. Good.
　まず、図１（ａ）に示すように、基板１１上に第１導電膜（ゲートメタル膜ともいう。）１２を堆積し、第１導電膜１２をパターニングすることによってゲートメタル層１２を形成する。簡単のために、第１導電膜１２と第１導電膜１２をパターニングすることによって形成されるゲートメタル層１２とを同じ参照符号で示す。典型的には、第１導電膜１２は、基板１１のほぼ全面に堆積される。第１導電膜の厚さは、例えば、５０ｎｍ以上３００ｎｍ以下である。ゲートメタル層１２は、ゲート電極１２ｇ、ゲートコンタクト層１２ｃおよびゲート端子層１２ｔを含む。ゲートメタル層１２は、この他、ゲート電極１２ｇと一体に形成されるゲートバスラインや、ＣＳ電極およびＣＳ電極と一体に形成されるＣＳバスラインを含み得る（いずれも不図示）。 First, as shown in FIG. 1A, a first conductive film (also referred to as a gate metal film) 12 is deposited on a substrate 11, and the first conductive film 12 is patterned to form a gate metal layer 12. . For simplicity, the first conductive film 12 and the gate metal layer 12 formed by patterning the first conductive film 12 are denoted by the same reference numerals. Typically, the first conductive film 12 is deposited on almost the entire surface of the substrate 11. The thickness of the first conductive film is, for example, not less than 50 nm and not more than 300 nm. The gate metal layer 12 includes a gate electrode 12g, a gate contact layer 12c, and a gate terminal layer 12t. In addition, the gate metal layer 12 may include a gate bus line formed integrally with the gate electrode 12g and a CS bus line formed integrally with the CS electrode and the CS electrode (all not shown).
　基板１１としては、例えば、ガラス基板、シリコン基板の他、耐熱性を有するプラスチック基板（樹脂基板ともいう。）を用いることができる。特に、プラスチック基板の材料としては、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート基板、ポリエーテルサルフォン、アクリル、ポリイミド等を用いることができる。さらに、これらのプラスチック材料に充填剤（ファイバーや不織布など）を混合したプラスチック複合材料を用いてもよい。ここでは、例えば、ガラス基板を用いる。 As the substrate 11, for example, a glass substrate, a silicon substrate, or a heat-resistant plastic substrate (also referred to as a resin substrate) can be used. In particular, as a material for the plastic substrate, polyethylene terephthalate (PET), polyethylene naphthalate substrate, polyethersulfone, acrylic, polyimide, or the like can be used. Furthermore, you may use the plastic composite material which mixed filler (fiber, the nonwoven fabric, etc.) with these plastic materials. Here, for example, a glass substrate is used.
　第１導電膜１２の材料としては、アルミニウム（Ａｌ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）、クロム（Ｃｒ）、チタン（Ｔｉ）、銅（Ｃｕ）等の金属またはこれらの少なくとも１つを含む合金、もしくは、これらの金属窒化物を用いることができる。さらに、第１導電膜１２は、上記の材料から形成された単層膜だけでなく、上記の材料から形成された積層膜であってもよい。ここでは、例えば、スパッタリング法で、アルミニウム（Ａｌ）膜とチタン（Ｔｉ）膜との積層構造の第１導電膜１２（膜厚：３００ｎｍ）を形成した後、フォトリソグラフィプロセスを用いて第１導電膜１２をパターニングすることによって、ゲート電極等を含むゲートメタル層１２を形成する。 Examples of the material of the first conductive film 12 include metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu), or these metals. An alloy containing at least one or a metal nitride thereof can be used. Furthermore, the first conductive film 12 may be not only a single layer film formed from the above material but also a laminated film formed from the above material. Here, for example, after the first conductive film 12 (film thickness: 300 nm) having a stacked structure of an aluminum (Al) film and a titanium (Ti) film is formed by a sputtering method, the first conductive is performed using a photolithography process. By patterning the film 12, a gate metal layer 12 including a gate electrode and the like is formed.
　次に、図１（ｂ）に示すように、ゲートメタル層１２上に第１絶縁膜（ゲート絶縁膜ともいう。）１４を堆積する。典型的には、第１絶縁膜１４も基板１１のほぼ全面に堆積される。 Next, as shown in FIG. 1B, a first insulating film (also referred to as a gate insulating film) 14 is deposited on the gate metal layer 12. Typically, the first insulating film 14 is also deposited on almost the entire surface of the substrate 11.
　第１絶縁膜１４の材料は、例えば、酸化珪素（ＳｉＯx）、窒化珪素（ＳｉＮx）、酸化窒化珪素（ＳｉＯxＮy、ｘ＞ｙ）、窒化酸化珪素（ＳｉＮxＯy、ｘ＞ｙ）を用いることができる。第１絶縁膜１４も単層膜であってもよいし、積層膜であってもよい。第１絶縁膜１４を２層膜とするときは、例えば、基板１１からの不純物等の拡散を防止するために、下層絶縁膜を、例えば、窒化珪素（ＳｉＮx）または窒化酸化珪素（ＳｉＮxＯy、ｘ＞ｙ）を用いて形成し、上層絶縁膜を、例えば、酸化珪素（ＳｉＯx）、酸化窒化珪素（ＳｉＯxＮy、ｘ＞ｙ）を用いて形成することが好ましい。また、反応ガスにアルゴンなどの希ガスを混合することによって、比較的低い温度で、緻密な絶縁膜を堆積することができる。緻密な絶縁膜は、ゲートリーク電流を低減させる効果を有し得る。ここでは、例えば、ＳｉＨ4およびＮＨ3を反応ガスとして用いるスパッタリング法で、下層絶縁膜として、厚さが１００ｎｍ以上４００ｎｍ以下の窒化珪素膜を形成し、その上に上層絶縁膜として、厚さが５０ｎｍ以上１００ｎｍ以下の酸化珪素膜を形成した積層膜を第１絶縁膜１４とする。 The material of the first insulating film 14 is, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y , x> y), silicon nitride oxide (SiN x O y , x>) y) can be used. The first insulating film 14 may also be a single layer film or a laminated film. When the first insulating film 14 has a two-layer film, for example, in order to prevent diffusion of impurities or the like from the substrate 11, the lower insulating film, for example, silicon nitride (SiN x) or silicon nitride oxide (SiN x O y, formed using x> y), the upper insulating film, for example, silicon oxide (SiO x), is preferably formed using a silicon oxynitride (SiO x N y, x> y). In addition, by mixing a rare gas such as argon with the reaction gas, a dense insulating film can be deposited at a relatively low temperature. A dense insulating film can have an effect of reducing gate leakage current. Here, for example, a silicon nitride film having a thickness of 100 nm to 400 nm is formed as a lower insulating film by a sputtering method using SiH 4 and NH 3 as a reaction gas, and a thickness of the upper insulating film is formed thereon. A laminated film in which a silicon oxide film having a thickness of 50 nm to 100 nm is formed as the first insulating film 14.
　続いて、図１（ｃ）に示すように、第１絶縁膜１４の上に酸化物半導体膜１６を堆積する。典型的には、酸化物半導体膜１６も基板１１のほぼ全面に堆積される。酸化物半導体膜１６の厚さは、例えば、３０ｎｍ以上１００ｎｍ以下である。 Subsequently, as shown in FIG. 1C, an oxide semiconductor film 16 is deposited on the first insulating film 14. Typically, the oxide semiconductor film 16 is also deposited on almost the entire surface of the substrate 11. The thickness of the oxide semiconductor film 16 is, for example, not less than 30 nm and not more than 100 nm.
　酸化物半導体膜１６の材料は、例えば、ＩｎＧａＯ3（ＺｎＯ）5、酸化マグネシウム亜鉛（ＭｇxＺｎ1-xＯ）、酸化カドミウム亜鉛（ＣｄxＺｎ1-xＯ）、酸化カドミウム（ＣｄＯ）、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の酸化物半導体を用いることができる。ここで、Ｉｎ－Ｇａ－Ｚｎ－Ｏは、Ｉｎ（インジウム）、Ｇａ（ガリウム）、Ｚｎ（亜鉛）の酸化物であり、アモルファスでもよいし、結晶質でもよい。結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ膜としては、ｃ軸が膜面に概ね垂直に配向した結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ膜が好ましい。このようなＩｎ－Ｇａ－Ｚｎ－Ｏ膜の結晶構造は、例えば、特開２０１２－１３４４７５号公報に開示されている。参考のために、特開２０１２－１３４４７５号公報の開示内容の全てを本明細書に援用する。また、１族元素、１３族元素、１４族元素、１５族元素または１７族元素等のうち一種、又は複数種の不純物元素が添加されたＺｎＯの非晶質（アモルファス）状態、多結晶状態又は非晶質状態と多結晶状態が混在する微結晶状態のもの、又は何も不純物元素が添加されていないものを用いることもできる。 Examples of the material of the oxide semiconductor film 16 include InGaO 3 (ZnO) 5 , magnesium zinc oxide (Mg x Zn 1-x O), cadmium zinc oxide (Cd x Zn 1-x O), cadmium oxide (CdO), An In—Ga—Zn—O-based oxide semiconductor can be used. Here, In—Ga—Zn—O is an oxide of In (indium), Ga (gallium), or Zn (zinc), and may be either amorphous or crystalline. As the crystalline In—Ga—Zn—O film, a crystalline In—Ga—Zn—O film in which the c-axis is oriented substantially perpendicular to the film surface is preferable. Such a crystal structure of the In—Ga—Zn—O film is disclosed in, for example, Japanese Patent Laid-Open No. 2012-134475. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference. Further, ZnO to which one or more impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element or Group 17 element are added, or an amorphous state, a polycrystalline state, or A microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can also be used.
　その後、図１（ｄ）に示すように、酸化物半導体膜１６の一部の表面を露出させる第１開口部４２ａおよび４２ｂを有する第１レジストマスク４２を形成する。ここで、第１レジストマスク４２が有する２つの第１開口部４２ａおよび４２ｂは、それぞれ、Ｓ／Ｇコンタクト部を形成するための第１コンタクトホール１４ａおよび端子部を形成するための第１コンタクトホール１４ｂを形成するための開口部である。もちろん、第１コンタクトホール１４ａだけを形成する場合には、第１開口部４２ａだけを有する第１レジストマスク４２を形成すればよい。第１レジストマスク４２は、公知のフォトレジストを用いて、所定のパターンを有するフォトマスクを用いて公知の方法で形成される。フォトレジストはネガ型でもポジ型でもよい。 Thereafter, as shown in FIG. 1D, a first resist mask 42 having first openings 42a and 42b exposing a part of the surface of the oxide semiconductor film 16 is formed. Here, the two first openings 42a and 42b of the first resist mask 42 are respectively a first contact hole 14a for forming an S / G contact portion and a first contact hole for forming a terminal portion. 14b is an opening for forming 14b. Of course, when only the first contact hole 14a is formed, the first resist mask 42 having only the first opening 42a may be formed. The first resist mask 42 is formed by a known method using a known photoresist and a photomask having a predetermined pattern. The photoresist may be negative or positive.
　第１コンタクトホール１４ａ、１４ｂの形成は、例えば、図１（ｅ）に示すように、第１開口部４２ａ、４２ｂを有する第１レジストマスク４２を用いて、酸化物半導体膜１６および第１絶縁膜１４をエッチングすることによって形成される。酸化物半導体膜１６のエッチングは、例えば、ウェットエッチングで行われ、第１絶縁膜１４のエッチングは例えばドライエッチングで行われる。フォトレジストを用いた第１レジストマスク４２の形成および第１レジストマスク４２を用いたエッチングによる第１コンタクトホール１４ａ、１４ｂの形成をフォトリソグラフィプロセスと呼ぶ。 For example, the first contact holes 14a and 14b are formed by using the first resist mask 42 having the first openings 42a and 42b as shown in FIG. It is formed by etching the film 14. Etching of the oxide semiconductor film 16 is performed by, for example, wet etching, and etching of the first insulating film 14 is performed by, for example, dry etching. The formation of the first resist mask 42 using a photoresist and the formation of the first contact holes 14a and 14b by etching using the first resist mask 42 are called a photolithography process.
　次に、図２（ａ）に示すように、酸化物半導体膜１６およびゲートメタル層１２の上記一部の上に第２導電膜（ソースメタル膜ともいう。）１８を堆積する。典型的には、第２導電膜１８も基板１１のほぼ全面に堆積される。このとき、第１コンタクトホール１４ａ、１４ｂ内で、第２導電膜１８がゲートメタル層１２と接触する。第２導電膜１８が第１コンタクトホール１４ａ内でゲートコンタクト層１２ｃと接触した部分からＳ／Ｇコンタクト部が形成され、第２導電膜１８が第１コンタクトホール１４ｂ内でゲート端子層１２ｔと接触した部分から端子部が形成される。 Next, as shown in FIG. 2A, a second conductive film (also referred to as a source metal film) 18 is deposited on the oxide semiconductor film 16 and the part of the gate metal layer 12. Typically, the second conductive film 18 is also deposited on almost the entire surface of the substrate 11. At this time, the second conductive film 18 contacts the gate metal layer 12 in the first contact holes 14a and 14b. The S / G contact portion is formed from the portion where the second conductive film 18 is in contact with the gate contact layer 12c in the first contact hole 14a, and the second conductive film 18 is in contact with the gate terminal layer 12t in the first contact hole 14b. A terminal portion is formed from the formed portion.
　第２導電膜１８の材料としては、アルミニウム（Ａｌ）、モリブデン（Ｍｏ）、銅（Ｃｕ）、チタン（Ｔｉ）等の金属またはこれらの少なくとも１つを含む合金、もしくは、これらの金属窒化物を用いることができる。さらに、第２導電膜１８は、上記の材料から形成された単層膜だけでなく、上記の材料から形成された積層膜であってもよい。ここでは、例えば、スパッタリング法で、アルミニウム（Ａｌ）膜とチタン（Ｔｉ）膜との積層構造の第２導電膜１８（膜厚：４００ｎｍ）を形成する。 As a material of the second conductive film 18, a metal such as aluminum (Al), molybdenum (Mo), copper (Cu), titanium (Ti), an alloy including at least one of these, or a metal nitride thereof is used. Can be used. Further, the second conductive film 18 may be not only a single layer film formed from the above material but also a laminated film formed from the above material. Here, for example, the second conductive film 18 (film thickness: 400 nm) having a stacked structure of an aluminum (Al) film and a titanium (Ti) film is formed by a sputtering method.
　続いて、図２（ｂ）に示すように、酸化物半導体膜１６および第２導電膜１８を、多階調マスクを用いたフォトリソグラフィプロセスでパターニングすることによって、所定のパターンを有する酸化物半導体層１６および、第１コンタクトホール１４ａ内でゲートメタル層１２と接触したコンタクト部を有するソースメタル層１８を形成する。 Subsequently, as shown in FIG. 2B, the oxide semiconductor film 16 and the second conductive film 18 are patterned by a photolithography process using a multi-tone mask to thereby form an oxide semiconductor having a predetermined pattern. A source metal layer 18 having a contact portion in contact with the gate metal layer 12 in the layer 16 and the first contact hole 14a is formed.
　図２（ｂ）に示す第２レジストマスク４４は、第２開口部４４ａ、４４ｂと、凹部４４ｃとを有している。多階調マスクを用いて、フォトレジスト膜を露光することによって、１回の露光工程で、３つの互いに異なる露光量（最小値、最大値およびこれらの間の中間値）で露光された領域が形成され、これを現像することによって、第２レジストマスク４４を形成することができる。フォトレジスト膜をネガ型のフォトレジストを用いて形成すると、露光量が最大の領域の膜厚が最も大きく、露光量が最小の領域に開口部４４ａ、４４ｂが形成され、露光量が中間の領域に凹部４４ｃが形成される。ポジ型のフォトレジストを用いると、露光量が最小の領域の膜厚が最も大きく、露光量が最大の領域に開口部４４ａ、４４ｂが形成され、露光量が中間の領域に凹部４４ｃが形成される。 The second resist mask 44 shown in FIG. 2B has second openings 44a and 44b and a recess 44c. By exposing the photoresist film using a multi-tone mask, a region exposed at three different exposure amounts (minimum value, maximum value, and intermediate value therebetween) can be obtained in one exposure step. The second resist mask 44 can be formed by forming and developing this. When the photoresist film is formed using a negative type photoresist, the film thickness of the region with the largest exposure amount is the largest, and the openings 44a and 44b are formed in the region with the smallest exposure amount. A recess 44c is formed on the surface. When a positive photoresist is used, the film thickness of the region with the smallest exposure amount is the largest, the openings 44a and 44b are formed in the region with the maximum exposure amount, and the recess 44c is formed in the region with the intermediate exposure amount. The
　第２レジストマスク４４を用いて、エッチングを行うことによって、図２（ｃ）に示すように、所定のパターンを有する酸化物半導体層１６ａおよび、第１コンタクトホール１４ａ内でゲートメタル層１２（１２ｃ）と接触したコンタクト部（Ｓ／Ｇコンタクト部を構成する）と、第１コンタクトホール１４ｂ内でゲートメタル層（１２ｔ）と接触したコンタクト部（端子部を構成する）とを有するソースメタル層１８を形成する。 By performing etching using the second resist mask 44, as shown in FIG. 2C, the oxide semiconductor layer 16a having a predetermined pattern and the gate metal layer 12 (12c) in the first contact hole 14a. The source metal layer 18 having a contact portion (which constitutes an S / G contact portion) in contact with the first contact hole 14b and a contact portion (which constitutes a terminal portion) which is in contact with the gate metal layer (12t) in the first contact hole 14b. Form.
　すなわち、第２レジストマスク４４の凹部４４ｃの下部では、ソースメタル膜１８だけがエッチングによって除去され、ソースメタル膜１８から、ソース電極１８ｓおよびドレイン電極１８ｄが形成される。酸化物半導体層１６ａの内で、酸化物半導体層１６ａ上のソースメタル膜１８が除去された領域がチャネル領域となり、ＴＦＴ１０Ａが得られる。 That is, only the source metal film 18 is removed by etching below the recess 44 c of the second resist mask 44, and the source electrode 18 s and the drain electrode 18 d are formed from the source metal film 18. In the oxide semiconductor layer 16a, a region where the source metal film 18 on the oxide semiconductor layer 16a is removed becomes a channel region, and the TFT 10A is obtained.
　また、第２レジストマスク４４の第２開口部４４ａおよび４４ｂの下部では、ソースメタル膜１８および酸化物半導体膜１６がともに除去され、第１絶縁膜１４の表面が露出させられる。その結果、Ｓ／Ｇコンタクト部のソースメタル部１８ｃおよび端子部のソースメタル部１８ｔはそれぞれ所定のパターンを有することになる。ここでは、積層構造に注目して断面構造を図示したが、例えば、Ｓ／Ｇコンタクト部のソースメタル部１８ｃは、ソース電極１８ｓおよびソースバスライン（不図示）と一体に形成され得る。また、端子部のソースメタル部１８ｔも、ソース電極１８ｓおよびソースバスライン（不図示）と一体に形成されてもよい。このとき、端子部は、ソース端子部である。一方、端子部のゲート端子層１２ｃがゲート電極１２ｇおよびゲートバスライン（不図示）と一体に形成されているとき、ソースメタル部１８ｔは、島状に形成されてもよい。 Further, under the second openings 44a and 44b of the second resist mask 44, both the source metal film 18 and the oxide semiconductor film 16 are removed, and the surface of the first insulating film 14 is exposed. As a result, the source metal portion 18c of the S / G contact portion and the source metal portion 18t of the terminal portion each have a predetermined pattern. Here, the cross-sectional structure is illustrated focusing on the laminated structure, but for example, the source metal portion 18c of the S / G contact portion can be formed integrally with the source electrode 18s and the source bus line (not shown). Further, the source metal portion 18t of the terminal portion may be formed integrally with the source electrode 18s and the source bus line (not shown). At this time, the terminal portion is a source terminal portion. On the other hand, when the gate terminal layer 12c of the terminal portion is formed integrally with the gate electrode 12g and the gate bus line (not shown), the source metal portion 18t may be formed in an island shape.
　この後、必要に応じて、酸化物半導体層１６およびソースメタル層１８の上に第２絶縁膜２２を形成し、第２絶縁膜２２を貫通し、ゲートメタル層１２の一部（１２ｔ）上に形成されたソースメタル層１８の一部の表面を露出させる第２コンタクトホール２２ａを形成する。 Thereafter, if necessary, a second insulating film 22 is formed on the oxide semiconductor layer 16 and the source metal layer 18, penetrates through the second insulating film 22, and covers a part (12 t) of the gate metal layer 12. A second contact hole 22a that exposes a part of the surface of the source metal layer 18 is formed.
　第２絶縁膜２２の材料としては、酸化珪素（ＳｉＯx）、窒化珪素（ＳｉＮx）、酸化窒化珪素（ＳｉＯxＮy、ｘ＞ｙ）、窒化酸化珪素（ＳｉＮxＯy、ｘ＞ｙ）、ＴＥＯＳ(Tetraethyl orthosilicate）などの無機絶縁材料や有機絶縁材料を用いることができる。有機絶縁材料として感光性樹脂を用いると、フォトレジストを用いることなく、端子部のソースメタル部１８ｔを露出させるコンタクトホール２２ａを形成することができる。また、有機絶縁材料を用いると基板１１の表面を平坦化することができる。第２絶縁膜２２は、上記の材料から形成された単層膜だけでなく、上記の材料から形成された積層膜であってもよい。ここでは、下層絶縁膜として、厚さが５ｎｍ以上５００ｎｍ以下の酸化珪素（ＳｉＯx）膜を形成し、その上に上層絶縁膜として、厚さが５ｎｍ以上５００ｎｍ以下の窒化珪素（ＳｉＮx）膜を形成した積層膜を第２絶縁膜２２とする。また、必要に応じて、例えば、無機絶縁膜を形成した後、有機絶縁膜を形成する前に、基板１１の全面を加熱（例えば３５０℃）する工程をさらに行ってもよい。 As the material of the second insulating film 22, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y , x> y), silicon nitride oxide (SiN x O y , x> y) ), TEOS (Tetraethyl orthosilicate) and other inorganic insulating materials and organic insulating materials can be used. When a photosensitive resin is used as the organic insulating material, the contact hole 22a that exposes the source metal portion 18t of the terminal portion can be formed without using a photoresist. Further, when an organic insulating material is used, the surface of the substrate 11 can be planarized. The second insulating film 22 may be not only a single layer film formed from the above material but also a laminated film formed from the above material. Here, a silicon oxide (SiO x ) film having a thickness of 5 nm to 500 nm is formed as a lower insulating film, and a silicon nitride (SiN x ) film having a thickness of 5 nm to 500 nm is formed thereon as an upper insulating film. The laminated film on which the film is formed is used as the second insulating film 22. Further, if necessary, for example, after forming the inorganic insulating film and before forming the organic insulating film, a step of heating the entire surface of the substrate 11 (for example, 350 ° C.) may be further performed.
　このようにして、ＴＦＴ基板１００Ａが得られる。 In this way, the TFT substrate 100A is obtained.
　ＴＦＴ基板１００Ａには、さらに必要に応じて、画素電極などが形成され、例えば、液晶表示装置のＴＦＴ基板として用いられ得る。 A pixel electrode or the like is further formed on the TFT substrate 100A as necessary, and can be used, for example, as a TFT substrate of a liquid crystal display device.
　図３を参照して、本発明の実施形態の液晶表示装置１００の構造を説明する。液晶表示装置１００は、本発明の実施形態による半導体装置（ＴＦＴ基板）１００Ｂを備える。 The structure of the liquid crystal display device 100 according to the embodiment of the present invention will be described with reference to FIG. The liquid crystal display device 100 includes a semiconductor device (TFT substrate) 100B according to an embodiment of the present invention.
　ＴＦＴ基板１００Ｂは、図２（ｃ）に示したＴＦＴ基板１００Ａの第２絶縁膜２２の上に画素電極２４を形成することによって得られる。なお、画素電極２４をドレイン電極１８ｄと電気的に接続するためのコンタクトホール２２ｂは、図２（ｃ）に示したコンタクトホール２２ａと同じ工程で形成され得る。図３は、簡単のために、ＴＦＴ１０Ａとその近傍だけを模式的に示している。 The TFT substrate 100B is obtained by forming the pixel electrode 24 on the second insulating film 22 of the TFT substrate 100A shown in FIG. The contact hole 22b for electrically connecting the pixel electrode 24 to the drain electrode 18d can be formed in the same process as the contact hole 22a shown in FIG. FIG. 3 schematically shows only the TFT 10A and the vicinity thereof for the sake of simplicity.
　液晶表示装置１００は、ＴＦＴ基板１００Ｂと、基板（例えばガラス基板）６１と、液晶層８２とを有している。基板６１の液晶層８２側には、対向電極７４が形成されている。画素電極２４と対向電極７４との間に存在する液晶層８２に電圧が印加される。画素電極２４および対向電極７４のそれぞれの液晶層８２側には必要に応じて配向膜（例えば垂直配向膜）が形成される。液晶表示装置１００は、例えば垂直配向モード（ＶＡモード）液晶表示装置である。もちろん、本発明の実施形態による液晶表示装置はこれに限られず、例えば、ＴＦＴ基板上に、画素電極と対向電極とを有する、例えば、Ｉｎ－Ｐｌａｎｅ　Ｓｗｉｔｃｈｉｎｇ（ＩＰＳ）モードやＦｒｉｎｇｅ　Ｆｉｅｌｄ　Ｓｗｉｔｃｈｉｎｇ（ＦＦＳ）モードのような横電界モードの液晶表示装置にも適用できる。ＩＰＳモードやＦＦＳモードの液晶表示装置のＴＦＴの構造は良く知られているので、説明を省略する。 The liquid crystal display device 100 includes a TFT substrate 100B, a substrate (for example, a glass substrate) 61, and a liquid crystal layer 82. A counter electrode 74 is formed on the liquid crystal layer 82 side of the substrate 61. A voltage is applied to the liquid crystal layer 82 existing between the pixel electrode 24 and the counter electrode 74. An alignment film (for example, a vertical alignment film) is formed on the pixel electrode 24 and the counter electrode 74 on the liquid crystal layer 82 side as necessary. The liquid crystal display device 100 is, for example, a vertical alignment mode (VA mode) liquid crystal display device. Of course, the liquid crystal display device according to the embodiment of the present invention is not limited thereto, and has, for example, a pixel electrode and a counter electrode on a TFT substrate, for example, an In-Plane Switching (IPS) mode or a Ringe Field Switching (FFS). The present invention can also be applied to a liquid crystal display device in a horizontal electric field mode such as a mode. Since the structure of the TFT of the IPS mode or FFS mode liquid crystal display device is well known, description thereof is omitted.
　また、本発明による実施形態の表示装置は、液晶表示装置に限らず、有機エレクトロルミネセンス（ＥＬ）表示装置および無機エレクトロルミネセンス表示装置等、ＴＦＴ基板を有する表示装置に広く適用される。 Further, the display device according to the embodiment of the present invention is not limited to the liquid crystal display device, and is widely applied to display devices having a TFT substrate such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device.
　次に、図４および図５を参照して、比較例による半導体装置２００Ａの製造方法を説明する。以下の説明において、上述したＴＦＴ基板１００Ａの構成要素と実質的に同じ機能を有する構成要素は共通の参照符号で示し、その説明を省略する。比較例のＴＦＴ基板２００Ａは、図５（ｄ）に示すように、Ｓ／Ｇコンタクト部および端子部において、ソースメタル層１８とゲートメタル層１２との間に酸化物半導体層１６が存在する点において、ＴＦＴ基板１００Ａと異なる。 Next, a method for manufacturing the semiconductor device 200A according to the comparative example will be described with reference to FIGS. In the following description, components having substantially the same functions as those of the above-described TFT substrate 100A are denoted by common reference numerals, and description thereof is omitted. As shown in FIG. 5D, the TFT substrate 200A of the comparative example has an oxide semiconductor layer 16 between the source metal layer 18 and the gate metal layer 12 in the S / G contact portion and the terminal portion. However, it is different from the TFT substrate 100A.
　まず、図４（ａ）に示すように、基板１１上に第１導電膜（ゲートメタル膜）１２を堆積し、第１導電膜１２をパターニングすることによってゲートメタル層１２を形成する。 First, as shown in FIG. 4A, a first conductive film (gate metal film) 12 is deposited on a substrate 11 and the first conductive film 12 is patterned to form a gate metal layer 12.
　次に、図４（ｂ）に示すように、ゲートメタル層１２上に第１絶縁膜（ゲート絶縁膜）１４を堆積する。 Next, as shown in FIG. 4B, a first insulating film (gate insulating film) 14 is deposited on the gate metal layer 12.
　その後、図４（ｃ）に示すように、第１絶縁膜１４の一部の表面を露出させる第１開口部５２ａおよび５２ｂを有する第１レジストマスク５２を形成する。ここで、第１レジストマスク５２が有する２つの第１開口部５２ａおよび５２ｂは、それぞれ、Ｓ／Ｇコンタクト部を形成するために第１コンタクトホール１４ａおよび端子部を形成するための第１コンタクトホール１４ｂを形成するための開口部である。 Thereafter, as shown in FIG. 4C, a first resist mask 52 having first openings 52a and 52b exposing a part of the surface of the first insulating film 14 is formed. Here, the two first openings 52a and 52b of the first resist mask 52 are respectively formed in the first contact hole 14a and the first contact hole for forming the terminal portion in order to form the S / G contact portion. 14b is an opening for forming 14b.
　次に、図４（ｄ）に示すように、第１レジストマスク５２を用いて、第１絶縁膜１４をエッチングすることによって、第１コンタクトホール１４ａおよび１４ｂを形成する。 Next, as shown in FIG. 4D, the first contact holes 14a and 14b are formed by etching the first insulating film 14 using the first resist mask 52. Next, as shown in FIG.
　次に、図５（ａ）に示すように、第１絶縁膜１４上に、酸化物半導体膜１６および第２導電膜１８を堆積する。このとき、第１コンタクトホール１４ａ、１４ｂ内で、酸化物半導体膜１６がゲートメタル層１２と接触する。酸化物半導体膜１６が第１コンタクトホール１４ａ内でゲートコンタクト層１２ｃと接触した部分からＳ／Ｇコンタクト部が形成され、酸化物半導体膜１６が第１コンタクトホール１４ｂ内でゲート端子層１２ｔと接触した部分から端子部が形成される。酸化物半導体膜１６上には第２導電膜１８が必ず存在している。 Next, as shown in FIG. 5A, an oxide semiconductor film 16 and a second conductive film 18 are deposited on the first insulating film 14. At this time, the oxide semiconductor film 16 contacts the gate metal layer 12 in the first contact holes 14a and 14b. An S / G contact portion is formed from a portion where the oxide semiconductor film 16 is in contact with the gate contact layer 12c in the first contact hole 14a, and the oxide semiconductor film 16 is in contact with the gate terminal layer 12t in the first contact hole 14b. A terminal portion is formed from the formed portion. The second conductive film 18 necessarily exists on the oxide semiconductor film 16.
　続いて、図５（ｂ）に示すように、酸化物半導体膜１６および第２導電膜１８を、多階調マスクを用いたフォトリソグラフィプロセスでパターニングすることによって、所定のパターンを有する酸化物半導体層１６およびソースメタル層１８を形成する。 Subsequently, as illustrated in FIG. 5B, the oxide semiconductor film 16 and the second conductive film 18 are patterned by a photolithography process using a multi-tone mask, thereby having an oxide semiconductor having a predetermined pattern. Layer 16 and source metal layer 18 are formed.
　図５（ｂ）に示す第２レジストマスク５４を用いて、エッチングを行うことによって、図５（ｃ）に示すように、所定のパターンを有する酸化物半導体層１６ａおよびソースメタル層１８を形成する。ソースメタル層１８は、酸化物半導体層１６を介して、第１コンタクトホール１４ａ内でゲートメタル層１２（１２ｃ）と接触したコンタクト部（Ｓ／Ｇコンタクト部を構成する）と、第１コンタクトホール１４ｂ内でゲートメタル層（１２ｔ）と接触したコンタクト部（端子部を構成する）とを有する。 By performing etching using the second resist mask 54 shown in FIG. 5B, the oxide semiconductor layer 16a and the source metal layer 18 having a predetermined pattern are formed as shown in FIG. 5C. . The source metal layer 18 includes a contact portion (which constitutes an S / G contact portion) in contact with the gate metal layer 12 (12c) in the first contact hole 14a via the oxide semiconductor layer 16, and a first contact hole. 14b has a contact portion (constituting a terminal portion) in contact with the gate metal layer (12t).
　すなわち、第２レジストマスク５４の凹部５４ｃの下部では、ソースメタル膜１８だけがエッチングによって除去され、ソースメタル膜１８から、ソース電極１８ｓおよびドレイン電極１８ｄが形成される。酸化物半導体層１６ａの内で、酸化物半導体層１６ａ上のソースメタル膜１８が除去された領域がチャネル領域となり、ＴＦＴが得られる。 That is, only the source metal film 18 is removed by etching under the recess 54 c of the second resist mask 54, and the source electrode 18 s and the drain electrode 18 d are formed from the source metal film 18. In the oxide semiconductor layer 16a, a region where the source metal film 18 on the oxide semiconductor layer 16a is removed becomes a channel region, and a TFT is obtained.
　また、第２レジストマスク５４の第２開口部５４ａおよび５４ｂの下部では、ソースメタル膜１８および酸化物半導体膜１６がともに除去され、第１絶縁膜１４の表面が露出させられる。その結果、Ｓ／Ｇコンタクト部のソースメタル部１８ｃおよび端子部のソースメタル部１８ｔはそれぞれ所定のパターンを有することになる。 Further, under the second openings 54a and 54b of the second resist mask 54, both the source metal film 18 and the oxide semiconductor film 16 are removed, and the surface of the first insulating film 14 is exposed. As a result, the source metal portion 18c of the S / G contact portion and the source metal portion 18t of the terminal portion each have a predetermined pattern.
　この後、必要に応じて、酸化物半導体層１６およびソースメタル層１８の上に第２絶縁膜２２を形成し、第２絶縁膜２２を貫通し、ゲートメタル層１２の一部（１２ｔ）上に形成されたソースメタル層１８の一部の表面を露出させる第２コンタクトホール２２ａを形成する。 Thereafter, if necessary, a second insulating film 22 is formed on the oxide semiconductor layer 16 and the source metal layer 18, penetrates through the second insulating film 22, and covers a part (12 t) of the gate metal layer 12. A second contact hole 22a that exposes a part of the surface of the source metal layer 18 is formed.
　このようにして、ＴＦＴ基板２００Ａが得られる。 In this way, the TFT substrate 200A is obtained.
　ＴＦＴ２００Ａは、Ｓ／Ｇコンタクト部および端子部において、ソースメタル層１８とゲートメタル層１２との間に酸化物半導体層１６が存在するので、コンタクト抵抗が増大するという問題が生じることがある。上述した本発明による実施形態のＴＦＴ基板１００Ａは、ソースメタル層１８とゲートメタル層１２との間に酸化物半導体層１６が存在しないので、このような問題は発生しない。また、上述した実施形態のＴＦＴ基板１００Ａの製造方法は、多階調マスクを用いたフォトリソグラフィプロセスで、酸化物半導体層とソースメタル層とをパターニングする工程を含んでおり、比較例のＴＦＴ基板２００Ａの製造方法と比較しても、フォトマスク数は増加していない。 In the TFT 200A, since the oxide semiconductor layer 16 exists between the source metal layer 18 and the gate metal layer 12 in the S / G contact portion and the terminal portion, there is a problem that the contact resistance increases. In the above-described TFT substrate 100A according to the embodiment of the present invention, since the oxide semiconductor layer 16 does not exist between the source metal layer 18 and the gate metal layer 12, such a problem does not occur. Moreover, the manufacturing method of the TFT substrate 100A of the above-described embodiment includes a step of patterning the oxide semiconductor layer and the source metal layer by a photolithography process using a multi-tone mask, and the TFT substrate of the comparative example Compared with the manufacturing method of 200A, the number of photomasks has not increased.
　本発明の実施形態は、酸化物半導体ＴＦＴおよび酸化物半導体ＴＦＴを有する種々の半導体装置に広く適用され得る。例えばアクティブマトリクス基板等の回路基板、液晶表示装置、有機エレクトロルミネセンス（ＥＬ）表示装置および無機エレクトロルミネセンス表示装置等の表示装置、イメージセンサー装置等の撮像装置、画像入力装置や指紋読み取り装置等の電子装置などにも適用できる。 Embodiments of the present invention can be widely applied to various semiconductor devices having an oxide semiconductor TFT and an oxide semiconductor TFT. For example, circuit boards such as active matrix substrates, liquid crystal display devices, display devices such as organic electroluminescence (EL) display devices and inorganic electroluminescence display devices, imaging devices such as image sensor devices, image input devices, fingerprint readers, etc. It can also be applied to other electronic devices.
　１０Ａ　ＴＦＴ
　１１　基板
　１２　第１導電膜（ゲートメタル膜、ゲートメタル層）
　１４　第１絶縁膜（ゲート絶縁膜）
　１４ａ、１４ｂ　第１コンタクトホール
　１６　酸化物半導体膜
　１８　第２導電膜（ソースメタル膜、ソースメタル層）
　２２　第２絶縁膜
　２２ａ、２２ｂ　第２コンタクトホール
　４２、４４、５２、５４　レジストマスク
　１００Ａ、２００Ａ　ＴＦＴ基板（半導体装置）
　１００　液晶表示装置 10A TFT
11 Substrate 12 First conductive film (gate metal film, gate metal layer)
14 First insulating film (gate insulating film)
14a, 14b First contact hole 16 Oxide semiconductor film 18 Second conductive film (source metal film, source metal layer)
22 Second insulating film 22a, 22b Second contact hole 42, 44, 52, 54 Resist mask 100A, 200A TFT substrate (semiconductor device)
100 Liquid crystal display device

Claims (5)

  1. 　基板上に第１導電膜を堆積し、前記第１導電膜をパターニングすることによってゲートメタル層を形成する工程（ａ）と、
    　前記ゲートメタル層の上に第１絶縁膜を堆積する工程（ｂ）と、
    　前記第１絶縁膜の上に酸化物半導体膜を堆積する工程（ｃ）と、
    　前記酸化物半導体膜と前記第１絶縁膜とを貫通し、前記ゲートメタル層の一部の表面を露出させる第１コンタクトホールを形成する工程（ｄ）と、
    　前記酸化物半導体膜および前記ゲートメタル層の前記一部の上に第２導電膜を堆積し、前記酸化物半導体膜および前記第２導電膜を、多階調マスクを用いたフォトリソグラフィプロセスでパターニングすることによって、所定のパターンを有する酸化物半導体層および、前記第１コンタクトホール内で前記ゲートメタル層と接触したコンタクト部を有するソースメタル層を形成する工程（ｅ）と
    を包含する、半導体装置の製造方法。     Depositing a first conductive film on a substrate and patterning the first conductive film to form a gate metal layer (a);
    Depositing a first insulating film on the gate metal layer;
    Depositing an oxide semiconductor film on the first insulating film (c);
    Forming a first contact hole penetrating the oxide semiconductor film and the first insulating film and exposing a part of the surface of the gate metal layer;
    A second conductive film is deposited on the oxide semiconductor film and the part of the gate metal layer, and the oxide semiconductor film and the second conductive film are patterned by a photolithography process using a multi-tone mask. And a step (e) of forming an oxide semiconductor layer having a predetermined pattern and a source metal layer having a contact portion in contact with the gate metal layer in the first contact hole. Manufacturing method.
  2. 　前記酸化物半導体層および前記ソースメタル層の上に第２絶縁膜を形成する工程（ｆ）と、
    　前記第２絶縁膜を貫通し、前記ゲートメタル層の前記一部上に形成された前記ソースメタル層の一部の表面を露出させる第２コンタクトホールを形成する工程（ｇ）と
    をさらに包含する、請求項１に記載の半導体装置の製造方法。     A step (f) of forming a second insulating film on the oxide semiconductor layer and the source metal layer;
    Forming a second contact hole penetrating the second insulating film and exposing a part of the surface of the source metal layer formed on the part of the gate metal layer; A method for manufacturing a semiconductor device according to claim 1.
  3. 　前記工程（ｄ）は、前記酸化物半導体膜をウェットエッチングする工程と、前記第１絶縁膜をドライエッチングする工程とを包含する、請求項１または２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step (d) includes a step of wet etching the oxide semiconductor film and a step of dry etching the first insulating film.
  4. 　前記酸化物半導体膜は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系酸化物を含む、請求項１から３のいずれかに記載の半導体装置の製造方法。 4. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor film includes an In—Ga—Zn—O-based oxide.
  5. 　請求項１から４のいずれかに記載の半導体装置の製造方法によって製造された半導体装置と、表示媒体層とを備える表示装置。 A display device comprising: a semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1; and a display medium layer.
PCT/JP2013/080295 2012-11-15 2013-11-08 Method for manufacturing semiconductor device and display device WO2014077201A1 (en)

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