KR20070008923A - Wire structure, method for making the same, thin film transistor substrate comprising the wire and method for fabricating the same - Google Patents

Abstract

A wiring structure, a forming method thereof, a thin film transistor including the wiring, and a fabrication method thereof are provided to improve an adhesion with a semiconductor layer including silicon by forming a wiring including an alloy of Ag and a metal for silicide on the semiconductor layer. A semiconductor layer(1) includes silicon. A conductive layer(2) is formed on the semiconductor layer, and is formed of an alloy of Ag and a metal that generates a silicide reaction at an interface of the semiconductor layer. A silicide layer(3a) or an agglomerated silicide(3b) is formed on a surface of the semiconductor layer.

Description

Wiring structure, method for forming the same, thin film transistor substrate including the wiring and manufacturing method thereof {Wire structure, method for making the same, thin film transistor substrate comprising the wire and method for fabricating the same}

1A to 1C are cross-sectional views sequentially illustrating a method of forming a wiring structure according to an exemplary embodiment of the present invention.

2 is a cross-sectional view illustrating a method of forming a wiring structure according to another exemplary embodiment of the present invention.

3A is a layout view of a thin film transistor substrate to which a wiring structure according to an exemplary embodiment of the present invention is applied.

FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. 3A.

4 is a cross-sectional view illustrating a step of forming data wirings in a process of the method of manufacturing the thin film transistor substrate illustrated in FIGS. 3A and 3B.

5 is a cross-sectional view of a thin film transistor substrate to which a wiring structure according to another exemplary embodiment of the present invention is applied.

FIG. 6A is a layout view of a thin film transistor substrate including a semiconductor layer and data lines to which a wiring structure is applied and formed using one mask, according to an exemplary embodiment.

FIG. 6B is a cross-sectional view taken along the line BB ′ of FIG. 6A.

7 and 8 are cross-sectional views illustrating a step of forming data wirings in a process of manufacturing the thin film transistor substrate shown in FIGS. 6A and 6B.

FIG. 9 is a cross-sectional view illustrating a thin film transistor substrate including a semiconductor layer and data lines, to which a wiring structure is applied and formed using one mask, according to another exemplary embodiment.

<Explanation of symbols on main parts of the drawings>

8a: silicide layer 8b: aggregated silicide

10: insulating substrate 22: gate line

24: gate end 26: gate electrode

27: sustain electrode 28: sustain electrode line

30: gate insulating film 40: semiconductor layer

55, 56: ohmic contact layer 62: data line

65 source electrode 66 drain electrode

67: drain electrode extension 68: data end

70: protective film 82: pixel electrode

The present invention relates to a wiring structure, and more particularly, to a wiring structure having improved adhesion to a semiconductor layer including silicon, a method of forming the same, and a thin film transistor substrate including the wiring structure and a method of manufacturing the same.

Liquid crystal display is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed between them. The display device is applied to rearrange the liquid crystal molecules of the liquid crystal layer to control the amount of light transmitted.

The liquid crystal display has a thin film transistor substrate, a color filter substrate facing the thin film transistor substrate, and a liquid crystal interposed between both substrates to determine whether light is transmitted as an electrical signal is applied. Here, a plurality of data lines and gate lines cross each other on the thin film transistor substrate, and a thin film transistor and a pixel electrode, which are switching elements, are formed in each crossing area.

On the other hand, as the liquid crystal display device becomes larger in size, the data wiring connected to the thin film transistor also becomes longer, and thus the resistance of the wiring also increases. Therefore, in order to solve such a problem as signal delay caused by an increase in resistance, it is necessary to form the data line wiring with a material having the lowest specific resistance.

The lowest specific resistance among the wiring materials is silver (Ag). Silver (Ag) has a specific resistance of about 1.59 μΩcm. Therefore, by using the data wiring made of silver (Ag) in the actual process, problems such as signal delay can be solved.

However, silver (Ag) is generally extremely poor in adhesion to semiconductor substrates made of intrinsic amorphous silicon, doped amorphous silicon, and the like, and thus is not easily deposited. This poor adhesion of silver causes lifting or peeling of the wiring in subsequent processes such as etching.

An object of the present invention is to provide a wiring structure with improved adhesion to a semiconductor layer containing silicon.

Another object of the present invention is to provide a method of forming a wiring structure as described above.

Another object of the present invention is to provide a thin film transistor substrate including the wiring structure as described above.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate including the wiring structure as described above.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a wiring structure according to an embodiment of the present invention includes a semiconductor layer including silicon, and a silver alloy formed of metal on the semiconductor layer and causing a silicide reaction at an interface with silver and the semiconductor layer. The surface of the conductive layer and the semiconductor layer includes a silicide layer or aggregated silicide.

According to another aspect of the present invention, there is provided a method of forming a wiring structure, which includes a conductive layer made of silver on a semiconductor layer including silicon and a silver alloy of a metal causing a silicide reaction at an interface with the semiconductor layer. Stacking a layer, such that a silicide layer or aggregated silicide is formed on the surface of the semiconductor layer and patterning the conductive layer and the silicide layer or the conductive layer and the aggregated silicide.

According to another aspect of the present invention, a thin film transistor substrate is formed on a gate insulating film covering a gate wiring formed on a substrate, a semiconductor layer formed on the gate insulating film, and the semiconductor layer. A data line comprising a data line, a source electrode connected to the data line, and a drain electrode formed to be spaced apart from the source electrode by a predetermined distance, and a conductive layer made of silver and a silver alloy of a metal causing a silicide reaction at an interface with the semiconductor layer. And a data line including a silicide layer or aggregated silicide on the surface of the semiconductor layer.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, including sequentially forming a gate wiring, a gate insulating film, and a semiconductor layer on the substrate, and forming a data line, a source electrode, and a drain electrode. Forming a data line including a conductive line formed of silver and a silver alloy of a metal which causes a silicide reaction at an interface with the semiconductor layer to form a silicide layer or a cohesive silicide on the surface of the semiconductor layer; It includes a step.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a wiring structure, a method of forming the same, and a thin film transistor substrate including the wiring structure and a method of manufacturing the thin film transistor substrate will be described in detail with reference to the accompanying drawings.

First, a wiring structure and a method of forming the same will be described with reference to FIGS. 1A to 1C. 1A to 1C are cross-sectional views sequentially illustrating a method of forming a wiring structure according to an exemplary embodiment of the present invention.

As shown in FIG. 1A, an alloy of silver (Ag) and a metal causing a silicide reaction at an interface with the semiconductor layer 1 (hereinafter, 'silicide metal') is laminated on the semiconductor layer 1 to form a conductive layer ( 2) form. The semiconductor layer 1 is made of intrinsic amorphous silicon or amorphous silicon doped with impurities.

The silicide metal included in the conductive layer 2 is a metal that forms a silicide as a thin film silicon compound by interfacial reaction with silicon contained in the semiconductor layer 1, and its content is 0.5 based on silver (Ag). It may be about 15 atoms (hereinafter 'atomic')%. And the silicide metal, for example, Zr, Ti, Hf, V, Ta, Ir, Ni, Th, Cr, Re, Nb, Co, Mn, Mo, Fe, W, Rh, Os or these compounds; Can be used.

The silicide metal is melted and alloyed with silver (Ag) and then deposited on the semiconductor layer 1 at a low temperature of about 150 ° C., so that the silicon of the silicon layer of the semiconductor layer 1 and the silicide metal in the conductive layer 2 are deposited. The silicide reaction occurs at the interface. This silicide reaction is inserted into a portion of the upper portion of the semiconductor layer 1 and a portion of the lower portion of the conductive layer 2 as shown in the enlarged view to form a thin silicide layer 3a on the whole, or partially aggregated silicide 3b. To form. In this case, the thickness of the conductive layer 2 and the silicide layer 3a or the conductive layer 2 and the aggregated silicide 3b may be approximately 1000 to 5000 mm. The formed silicide layer 3a and the aggregated silicide 3b have a thickness of 50 kPa or less compared with the conductive layer 2.

Therefore, at the interface, the silicide layer 3a or the aggregated silicide 3b generated by the silicide reaction between the silicon in the semiconductor layer 1 and the silicide metal in the conductive layer 2 is formed of the semiconductor layer 1 and the conductive layer 2. The chemical bond is strengthened at the contact surface of the to improve the adhesion between the conductive layer 2 and the semiconductor layer (1). Therefore, the phenomenon that the conductive layer 2 is lifted or peeled off from the semiconductor layer 1 can be prevented.

Although the above-described metal has been described as an example of the silicide metal, the present invention is not limited thereto, and may be a metal capable of forming silicide.

In addition to the binary alloy of silver (Ag) and the silicide metal, the conductive layer 2 may be a ternary alloy that is an alloy of two metals and silver in the silicide metal.

For example, sputtering may be used as a method for forming the conductive layer 2 of the alloy of silver (Ag) and the silicide metal.

Although not shown in the drawings, a silver layer may be further formed on the conductive layer 2 in order to sufficiently reduce the wiring structure.

Subsequently, as illustrated in FIG. 1B, a photosensitive film is coated on the conductive layer 2, exposed and developed to form a photosensitive film pattern 4 defining a wiring pattern.

Subsequently, as illustrated in FIG. 1C, the photoresist pattern 4 is etched using the etching mask. At this time, the silicide layer or the aggregated silicide (see 3a and 3b of FIG. 1A) existing under the conductive layer 2 to be etched is also removed at the same time as the conductive layer 2 to expose the lower semiconductor layer 1. After the semiconductor layer 1 is exposed, the photosensitive film pattern 4 is removed to form the first wiring structure 5. At this time, the etching process is a wet etching, the etching liquid used, for example, a mixture of phosphoric acid, nitric acid, acetic acid can be used.

2 is a cross-sectional view illustrating a method of forming a wiring structure according to another exemplary embodiment of the present invention.

Referring to FIG. 2, first, an adhesion promoting layer 6 made of a silicide metal is formed on a semiconductor layer 1. The thickness of the adhesion promoting layer 6 can be, for example, 50 kPa or more to substantially perform the adhesion promoting function of the semiconductor layer 1 and the conductive layer 2 formed thereon. In addition, from the viewpoint of the etching rate and the specific resistance with the conductive layer 2 formed on the semiconductor layer 1, it may be preferably 1000 kPa or less.

Although not shown in the drawings, a silver layer may be further formed on the conductive layer 2 in order to sufficiently reduce the wiring structure.

As the silicide metal constituting the adhesion promotion layer 6, the silicide metal used in one embodiment of the present invention may be applied in the same manner. Therefore, the silicide metal constituting the adhesion promotion layer 6 is subjected to a silicide reaction at the interface with silicon of the semiconductor layer 1 by the same mechanism. Here, the formation of the silicide layer 3a or the aggregated silicide 3b at the interface between the semiconductor layer 1 and the adhesion promotion layer 6 is the same as in the embodiment of the present invention. The silicide thus formed increases the adhesion of the adhesion promotion layer 6 to the semiconductor layer 1.

Subsequently, on the adhesion promotion layer 6, a conductive layer 2 made of an alloy of silver (Ag) and a metal for silicide is formed. At this time, the conductive layer 2 consists of silver (Ag) or silver (Ag) and the above-mentioned silicide metal. Since the conductive layer 2 is formed on the adhesion promoting layer 6 having a relatively better adhesion than the semiconductor layer 1, the adhesion is improved as compared with the case where the conductive layer 2 is directly formed on the semiconductor layer 1. In addition, when using the same metal as the silicide metal which comprises the adhesion promotion layer 6 as the silicide metal contained in the conductive layer 2, the same metal which exists in the adhesion promotion layer 6 and the conductive layer 2 is used. Adhesion can be further enhanced by the combination of.

On the other hand, the adhesion promoting layer 6 and the conductive layer 2 are formed by laminating by, for example, a sputtering method. At this time, the thickness of laminating the conductive layer 2 may be 1000 to 5000 kPa. In addition, since the sputtering process is performed at, for example, about 150 ° C., the metal for silicide of the adhesion promoting layer 6 exposed to this temperature promotes the reaction with the conductive layer 2 to promote the adhesion promoting layer 6. ) And the conductive layer 2 may further increase. Therefore, the conductive layer 2 is strengthened with the adhesion of the semiconductor layer 1 via the adhesion promotion layer 6, it is possible to prevent the phenomenon of lifting or peeling off from the semiconductor layer (1).

Subsequently, forming the wiring structure through patterning may be performed in the same manner as in the exemplary embodiment of the present invention, and a description thereof will be omitted.

The wiring structure according to the embodiment of the present invention described above can be equally applied to a thin film transistor substrate and a method of manufacturing the same.

Hereinafter, a thin film transistor substrate and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, a structure of a thin film transistor substrate to which a wiring structure according to an exemplary embodiment of the present invention is applied will be described with reference to FIGS. 3A and 3B. 3A is a layout view of a thin film transistor substrate, and FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. 3A.

A plurality of gate wirings for transmitting a gate signal are formed on the insulating substrate 10. The gate wires 22, 24, 26, 27, and 28 are connected to the ends of the gate line 22 and the gate line 22 extending in the horizontal direction, and receive gate signals from the outside and transfer them to the gate line. (24), the gate electrode 26 of the thin film transistor which is connected to the gate line 22 in the form of a projection, and the sustain electrode 27 and the sustain electrode line 28 formed in parallel with the gate line 22. . The storage electrode line 28 extends in the horizontal direction across the pixel region and is connected to the storage electrode 27 having a width wider than that of the storage electrode line 28. The storage electrode 27 overlaps with the drain electrode extension 67 connected to the pixel electrode 82, which will be described later, to form a storage capacitor that improves the charge storage capability of the pixel. Such shapes and arrangements of the storage electrode 27 and the storage electrode line 28 may be modified in various forms, and may not be formed when the storage capacitance generated by the overlap between the pixel electrode 82 and the gate line 22 is sufficient. It may not.

The gate wirings 22, 24, 26, 27, and 28 are made of a single layer made of aluminum (Al), copper (Cu), silver (Ag), or a double layer in which metals and molybdenum (Mo) are stacked. Can be.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the substrate 10 and the gate wirings 22, 24, 26, 27, and 28.

A semiconductor layer 40 made of a semiconductor such as hydrogenated amorphous silicon or polycrystalline silicon is formed in an island shape on the gate insulating layer 30 of the gate electrode 26, and a silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as heavily doped n + hydrogenated amorphous silicon are formed, respectively.

Data lines 62, 65, 66, 67, and 68 are formed on the ohmic contacts 55 and 56 and the gate insulating layer 30. The data lines 62, 65, 66, 67, and 68 are formed in the vertical direction and cross the gate line 22 to define the pixel and the branch of the data line 62 and the data line 62 to define a pixel. Is connected to one end of the source electrode 65 and the data line 62 extending to an upper portion of the data source, separated from the data end 68 and the source electrode 65 to which an image signal from the outside is applied, and the gate electrode 26. Or a wide area extending from the drain electrode 66 and the drain electrode 66 formed on the ohmic contact layer 56 opposite to the source electrode 65 with respect to the channel portion of the thin film transistor and overlapping the storage electrode 27. A drain electrode extension 67 of the area.

The data lines 62, 65, 66, 67 and 68 are made of a conductive layer 7 made of silver (Ag) or an alloy of silver (Ag) and a silicide metal. The data wirings 65 and 66 in contact with the ohmic contact layers 55 and 56 have a silicide reaction at an interface between the ohmic contact layers 55 and 56 and the conductive layer 7 as described with reference to FIG. 1A. The resulting silicide layer 8a or aggregated silicide 8b is present. In the embodiment of the present invention, the metal for silicide is exemplified above, but is not limited thereto as long as the metal can form silicide.

Herein, the structure and function of the conductive layer and the silicide layer or the aggregated silicide are equally applicable to the structure and function mentioned in the wiring structure according to the embodiment of the present invention as described above.

The source electrode 65 overlaps at least a portion of the semiconductor layer 40, and the drain electrode 66 faces the source electrode 65 around the gate electrode 26 and at least a portion of the source electrode 65. Overlaps. Here, the ohmic contacts 55 and 56 exist between the lower semiconductor layer 40 and the source electrode 65 and the drain electrode 66 above and serve to lower the contact resistance.

The drain electrode extension 67 is formed to overlap the storage electrode 27, and a storage capacitor is formed with the storage electrode 27 and the gate insulating layer 30 interposed therebetween. When the sustain electrode 27 is not formed, the drain electrode extension 27 is also not formed.

The passivation layer 70 is formed on the data wires 62, 65, 66, 67, and 68 and the semiconductor layer 40 not covered by the data lines 62. The passivation layer 70 is formed of, for example, a-Si: C: O, a-Si: Low dielectric constant insulating materials such as O: F, or silicon nitride (SiNx), which is an inorganic material. In addition, when the protective film 70 is formed of an organic material, in order to prevent the organic material of the protective film 70 from contacting a portion where the semiconductor layer 40 between the source electrode 65 and the drain electrode 66 is exposed. An insulating film (not shown) made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) may be further formed below the organic film.

In the passivation layer 70, contact holes 77 and 78 exposing the drain electrode extension 67 and the data line end 68 are formed, respectively, and the passivation line 24 is formed in the passivation layer 70 and the gate insulating layer 30. The contact hole 74 exposing) is formed. The pixel electrode 82, which is electrically connected to the drain electrode 66 and positioned in the pixel, is formed on the passivation layer 70 through the contact hole 77. The pixel electrode 82 to which the data voltage is applied generates an electric field together with the common electrode of the upper panel to determine the arrangement of liquid crystal molecules of the liquid crystal layer between the pixel electrode 82 and the common electrode.

In addition, an auxiliary gate end 84 and an auxiliary data end 88 connected to the gate end 24 and the data end 68 are formed on the passivation layer 70 through the contact holes 74 and 78, respectively. The pixel electrode 82, the auxiliary gate, and the data ends 86 and 88 are made of ITO.

Hereinafter, a method of manufacturing the thin film transistor substrate illustrated in FIGS. 3A and 3B will be described in detail with reference to FIG. 4.

Hereinafter, the process that can be formed according to the process steps that are well known to those skilled in the art when describing the manufacturing method will be briefly described in order to avoid being ambiguous.

An insulating substrate 10 having an island-like semiconductor layer 40 and an ohmic contact layer 50 is formed on the gate insulating film 30 on the gate wirings 22, 24, 26, and 27.

Subsequently, a conductive layer 7 made of an alloy of silver (Ag) and a silicide metal is laminated on the gate insulating layer 30, the exposed semiconductor layer 40, and the ohmic contacts 55 and 56 by sputtering or the like. Thereafter, photo etching is performed to form the data lines 62, 65, 66, 67, and 68. At this time, the etching process is a wet etching using an etching solution.

Among the data wires 65 and 66 in contact with the ohmic contacts 55 and 56, as described with reference to FIG. 1A, the ohmic contact layers 55 and 56 and the conductive layers 7 are laminated while the conductive layers 7 are stacked. The silicide reaction is performed at the interface of 7) to form the silicide layer 8a or the aggregated silicide 8b.

The adhesion to the ohmic contacts 55 and 56 of the data wires 62, 65, 66, 67 and 68 is improved by the formation of the silicide layer 8a or the aggregated silicide 8b.

As a result, the data line 62 and the data line 62 intersecting the gate line 22 are connected to one end of the source electrode 65 and the data line 62 extending to the upper portion of the gate electrode 26. The data end 68, which is separated from the source electrode 65, extends from the drain electrode 66 and the drain electrode 66 facing the source electrode 65 with respect to the gate electrode 26. ), Data lines 62, 65, 66, 67, and 68 including a large area drain electrode extension 67 are formed.

Next, the doped amorphous silicon layer not covered by the data lines 62, 65, 66, 67, and 68 is etched to move the data lines 62, 65, 66, 67, and 68 to both sides of the gate electrode 26. While separating, the semiconductor layer 40 between the two ohmic contact layers 55 and 56 is exposed. At this time, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform an oxygen plasma.

Subsequent steps will be omitted here in order to avoid obscuring the present invention.

FIG. 5 is a cross-sectional view taken along the line BB ′ of FIG. 3A to a thin film transistor substrate to which a wiring structure is applied, according to another exemplary embodiment.

The data wires 62, 65, 66, 67, and 68 are made up of the data conductive layers 621, 651, 661, 671, and 681, and the data adhesion promoting layers 622, 652, 662, 672, and 682. The data lines 65 and 66 in contact with the ohmic contact layers 55 and 56 are interfaces between the ohmic contact layers 55 and 56 and the data adhesion promoting layers 652 and 662 as described with reference to FIG. 2. There is a silicide layer 8a or agglomerated silicide 8b produced by the silicide reaction at.

The structures and functions of the data conductive layers 621, 651, 661, 671, 681, the data adhesion promoting layers 622, 652, 662, 672, 682 and the silicide layer 8a or the cohesive silicide 8b are described above. The structures and functions mentioned in the wiring structure according to another embodiment of the invention apply equally.

On the other hand, the method of manufacturing the thin film transistor substrate shown in FIG. 5 is substantially the same as the data wiring forming method described with reference to FIG. 4.

As described above, the method of manufacturing the thin film transistor substrate for forming the semiconductor layer and the data wiring by the photolithography process using different masks has been described. The same applies to the same. This will be described in detail with reference to the drawings.

 6A and 6B are layout views and cross-sectional views of a thin film transistor substrate including a semiconductor layer and data lines to which a wiring structure is applied and formed using a mask according to an embodiment of the present invention.

6A and 6B, the semiconductor layer 44 is substantially formed below the data lines 65 and 66 of the thin film transistor channel portion, and is substantially the same as the thin film transistor substrate illustrated in FIG. 3A. Same as

Here, the data wirings 62, 65, 66, 67, and 68 are made of silver (Ag) or a conductive layer 7 of an alloy of silver (Ag) and a silicide metal. The data wires 62, 65, 66, 67, and 68 in contact with the ohmic contacts 52, 55, 56, and 58 are the ohmic contacts 52, 55, 56, and 58 as described with reference to FIG. 1A. At the interface between the conductive layer 7 and the silicide layer 8a or agglomerated silicide 8b produced by the silicide reaction is present. Herein, the structure and function of the conductive layer and the silicide layer or the aggregated silicide are equally applied to the structure and function mentioned in the wiring structure according to the embodiment of the present invention described above.

Hereinafter, a method of manufacturing the thin film transistor substrate illustrated in FIGS. 6A and 6B will be described with reference to FIGS. 7 and 8. As shown in FIG. 7, after the gate wirings 22, 24, 26, and 27 are formed on the insulating substrate 10, the gate insulating layer 30, the intrinsic amorphous silicon layer 40, and the doped amorphous layer are sequentially formed. The silicon layer 50 is continuously deposited.

Next, a conductive layer 7 made of an alloy of silver (Ag) and a metal for silicide is laminated on the doped amorphous silicon layer 50 by a sputtering method. Here, a silicide reaction is performed at the interface between the doped amorphous silicon layer 50 and the conductive layer 7 to form the silicide layer 8a or the aggregated silicide 8b.

The adhesion of the conductive layer 7 to the doped amorphous silicon layer 50 is improved by the formation of the silicide layer 8a or the aggregated silicide 8b.

Subsequently, photoresist patterns 112 and 114 are formed using a mask having a slit or a lattice pattern formed on the conductive layer 7. At this time, the first portion 114 between the photoresist patterns 112 and 114 between the source electrode 65 and the drain electrode 66 may have a smaller thickness than the second portion 112 positioned at the portion where the data line is to be formed.

Subsequently, as illustrated in FIG. 8, the data wirings 62, 65, 66, 67, and 68 may be formed by using a plurality of etching methods suitable for each material layer using the photoresist patterns 112 and 114 as an etching mask. The semiconductor patterns 42, 44, 48 and the ohmic contacts 52, 55, 56, and 58 are formed.

Here, the formed data wires 62, 65, 66, 67, and 68 may have the silicide layer 8a or the cohesive silicide 8b only between the conductive layer 7 and the doped amorphous silicon layers 52, 56, 57, and 58. ) Exists.

In this case, the adhesion between the conductive layer 7 of the data lines 62, 65, 66, 67, and 68 and the doped amorphous silicon layers 52, 56, 57, and 58 is determined by the silicide layer 8a or the aggregated silicide 8b. It is improved by formation.

Subsequent steps will be omitted here in order to avoid obscuring the present invention.

In another embodiment of the present invention, the data wirings 62, 65, 66, 67, and 68 and the ohmic contact layers 52, 55, 56, and 58 and the semiconductors as well as the effects according to the embodiment of the present invention may be used. The manufacturing process may be simplified by forming the patterns 42, 44, and 48 using one mask and separating the source electrode 65 and the drain electrode 66 in this process.

FIG. 9 is a cross-sectional view taken along the line BB ′ of FIG. 6A of a thin film transistor substrate having a semiconductor layer and data wiring formed by using a mask and having a wiring structure according to another embodiment of the present invention.

The data wires 62, 65, 66, 67, and 68 are made up of the data conductive layers 621, 651, 661, 671, and 681, and the data adhesion promoting layers 622, 652, 662, 672, and 682. The data wires 62, 65, 66, 67, and 68 in contact with the ohmic contacts 52, 55, 56, and 58 are the ohmic contacts 52, 55, 56, and 58 as described with reference to FIG. 2. At the interface between the data adhesion promotion layers 622, 652, 662, 672, and 682, there is a silicide layer 8a or agglomerated silicide 8b produced by the silicide reaction.

 The structures and functions of the data conductive layers 621, 651, 661, 671, 681, the data adhesion promoting layers 622, 652, 662, 672, 682 and the silicide layer 8a or the cohesive silicide 8b are described above. The structures and functions mentioned in the wiring structure according to another embodiment of the invention apply equally.

Meanwhile, the manufacturing method of the thin film transistor substrate to which the wiring structure is applied according to another embodiment of the present invention illustrated in FIG. 9 is substantially the same as the data wiring forming method described with reference to FIGS. 7 and 8, and thus description thereof is omitted. do.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the wiring of the present invention as described above, the method of forming the wiring and the thin film transistor substrate including the wiring and the manufacturing method of the thin film transistor substrate, the following effects are obtained.

First, a wiring made of an alloy of silver (Ag) and a silicide metal may be formed on a semiconductor layer containing silicon to improve adhesion.

Second, by using a thin film transistor substrate including a wiring made of an alloy of silver (Ag) and a silicide metal, the adhesive force may be improved to prevent lifting or peeling off of the substrate to improve signal characteristics.

Claims (28)

A semiconductor layer comprising silicon; A conductive layer formed on the semiconductor layer and made of silver and a silver alloy of a metal which causes a silicide reaction at an interface with the semiconductor layer; And A wiring structure including a silicide layer or aggregated silicide on the surface of the semiconductor layer. The method of claim 1. And a content of the metal causing the silicide reaction in the conductive layer is 0.5 to 15 atomic%. The method of claim 1, And a thickness of the sum of the conductive layer and the silicide layer or the conductive layer and the aggregated silicide is 1000 to 5000 kPa. The method of claim 1, A wiring structure further comprising an adhesion promoting layer made of a metal causing the silicide reaction under the conductive layer. The method of claim 4, wherein The thickness of the said adhesion promotion layer is a wiring structure of 50-1000 micrometers. The method of claim 1, And a silver layer on the conductive layer. The method according to any one of claims 1 to 6, The metal causing the silicide reaction includes a wire including Zr, Ti, Hf, V, Ta, Ir, Ni, Th, Cr, Re, Nb, Co, Mn, Mo, Fe, W, Rh, Os, or a compound thereof. rescue. Stacking a conductive layer made of silver and a silver alloy of a metal having a silicide reaction at an interface with the semiconductor layer on a semiconductor layer including silicon, wherein a silicide layer or aggregated silicide is formed on a surface of the semiconductor layer; And Patterning the conductive layer and the silicide layer or the conductive layer and the aggregated silicide. The method of claim 8. And a content of the metal causing the silicide reaction in the conductive layer is 0.5 to 15 atomic%. The method of claim 8, The thickness of the sum of the said conductive layer, the said silicide layer, or the said conductive layer, and the said cohesive silicide is 1000-5000 kPa, The formation method of the wiring structure. The method of claim 8, And forming an adhesion promoting layer made of a metal causing the silicide reaction under the conductive layer. The method of claim 11, The thickness of the said adhesion promotion layer is a formation method of the wiring structure of 50-1000 micrometers. The method of claim 8, And forming a silver layer on the conductive layer. The method according to any one of claims 8 to 13, The metal causing the silicide reaction includes a wire including Zr, Ti, Hf, V, Ta, Ir, Ni, Th, Cr, Re, Nb, Co, Mn, Mo, Fe, W, Rh, Os, or a compound thereof. Method of formation of the structure. A gate insulating film covering the gate wiring formed on the substrate; A semiconductor layer formed on the gate insulating layer; And A data line formed on the semiconductor layer, the data line including a data line, a source electrode connected to the data line, and a drain electrode formed to be spaced apart from the source electrode by a predetermined distance to cause a silicide reaction at an interface with silver and the semiconductor layer. A thin film transistor substrate comprising a conductive layer made of a silver alloy of a metal and a data line including a silicide layer or a cohesive silicide on a surface of the semiconductor layer. The method of claim 15. The thin film transistor substrate of claim 1, wherein the content of the metal causing the silicide reaction in the conductive layer is 0.5 to 15 atomic%. The method of claim 15, The thickness of the sum of the said conductive layer, the said silicide layer, or the said conductive layer, and the said cohesive silicide is 1000-5000 kPa. The method of claim 15, The thin film transistor substrate further comprising an adhesion promoter layer formed of a metal causing the silicide reaction under the conductive layer. The method of claim 18, The adhesion promoter layer has a thickness of 50 to 1000 kHz. The method of claim 15, The thin film transistor substrate further comprising a silver layer on the conductive layer. The method according to any one of claims 15 to 20, The metal causing the silicide reaction may be a thin film including Zr, Ti, Hf, V, Ta, Ir, Ni, Th, Cr, Re, Nb, Co, Mn, Mo, Fe, W, Rh, Os, or a compound thereof. Transistor substrate. Sequentially forming a gate wiring, a gate insulating film, and a semiconductor layer on the substrate; And A data line including a data line, a source electrode, and a drain electrode is formed. Forming a data line to form a silicide layer or a cohesive silicide on the surface of the semiconductor layer by stacking a conductive layer made of silver and a silver alloy of a metal which causes a silicide reaction at an interface with the semiconductor layer. Method of preparation. The method of claim 22. A method of manufacturing a thin film transistor substrate, which forms a conductive layer having a content of the metal causing the silicide reaction in the conductive layer is 0.5 to 15 atomic%. The method of claim 22, The thickness of the sum of the said conductive layer, the said silicide layer, or the said conductive layer, and the said cohesive silicide is 1000-5000 micrometers, The manufacturing method of the thin film transistor substrate. The method of claim 22, And forming an adhesion promoter layer formed of a metal causing the silicide reaction under the conductive layer. The method of claim 25, The adhesion promoter layer has a thickness of 50 to 1000 kW. The method of claim 22, The thin film transistor substrate manufacturing method further comprising a silver layer on the conductive layer. The method according to any one of claims 22 to 27, The metal causing the silicide reaction may be a thin film including Zr, Ti, Hf, V, Ta, Ir, Ni, Th, Cr, Re, Nb, Co, Mn, Mo, Fe, W, Rh, Os, or a compound thereof. Method for manufacturing a transistor substrate.

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