JP2004273614A - Semiconductor device and its fabricating process - Google Patents
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【0001】
【発明の属する技術分野】
本発明は、半導体装置およびその製造方法に関している。
【0002】
【従来の技術】
液晶表示装置の表示パネルに用いられる薄膜トランジスタの半導体部分は、通常、アモルファスシリコン(a−Si)や多結晶シリコン(poly−Si)から形成されている。
【0003】
これらの半導体材料は可視光を吸収するため、光の照射によって半導体中に電子・正孔対が形成され、トランジスタ特性が劣化する。具体的には、トランジスタがオフ状態にあるときでも、光の照射によって半導体層のチャネル領域にキャリアが生成され、ソース領域とドレイン領域との間に電流が流れる。オフ時のトランジスタを流れる電流は「オフリーク電流」と呼ばれ、この値が大きいと、表示バネルが正常に動作しないという問題がある。このため、光が半導体層を照射しないように遮光膜のパターンを形成することが行われている。しかし、遮光膜のパターンを形成するには、遮光膜の堆積工程やフォトリソグラフィ・エッチング工程が必要になるため、工程が煩雑になる。
【0004】
このような問題を解決するため、近年、禁制帯幅(バンドギャップ)が3.4eVと広い直接遷移型の半導体である酸化亜鉛(ZnO)やZnOを主成分とした化合物半導体から形成した透明トランジスタが注目されている。このような透明トランジスタでは、半導体のバンドギャップが可視光帯域の光エネルギよりも大きく、可視光を吸収しないため、光の照射を受けてもオフリーク電流は増大しないという利点を有し、注目されている。
【0005】
ZnOを半導体層に用いたスタガ型薄膜トランジスタは、例えば、特許文献1に開示されている。図1を参照しながら、ZnOを半導体層に用いたスタガ型薄膜トランジスタの構成を説明する。
【0006】
図1の薄膜トランジスタは、絶縁性基板1上に形成されたソース電極20aおよびドレイン電極20bと、ソース・ドレイン電極20a、20bに接触するように配置されたZnO層4と、ZnO層4上に積層されたゲート絶縁層5およびゲート電極6とを備えている。
【0007】
この薄膜トランジスタは、ZnO層4の下方にソース・ドレイン電極20a、20bを有し、かつ、ZnO層4の上方にゲート電極6を有するスタガ構成を備えている。このようなスタガ型薄膜トランジスタを形成するには、ソース・ドレイン電極材料膜をパターニングする工程と、ZnO膜、ゲート絶縁材料膜、およびゲート電極材料膜の積層体をパターニングする工程とが必要であるが、そのために必要なフォトリソグラフィ工程でのマスクアライメントは最低2回であり、製造コストの削減が期待できる。
【0008】
一方、近年の表示パネルの大型化および高精細化に伴って、ソース・ドレイン電極20a、20bやソース電極20aと一体的に形成されるソースバス配線の材料として、電気抵抗がより低い金属を用いることが求められている。このために、従来から広く用いられているTaなどの高融点金属よりも比抵抗が低いアルミニウム(Al)またはAlを主成分とするAl合金が注目されている。
【0009】
【特許文献1】
特開2000−150900号公報
【0010】
【発明が解決しようとする課題】
しかしながら、本発明者の検討によると、図1に示されるスタガ型薄膜トランジスタのソース・ドレイン電極20a、20bのための導電材料としてAlを用いた場合、ソース・ドレイン電極20a、20bとZnO層4との接触部において、ソース・ドレイン電極20a、20bに一部欠落などの欠陥・不良が生じることがわかった。
【0011】
このよう欠陥・不良は、現像液などの電解質を含んだ溶液や大気中に水分と薄膜トランジスタとが接触することにより発生した。このため、ソース・ドレイン電極20a、20bとZnO層4との接触部で局部電池反応が生じ、その結果、電蝕反応が進行して断線等の不良を引き起こしてしまうと考えられる。
【0012】
本発明は、上記事情に鑑みてなされたものであり、その目的とするところは、ZnOから半導体層を形成し、かつ、電極・配線材料としてアルミニウム用いた場合でも電蝕による欠陥・不良が生じない半導体装置を提供することにある。
【0013】
【課題を解決するための手段】
本発明による半導体装置は、基板と、前記基板に支持されている少なくとも1つの電極と、前記電極の上面の少なくとも一部に接触する半導体層とを備えた半導体装置であって、前記電極は、第1導電材料から形成された第1導電層と、前記第1導電層の上面と前記半導体層との間に配置され、前記第1導電材料とは異なる第2導電材料から形成された第2導電層と、前記半導体層の下面と前記第1導電層の側面との間に位置する絶縁性保護層とを有している。
【0014】
ある好ましい実施形態において、前記半導体層は、バンドギャップが3eV以上の半導体から形成されている。
【0015】
ある好ましい実施形態において、前記半導体層は、ZnOまたはZnOを主成分とした化合物半導体から形成されている。
【0016】
ある好ましい実施形態において、前記第1導電体材料は、主としてアルミニウムを含む。
【0017】
ある好ましい実施形態において、前記絶縁性保護層は、前記第1導電材料の酸化物および/または窒化物から形成されている。
【0018】
ある好ましい実施形態において、前記第1導電材料の比抵抗は、前記第2導電材料の比抵抗よりも低く、前記第2導電材料は前記第1導電材料に比べて局部電池反応による腐食が生じにくい。
【0019】
ある好ましい実施形態において、前記第2導電材料と前記半導体層との間でオーミック性を有する接触が生じている。
【0020】
ある好ましい実施形態において、前記第2導電材料は、第IV族、第V族、もしくは第VI族の金属またはこれらの金属の窒化物である。
【0021】
ある好ましい実施形態において、前記金属は、Ti、Ta、およびMoからなる群から選択された少なくとも1つの金属である。
【0022】
ある好ましい実施形態において、前記少なくとも1つの電極は、前記基板上において離れた位置に形成された2つの電極を含んでいる。
【0023】
ある好ましい実施形態において、前記2つの電極の各々における前記絶縁性保護層は、前記基板上において連続している。
【0024】
ある好ましい実施形態において、前記絶縁性保護層は、可視光を透過する材料から形成されている。
【0025】
ある好ましい実施形態において、前記絶縁性保護層は、SiO2、Al2O3、Ta2O3、およびSiNx(0≦x<3)からなる群から選択された少なくとも1つの絶縁材料から形成されている。
【0026】
ある好ましい実施形態において、前記半導体層の上面側に配置され、前記半導体層と接触する第2の電極を更に有している。
【0027】
ある好ましい実施形態において、前記2つの電極は、それぞれ、ソース電極およびドレイン電極であり、前記第2の電極は、前記半導体層の上面に形成されたゲート絶縁膜を介して前記半導体層に対向するゲート電極である。
【0028】
本発明の表示装置は、上記のいずれかに記載の半導体装置を備えている。
【0029】
本発明による半導体装置の製造方法は、少なくとも1つの電極を基板上に形成する工程と、前記電極を覆うように半導体層を形成する工程とを含む半導体装置の製造方法であって、前記電極を形成する工程は、第1導電材料の膜を形成する工程と、前記第1導電材料以外の第2導電材料の膜を前記第1導電層材料の膜の上に堆積する工程と、前記2つの膜をパターニングすることにより、前記第1導電材料から形成された第1導電層と、前記第2導電材料から形成された第2導電層とを含む積層構造を形成する工程と、前記第1導電層の側面の少なくとも一部を覆う絶縁性保護層を形成する工程とを含む。
【0030】
ある好ましい実施形態において、前記2つの膜をパターニングする工程は、前記2つの膜の上にレジストマスクを堆積する工程と、前記2つの膜のうちレジストマスクで覆われてない部分をエッチングする工程とを含む。
【0031】
ある好ましい実施形態において、前記絶縁性保護層を形成する工程は、前記第1導電層の側面を酸化および/または窒素する工程を含む。
【0032】
ある好ましい実施形態において、前記絶縁性保護層を形成する工程は、前記レジストマスクを除去する前に、絶縁膜を基板上に堆積する工程と、前記レジストマスクを除去することにより、前記絶縁膜の不要部分のリフトオフを行い、前記絶縁膜の一部を前記第1導電層の側面に残置する工程とを含む。
【0033】
本発明による他の半導体装置は、基板と、前記基板に支持されている少なくとも1つの電極と、前記電極の上面の少なくとも一部に接触する半導体層とを備えた半導体装置であって、前記半導体層は、ZnOまたはZnOを主成分とした化合物半導体から形成されており、前記電極は、アルミニウムを主成分とする第1導電材料から形成された第1導電層と、前記第1導電層の上面と前記半導体層との間に配置され、前記第1導電材料とは異なる第2導電材料から形成された第2導電層とを有しており、前記第2導電材料は、前記第1導電材料に比べて局部電池反応による腐食が生じにくい。
【0034】
ある好ましい実施形態において、前記第2導電層は、前記第1導電層の上面および側面の両方を覆っている。
【0035】
ある好ましい実施形態において、前記少なくとも1つの電極は、前記基板上において離れた位置に形成された2つの電極を含んでおり、前記2つの電極の各々における前記第2導電層は、前記基板上において電気的に分離されている。
【0036】
ある好ましい実施形態において、前記第2導電材料と前記半導体層との間でオーミック性を有する接触が生じている。
【0037】
ある好ましい実施形態において、前記第2導電材料は、第IV族、第V族、もしくは第VI族の金属またはこれらの金属の窒化物である。
【0038】
ある好ましい実施形態において、前記金属は、Ti、Ta、およびMoからなる群から選択された少なくとも1つの金属である。
【0039】
【発明の実施の形態】
以下、図面を参照しながら、本発明の好ましい実施形態を説明する。
【0040】
(実施形態1)
まず、図2を参照しながら、本発明による半導体装置の第1の実施形態の構成を説明する。本実施形態の半導体装置は、液晶表示装置などの表示パネルに好適に用いられるアクティブマトリクス基板である。
【0041】
なお、本明細書における「半導体装置」の用語は、基板上に形成された薄膜トランジスタなどの半導体素子そのものを指し示すのではなく、薄膜トランジスタなどの半導体素子が形成された基板を備える構造物、または当該構造物を備えた装置を広く指し示すものとする。また、基板上に形成される半導体素子は、薄膜トランジスタなどの三端子素子に限定されず、発光素子やスイッチング素子として機能するダイオードをも含むものとする。
【0042】
以下、簡単のため、複数の薄膜トランジスタが行および列からなるマトリクス状に配列されたアクティブマトリクス基板上の単一の薄膜トランジスタに着目して本実施形態を詳述する。図面には、単一の薄膜トランジスタのみを記載しているが、実際の基板上には複数の薄膜トランジスタが形成されている。
【0043】
本実施形態の半導体装置は、図2に示すように、基板1と、基板1に支持されたソース電極20aおよびドレイン電極20bと、ソース・ドレイン電極20a、20bの各々の上面の少なくとも一部に接触する半導体層4とを備えている。半導体層4の上には、ゲート絶縁膜5およびゲート電極6がこの順序で積層されており、薄膜トランジスタか構成されている。なお、図示してはいないが、現実のアクティブマトリクス基板には、上記の薄膜トランジスタに接続されたソースバスライン、ゲートバスライン、および画素電極が形成されており、また、これらを覆う絶縁膜や配向膜が堆積されている。
【0044】
本実施形態における基板1は、液晶表示装置用の無アルカリガラス(コーニング社製1737ガラス)から形成されている。基板1は、ガラスやプラスチックなどの透明材料から形成することが好ましいが、用途によっては、必ずしも透明な絶縁性材料から形成される必要はない。
【0045】
半導体層4は、ZnOから形成されている。前述したように、ZnOは、バンドギャップが3eVを超える化合物半導体であり、可視光を透過する。透過型の液晶表示装置に用いるアクティブマトリクス基板は、背面側に可視光の光源(バックライト)を配置するため、図示されている薄膜トランジスタもバックライトからの光で照射されることになる。従来のようにシリコンを用いて形成した薄膜トランジスタの場合、バックライトからの光が薄膜トランジスタを照射しないように遮光膜を適切に配置する必要があるが、本実施形態では、そのような必要はない。
【0046】
ゲート絶縁層5は、SiO2から形成され、ゲート電極6は、Alから形成されている。これらゲート絶縁層5およびゲート電極6の材料は、ここに示したものに限定されず、適宜最適な材料を選択して、用いることができる。
【0047】
ソース・ドレイン電極20a、20bの各々は、アルミニウム(Al)から形成された第1導電層2と、チタニウム(Ti)から形成された第2導電層3と、第1導電層2および第2導電層3の側面を覆う絶縁性保護層7とを有している。言い換えると、第1導電層2の上面と半導体層4との間には第2導電層3が配置され、第1導電層2の側面と半導体層4の下面との間には絶縁性保護層7が配置されている。
【0048】
本実施形態では、このように第1導電層2と半導体層4との直接的な接触が避けられているため、第1導電層2にAlを用い、半導体層4にZnOを用いた場合でも、局部電池反応による電蝕が生じないため、ソース・ドレイン電極20a、20bの断線などの欠陥・不良の発生を防止することができる。
【0049】
第2導電層3の材料(第2導電材料)としては、第1導電層2の材料(第1導電材料)に比べて、半導体層4の間で局部電池反応による腐食が生じにくい材料を用いることが好ましく、また、半導体層4との間でオーミック性を有する接触が生じる材料を選択することが好ましい。半導体層4の材料としてZnOやZnOを主成分とする化合物半導体を用いる場合、第2導電材料としては、第IV族、第V族、もしくは第IV族の金属またはこれらの金属の窒化物を用いることが可能であり、これらの金属は、具体的にはTi、Ta、および/またはMoである。
【0050】
半導体層4の材料として、ZnOやZnOを主成分とする化合物半導体以外の半導体を用いる場合は、その半導体との間で電蝕が生じにくく、かつ、オーミック接触の可能な材料を適宜選択すればよい。
【0051】
第2導電層3の厚さは、第1導電層2と半導体層4との間にあって電蝕防止効果を発揮し得る大きさを有しておればよい。また、第2導電層3を厚く形成しすぎると、第2導電材料の堆積に要する工程時間が長くなるため、好ましくない。第2導電層3の厚さは、例えば30nm以上200nm以下の範囲に設定され得る。
【0052】
第1導電層2の材料(第1導電材料)は、比抵抗が低いという観点から純度の高いアルミニウムを使用しているが、この代わりに添加物が付与されたアルミニウム合金などを用いても良い。アルミニウムには、温度の高いプロセスを経ると、ヒロックが成長しやすいという問題があるが、本実施形態のように、上面を第2導電層3で覆い、かつ側面を絶縁性保護層7で覆うことにより、ヒロックの発生・成長を抑制する効果も得られる。配線抵抗をより低くするためには、第1導電層2を厚く形成することが好ましく、液晶表示装置が大画面化すると、今までよりも第1導電層2を厚く形成することが必要になる。第1導電層2が厚くなるほど、第2導電層2の側面から成長するヒロックによる短絡などが問題になり得るが、本実施形態のように側面が絶縁性保護層7で覆われていると、そのようなヒロックを効果的に抑制できるという利点が得られる。
【0053】
第1導電層2の好ましい厚さ範囲は、例えば50nm以上700nm以下である。第1導電層2が50nmよりも薄くなると、抵抗低減効果がほんど得られないから好ましくなく、また、第1導電層2が700nmを超えて厚くなると、表面段差が大きくなりすぎるため、好ましくない。
【0054】
絶縁性保護層7の厚さは、電蝕防止効果を示すに充分な絶縁性を示す大きさを持つことが好ましい。絶縁性保護層7を厚く形成しすぎると、そのために必要な工程時間が長くなるため、好ましくない。このため、絶縁性保護層7の厚さは、例えば5nm以上50nm以下の範囲に設定され得る。
【0055】
本実施形態では、絶縁性保護層7を第1導電層2の側面に選択的に形成した絶縁膜から形成している。このため、特別のパターニング工程が不要である。
【0056】
以下、図2の薄膜トランジスタの製造方法を説明する。
【0057】
ます、DCスパッタ成膜方法などの薄膜堆積技術を用いて、50〜700nmの範囲から選択された厚さ(例えば100nm)を有するAl膜を基板1上に堆積した後、Al膜上に30〜200nmの範囲から選択された厚さ(例えば50nm)を有するTi膜を堆積する。
【0058】
次に、図3(a)に示すように、上記積層金属膜(Al/Ti積層膜)上に、ソース・ドレイン電極およびソース・ドレイン電極20a、20bと一体的に形成される配線の形状を規定するレジストマスク8を形成する。レジストマスク8は、公知のフォトリソグラフィ技術によってフォトレジスト材料を露光・現像することによって作製される。
【0059】
次に、上記のAl/Ti積層膜のうちレジストマスク8に覆われていない部分をエッチングすることにより、図3(a)に示すような第1導電層2および第2導電層3のTi/Al積層体を作製する。このエッチングは、好ましくは、プラズマを用いた異方性の高いドライエッチング技術で行う。
【0060】
次に、Ti/Al積層体の側面に対して絶縁性保護層7を形成する。本実施形態では、酸素プラズマ処理により、絶縁性保護層7を形成する。具体的には、まず、基板1をプラズマ処理装置のチャンバー内に挿入し、チャンバー内の圧力が400〜1000mTorrになるよう酸素ガスを導入する。次に、基板1が置かれる下部電極と、それに対向して配置されてい上部電極との間に例えば13.6MHzの高周波電界を印加する。投入する電力は、例えば500〜1000Wの範囲に設定することができる。プラズマ処理装置における上下の電極間に発生した酸素プラズマにより、Ti/Al積層体のうちレジストマスク8で覆われていない領域(側面部)が酸化され、その部分に厚さ5〜50nm(好ましくは10〜30nm)の絶縁性酸化物が成長し、それによって絶縁性保護層7が形成される。本実施形態における絶縁性保護層7は、Al2O3部分およびTiOx部分から構成されている。より詳細には、絶縁性保護層7のうちのAl2O3部分は第1導電層2の側面を覆い、TiOx部分は第2導電層3の側面を覆っている。AlとTiとでは酸化レートが異なるため、絶縁性保護層7のうちのAl2O3部分とTiOx部分とでは厚さが異なり得る。
【0061】
絶縁性保護層7を窒化膜から形成することも可能である。プラズマ処理装置のチャンバー内に窒素を導入し、窒素プラズマでTi/Al積層体の露出した側面が窒化すればよい。Ti/Al積層体の側面を窒化する場合、絶縁性保護層7は、第1導電層2の側面に形成されるAlNから構成されることになる。第2導電層3の側面にはTiNが形成されるが、TiNは導電性を有するため、絶縁性保護層7としては機能しない。
【0062】
本実施形態では、プラズマを用いた酸化によって第1導電層2の側面に酸化物を形成したが、陽極酸化法によって、数十nm程度の酸化物を形成しても良い。陽極酸化は、化成液中に基板1を浸し、70〜100Vの化成電圧を印加することによって行うことができる。Alの陽極酸化を行う場合、化成液としては、エチレングリコールまたはプロピレングリコールで希釈した酒石酸(PH:7程度)を用いることが好ましい。このように、Alの陽極酸化にとって最適な条件を採用すると、Tiなどからなる第2導電層3の側面には陽極酸化膜が形成されにくくなる。化成電圧が高くなりにくいため、ソース・ドレイン電極20a、20bにおける第1導電層2の側面に形成されるAl2O3の成長レートも小さい。しかし、Al2O3の厚さは数十nm程度もあれば、電蝕反応を抑制する効果は充分に発揮される。また、第2導電層3の側面は酸化膜によって覆われている必要はないため、Tiの陽極酸化膜を形成できなくとも問題ない。
【0063】
次に、CVD法やスパッタ法などの薄膜堆積技術により、ZnO膜(厚さ:例えば100nm)およびSiO2膜(厚さ:例えば200nm)を基板1上に連続して堆積した後、スパッタ法により、Al膜(厚さ:例えば100nm)をSiO2膜上に堆積する。ZnO膜の堆積にスパッタ法を用いる場合、好ましくは、ZnOの焼結ターゲットを用い、基板温度を例えば250℃に保持しながら、ArおよびO2の混合ガス雰囲気中(ガス流量はAr:O2=2:1)でZnOを堆積することができる。この後、必要に応じて熱処理を行ってもよい。
【0064】
次に、フォトリソグラフィ技術により、ゲート電極・配線のパターンを規定するレジストマスクを形成し、Al/SiO2/ZnO積層膜のうちレジストマスクで覆われてない部分を連続的にエッチングする。このエッチングは、好ましくは、プラズマを用いた異方性の高いドライエッチング方法などを用いて実行する。この後、剥離洗浄工程を行い、レジストマスクを除去する。こうして、図2に示すように、半導体層4、ゲート絶縁膜5、およびゲート電極6を形成することができる。
【0065】
本実施形態の方法によれば、半導体層4、ゲート絶縁膜5、およびゲート電極6が同一の平面レイアウトを有しており、ゲート電極6の下方に半導体層4が存在している。なお、トランジスタ毎に半導体層4を孤立させる場合、ゲート絶縁膜5およびゲート電極6のため膜を堆積する前に、半導体膜をパターニングしてアイランド状の半導体4を得てもよい。
【0066】
このようにして作製されたスタガ型薄膜トランジスタでは、AlとZnOとの接触が完全に避けることができるため、AlとZnOと間で電蝕反応が生じず、配線不良の発生を防止することができる。
【0067】
(実施形態2)
以下、図4を参照しながら、本発明による半導体装置の第2の実施形態を説明する。
【0068】
本実施形態の半導体装置と、実施形態1における半導体装置との相違点は、ソース・ドレイン電極20a、20bの構成にあり、それ以外の点では同様であるため、以下、ソース・ドレイン電極20a、20bの構成およびその作製方法を詳しく説明する。
【0069】
本実施形態におけるソース・ドレイン電極20a、20bは、図4に示すように、それぞれ。Alから形成された第1導電層2と、Tiから形成された第2導電層3と、第1導電層2および第2導電層3の側面および基板表面を覆う絶縁性保護層7とを有している。実施形態1と同様に、第1導電層2の上面と半導体層4との間には第2導電層3が配置され、第1導電層2の側面と半導体層4の下面との間には絶縁性保護層7が配置されているため、アルミニウムから形成された第1導電層2と半導体層4との直接的な接触が避けられている。
【0070】
本実施形態で特徴的な点のひとつは、絶縁性保護層7がソース電極20aとドレイン電極20bとの間で連続していることにある。
【0071】
以下、図5(a)および(b)を参照しながら、本実施形態の半導体装置の製造方法を説明する。
【0072】
まず、絶縁性基板1として、無アルカリガラス基板(コーニング社製1737ガラス)1を用意し、DCスパッタ成膜方法により、基板1上にAl膜(厚さ:例えば100nm)およびTi膜(厚さ:例えば50nm)を連続的に堆積する。次に、フォトリソグラフィ工程により、ソース・ドレイン電極20a、20bおよびソース・ドレイン電極20a、20bと一体的に連結された配線の形状を規定するレジストマスク8をTi/Al積層膜上に作製する。
【0073】
次に、Ti/Al積層膜のうち、レジストマスク8によって覆われていない部分をエッチングし、ソース・ドレイン電極における第1導電層2および第2導電層3を形成する。このエッチングは、好ましくは、反応性イオンエッチング(RIE)方式によって行う。具体的には、Cl2ガス(圧力:例えば10mTorr)でエッチング装置のチャンバーを満たし、電極間に5kW程度のRFを印加することによって行うことができる。
【0074】
以上の工程により、図5(a)に示す構造を得る。次に、レジストマスク8を除去することなく、RFスパッタリング法またはCVD法により、本実施形態ではSiO2膜(厚さ:30nm程度)を基板1上に堆積する(図5(b))。レジストマスク8が基板1上に存在するため、SiO2膜の堆積温度は200℃以下に設定することが好ましい。
【0075】
この後、レジストマスク8を剥離する工程を行うことにより、レジストマスク8上のSiO2膜の一部をリフトオフで除去する。このリフトオフにより、SiO2膜のうち図5(b)の点線部よりも上に位置する部分がレジストマスク8とともに除去されるため、ソース・ドレイン電極20a、20bにおける第1および第2導電層2、3の側面および基板1の表面を覆うSiO2膜が残置されることになる。このようにして残ったSiO2が絶縁性保護7として機能する。このように本実施形態では、基板1の上面のうち、ソース・ドレイン電極20a、20bが形成されていない領域が絶縁性保護層7によって覆われている。
【0076】
次に、CVD法やスパッタ法などの薄膜堆積技術により、ZnO膜(厚さ:例えば100nm)およびSiO2膜(厚さ:例えば200nm)を基板1上に連続して堆積した後、スパッタ法により、Al膜(厚さ:例えば100nm)をSiO2膜上に堆積する。
【0077】
次に、フォトリソグラフィ技術により、ゲート電極・配線のパターンを規定するレジストマスク(不図示)を形成し、Al/SiO2/ZnO積層膜のうちレジストマスクで覆われてない部分を連続的にエッチングする。このエッチングは、好ましくは、プラズマを用いた異方性の高いドライエッチング方法により実行する。この後、剥離洗浄工程を行い、レジストマスクを除去する。こうして、図4に示す半導体層4、ゲート絶縁膜5、およびゲート電極6を形成することができる。
【0078】
以上の方法で作製されたスタガ型薄膜トランジスタでは、AlとZnOとが接触していないため、AlとZnOとの間に電蝕反応が抑制される。
【0079】
本実施形態では、絶縁性保護層7としてSiO2の膜を用いているが、絶縁性保護層7の材料はSiO2に限定されない。液晶表示装置の場合、絶縁性保護層7の上に画素電極が形成されるため、透過型の表示を行うには、絶縁性保護層7がバックライトからの光を高い効率で透過する性質を持つことが好ましい。
【0080】
また、本実施形態における絶縁性保護層7は、ソース電極とドレイン電極との間に連続して存在しているため、その絶縁性が充分に高いことが望まれる。絶縁性保護層7の材料としては、SiNx、Al2O3、Ta2O5などの材料が好適である。
【0081】
上記の実施形態1および2における薄膜トランジスタを液晶表示装置の画像表示領域におけるスイッチング素子として使用する場合、ソース電極20aはソースバスライン(信号線)と接続され、ドレイン電極20bは、対応する画素電極に接続される。好ましい態様では、ソースバスラインがソース電極20aと一体的に形成され、その場合には、ソースバスラインもソース・ドレイン電極20a、20bと同様の断面構成を有することになる。前述のように、アルミニウムはタンタルなどに比べて比抵抗が小さいため、タンタルからソースバスラインを形成した場合に比べてソースバスラインの配線抵抗を大きく低減することができる。
【0082】
なお、上記の各実施形態におけるアクティブマトリクス基板を用いて液晶表示装置を作製する場合、公知の製造方法により、対向基板とアクティブマトリクス基板との間に液晶を封止することによって液晶パネルを形成すればよい。
【0083】
(実施形態3)
次に、図6を参照しながら、本発明による半導体装置の第3の実施形態を説明する。
【0084】
本実施形態では、薄膜トランジスタではなく、薄膜ダイオードを基板上に形成している。図6に示すように、本実施形態の半導体装置は、基板1と、基板1に支持された第1電極30と、第1電極30の上面の少なくとも一部に接触する半導体層4とを備えている。半導体層4の上には、第2電極12が配置されている。第1電極30および第2電極12は、ダイオードのカソードまたはアノードとして機能する。
【0085】
本実施形態では、半導体層4がZnOから形成されており、半導体層4の下方に位置する第1電極30が第1導電層10および第2導電層11を有し、かつ、側面が絶縁性保護層7によって覆われた構造を有している。
【0086】
以下、図6の半導体装置の製造方法を説明する。
【0087】
まず、絶縁性基板1を用意し、その上に、DCスパッタ成膜方法によってAl膜(厚さ:例えば100nm)およびTi膜(厚さ:例えば50nm)を連続的に堆積する。次に、フォトリソグラフィ工程で、第1電極の形状を規定するレジストマスクをTi/Al積層膜上に作製する。Ti/Al積層膜のうち、レジストマスクで覆わていない部分をエッチングし、第1電極30の第1導電層10および第2導電層11を作製する。ドライエッチングは、反応性イオンエッチング(RIE)方式で行う。具体的には、Cl2ガス(圧力:10mTorr)でエッチング装置のチャンバーを満たし、電極間に5kW程度のRFを印加することによって行うことができる。
【0088】
次に、実施形態1と同様の方法で第1導電層10および第2導電像11の側面に絶縁性保護層7を形成する。その後、CVD又はスパッタ法でZnOからなる半導体層(厚さ:100nm)4を堆積し、所定の形状にパターニングする。その後、ZnOとの間でショットキー接合を形成し得る材料(金、白金、Niなど)からショットキー接合電極(第2電極)12を形成し、図6に示す薄膜ダイオードを得る。
【0089】
図6に示す薄膜ダイオードにおいても、AlとZnOとの接触が完全に避けられているため、AlとZnOとの間に電蝕反応が抑制されている。
【0090】
(実施形態4)
図7は、実施形態2で説明した方法で絶縁性保護層7を形成した点以外は、上記の実施形態3と同様の方法で作製した薄膜ダイオードの断面構成を示している。本実施形態における薄膜ダイオードにおいても、AlとZnOとの接触が完全に避けられているため、AlとZnOとの間に電蝕反応が抑制されている。
【0091】
以上説明してきた各実施形態では、いずれも、半導体層をZnOから形成しているが、本発明はこれに限定されない。ZnOを主成分とした化合物半導体から半導体層を形成する場合にも本発明の電蝕防止効果を発揮する。また、半導体層としてシリコン層を用いる場合であっても、アルミニウムとシリコンとが直接接触しないことによる種々の効果を奏することができる。アルミニウムとシリコンとは相互拡散しやすく、直接接触した状態で高温の熱処理を行うと、アルミニウムがシリコン層の内部に深く拡散してしまうという問題がある。また、アルミニウムからは、熱処理によってはヒロックを成長しやすく、配線の短絡などを引き起こす可能性がある。しかし、上記実施形態の構成によれば、第1導電層の上面および側面をヒロックが発生しにくい材料から形成した層で覆っているため、第1導電層の材料としてアルミニウムのようにヒロックを発生しやすい材料を用いても、配線の短絡を防止することができる。アルミニウムを主成分とする導電材料は、比抵抗の低い材料であり、電極・配線として好んで用いられる傾向にあるが、ヒロックを形成しやすいという欠点を有している。本発明によれば、第2導電層が第1導電層の上面から延びるヒロックの発生を効果的に抑制する一方、絶縁性保護層が第1導電層の側面から延びるヒロックの発生を効果的に抑制する。なお、第1導電層の厚さが比較的薄い場合は、第1導電層の側面から延びるヒロックの問題はさほど重要ではないが、今後、第1導電層の抵抗を低下させるために第1導電層を厚くしてゆくと、側面からのヒロックが重要な不良要因となり得る。しかし、上記の各実施形態によれば、第1導電層と半導体層との間に配置した絶縁保護層によってこのような側面ヒロックの発生を効果的に抑制できる。
【0092】
第1導電層の材料(第1導電材料)は、アルミニウムに限定されない。アルミニウムに他の元素が添加された合金や複合材料であっても、ZnOまたはZnOを主成分とした化合物半導体との間で電蝕反応が生じると考えられるため、本発明の構成を採用することによる効果がある。
【0093】
更に、アルミニウムを実質的に含有しない導電材料から第1導電層を形成する場合であっても、その側面が絶縁性保護層で覆われているため、少なくとも短絡や断線が生じにくいという効果が得られると考えられる。このため、本発明によれば、第1導電層の材料および半導体層の材料の組合せによらず、半導体装置の信頼性が向上すると考えられる。
【0094】
(実施形態5)
図8を参照しながら、本発明による半導体装置の第5の実施形態を説明する。
【0095】
本実施形態に特徴的な点は、ソース電極25aおよびドレイン電極25bの各々が第1導電層2および第2導電層3の積層構造を有しているが、第1導電層2の側面に絶縁性保護層が存在していない点にある。
【0096】
本実施形態によれば、第1導電層2の上面と半導体層4の下面との直接的な接触が避けられるが、第1導電層2の側面と半導体層4の下面との間が直接接触している。このため、第1導電層2の上面の面積に比べて第1導電層2の側面の面積が格段に小さい場合や、第1導電層2の側面に形成される自然酸化膜によって第1導電層2と半導体層4との間の電気的抵抗が充分に高い場合、局部電池反応による電蝕をある程度抑制することが可能である。また、本実施形態によれば、絶縁性保護層を形成する工程が不要になるため、製造工程を単純化できるという利点がある。
【0097】
(実施形態6)
図9を参照しながら、本発明による半導体装置の第6の実施形態を説明する。
【0098】
本実施形態に特徴的な点は、ソース・ドレイン電極25a、25bが第1導電層2および第2導電層3の積層構造を有しており、しかも、第2導電層3が第1導電層2の側面をも覆っている点にある。
【0099】
本実施形態によれば、第1導電層2の半導体層4との直接的な接触を避けることができるため、局部電池反応による電蝕をある充分に抑制することができる。ただし、ソース電極25aとドレイン電極25bとの間において、第2導電層3を電気的に分離する必要がある。このため、第2導電層3を基板1の上面に堆積した後、フォトリソグラフィ工程およびエッチング工程により、第2導電層3をパターニングする工程が付加的に必要になる。
【0100】
なお、選択成長法により、第1導電層2の上面および側面にのみに第2導電層3を選択的に成長させることができれば、上記のフォトリソグラフィ工程およびエッチング工程は不要である。
【0101】
【発明の効果】
本発明によれば、第1導電層の上面と半導体層との間に第2導電層を配置しているため、第1導電層の材料として半導体層との間で電蝕しやすい材料を用いたとしても、局部電池反応を抑制し、それによって電蝕を抑制することが可能である。更に、第1半導体層の側面と半導体層との間に絶縁性保護層を設けることにより、電蝕防止効果を更に高めるとともに、第1導電層の側面から延びるヒックに起因した断線などを効果的に防止することが可能になる。
【0102】
本発明によれば、透明半導体として注目されているZnOやZnOを主成分とする化合物半導体から半導体層を形成し、かつ、電極・配線材料として低抵抗であるが電蝕反応を引き起こしやすいアルミニウムまたはアルミニウム合金を用いることが可能になる。
【図面の簡単な説明】
【図1】従来の半導体装置を示す断面図である。
【図2】本発明による半導体装置の第1の実施形態を示す断面図である。
【図3】(a)および(b)は、本発明による半導体装置の第1の実施形態の製造方法を示す工程断面図である。
【図4】本発明による半導体装置の第2の実施形態を示す断面図である。
【図5】(a)および(b)は、本発明による半導体装置の第2の実施形態の製造方法を示す工程断面図である。
【図6】本発明による半導体装置の第3の実施形態を示す断面図である。
【図7】本発明による半導体装置の第4の実施形態を示す断面図である。
【図8】本発明による半導体装置の第5の実施形態を示す断面図である。
【図9】本発明による半導体装置の第6の実施形態を示す断面図である。
【符号の説明】
1 ・・・ 基板
2 ・・・ ソース・ドレイン電極の第1導電層
3 ・・・ ソース・ドレイン電極の第2導電層
4 ・・・ 半導体層
5 ・・・ ゲート絶縁層
6 ・・・ ゲート電極
7 ・・・ 絶縁性保護層
8 ・・・ レジストマスク
10・・・ 第1電極の第1導電層
11・・・ 第1電極の第2導電層
12・・・ 第2電極
20a・・・ソース電極
20b・・・ドレイン電極
25a・・・ソース電極
25b・・・ドレイン電極
30・・・ 第1電極[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
A semiconductor portion of a thin film transistor used for a display panel of a liquid crystal display device is usually formed of amorphous silicon (a-Si) or polycrystalline silicon (poly-Si).
[0003]
Since these semiconductor materials absorb visible light, electron-hole pairs are formed in the semiconductor by light irradiation, and the transistor characteristics deteriorate. Specifically, even when the transistor is off, carriers are generated in the channel region of the semiconductor layer by light irradiation, so that a current flows between the source region and the drain region. The current flowing through the transistor when the transistor is off is called “off-leakage current”. If this value is large, there is a problem that the display panel does not operate normally. Therefore, a pattern of a light-shielding film is formed so that light does not irradiate the semiconductor layer. However, forming a pattern of the light-shielding film requires a deposition step of the light-shielding film and a photolithography / etching step, which complicates the process.
[0004]
In order to solve such a problem, in recent years, a transparent transistor formed from zinc oxide (ZnO) or a compound semiconductor containing ZnO as a main component, which is a direct transition type semiconductor having a wide band gap of 3.4 eV. Is attracting attention. Such a transparent transistor has the advantage that the band gap of the semiconductor is larger than the light energy in the visible light band and does not absorb visible light, so that the off-leak current does not increase even when irradiated with light. I have.
[0005]
A staggered thin film transistor using ZnO for a semiconductor layer is disclosed in, for example,
[0006]
The thin film transistor of FIG. 1 has a
[0007]
This thin film transistor has a staggered configuration having source /
[0008]
On the other hand, with the recent increase in size and definition of display panels, as the material of the source /
[0009]
[Patent Document 1]
JP 2000-150900 A
[0010]
[Problems to be solved by the invention]
However, according to the study of the present inventor, when Al is used as the conductive material for the source /
[0011]
Such defects and defects were caused by contact of the thin film transistor with moisture in a solution containing an electrolyte such as a developer or in the air. For this reason, it is considered that a local battery reaction occurs at a contact portion between the source /
[0012]
The present invention has been made in view of the above circumstances, and a purpose thereof is to generate defects and defects due to electrolytic corrosion even when a semiconductor layer is formed from ZnO and aluminum is used as an electrode and wiring material. There is not to provide a semiconductor device.
[0013]
[Means for Solving the Problems]
A semiconductor device according to the present invention is a semiconductor device including a substrate, at least one electrode supported by the substrate, and a semiconductor layer in contact with at least a part of an upper surface of the electrode, wherein the electrode includes: A first conductive layer formed of a first conductive material; and a second conductive layer disposed between an upper surface of the first conductive layer and the semiconductor layer and formed of a second conductive material different from the first conductive material. A conductive layer; and an insulating protective layer located between a lower surface of the semiconductor layer and a side surface of the first conductive layer.
[0014]
In a preferred embodiment, the semiconductor layer is formed of a semiconductor having a band gap of 3 eV or more.
[0015]
In a preferred embodiment, the semiconductor layer is made of ZnO or a compound semiconductor containing ZnO as a main component.
[0016]
In a preferred embodiment, the first conductive material mainly includes aluminum.
[0017]
In a preferred embodiment, the insulating protective layer is formed from an oxide and / or a nitride of the first conductive material.
[0018]
In a preferred embodiment, the specific resistance of the first conductive material is lower than the specific resistance of the second conductive material, and the second conductive material is less susceptible to corrosion due to a local battery reaction than the first conductive material. .
[0019]
In a preferred embodiment, ohmic contact occurs between the second conductive material and the semiconductor layer.
[0020]
In a preferred embodiment, the second conductive material is a Group IV, V, or VI metal or a nitride of these metals.
[0021]
In a preferred embodiment, the metal is at least one metal selected from the group consisting of Ti, Ta, and Mo.
[0022]
In a preferred embodiment, the at least one electrode includes two electrodes formed at separate positions on the substrate.
[0023]
In a preferred embodiment, the insulating protective layer in each of the two electrodes is continuous on the substrate.
[0024]
In a preferred embodiment, the insulating protective layer is formed from a material that transmits visible light.
[0025]
In a preferred embodiment, the insulating protective layer is made of
[0026]
In a preferred embodiment, the semiconductor device further includes a second electrode disposed on the upper surface side of the semiconductor layer and in contact with the semiconductor layer.
[0027]
In a preferred embodiment, the two electrodes are a source electrode and a drain electrode, respectively, and the second electrode faces the semiconductor layer via a gate insulating film formed on an upper surface of the semiconductor layer. It is a gate electrode.
[0028]
A display device according to the present invention includes any one of the semiconductor devices described above.
[0029]
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device, comprising: a step of forming at least one electrode on a substrate; and a step of forming a semiconductor layer so as to cover the electrode. Forming a first conductive material film; depositing a second conductive material film other than the first conductive material film on the first conductive layer material film; Forming a layered structure including a first conductive layer formed of the first conductive material and a second conductive layer formed of the second conductive material by patterning a film; Forming an insulating protective layer covering at least a part of the side surface of the layer.
[0030]
In a preferred embodiment, the steps of patterning the two films include: depositing a resist mask on the two films; and etching a portion of the two films not covered by the resist mask. including.
[0031]
In a preferred embodiment, the step of forming the insulating protective layer includes a step of oxidizing and / or nitrogen side surfaces of the first conductive layer.
[0032]
In a preferred embodiment, the step of forming the insulating protective layer includes, before removing the resist mask, a step of depositing an insulating film on a substrate, and removing the resist mask to form the insulating film. Lifting off unnecessary portions and leaving a part of the insulating film on side surfaces of the first conductive layer.
[0033]
Another semiconductor device according to the present invention is a semiconductor device comprising a substrate, at least one electrode supported by the substrate, and a semiconductor layer in contact with at least a part of an upper surface of the electrode, wherein the semiconductor device The layer is made of ZnO or a compound semiconductor containing ZnO as a main component, and the electrode is made of a first conductive layer made of a first conductive material containing aluminum as a main component, and an upper surface of the first conductive layer. And a second conductive layer formed of a second conductive material different from the first conductive material, the second conductive material being disposed between the semiconductor layer and the first conductive material. Corrosion due to a local battery reaction is less likely to occur.
[0034]
In a preferred embodiment, the second conductive layer covers both a top surface and a side surface of the first conductive layer.
[0035]
In a preferred embodiment, the at least one electrode includes two electrodes formed at separate positions on the substrate, and the second conductive layer in each of the two electrodes is formed on the substrate. Electrically isolated.
[0036]
In a preferred embodiment, ohmic contact occurs between the second conductive material and the semiconductor layer.
[0037]
In a preferred embodiment, the second conductive material is a Group IV, V, or VI metal or a nitride of these metals.
[0038]
In a preferred embodiment, the metal is at least one metal selected from the group consisting of Ti, Ta, and Mo.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0040]
(Embodiment 1)
First, the configuration of a first embodiment of a semiconductor device according to the present invention will be described with reference to FIG. The semiconductor device of the present embodiment is an active matrix substrate suitably used for a display panel such as a liquid crystal display device.
[0041]
Note that the term "semiconductor device" in this specification does not refer to a semiconductor element itself such as a thin film transistor formed over a substrate, but refers to a structure including a substrate over which a semiconductor element such as a thin film transistor is formed, or A device equipped with an object shall be widely referred to. Further, a semiconductor element formed over a substrate is not limited to a three-terminal element such as a thin film transistor, and includes a diode functioning as a light-emitting element or a switching element.
[0042]
Hereinafter, for simplicity, the present embodiment will be described in detail focusing on a single thin film transistor on an active matrix substrate in which a plurality of thin film transistors are arranged in a matrix composed of rows and columns. Although only a single thin film transistor is illustrated in the drawings, a plurality of thin film transistors are formed on an actual substrate.
[0043]
As shown in FIG. 2, the semiconductor device of the present embodiment includes a
[0044]
The
[0045]
The
[0046]
The
[0047]
Each of the source /
[0048]
In the present embodiment, since direct contact between the first
[0049]
As the material of the second conductive layer 3 (second conductive material), a material that is less likely to cause corrosion due to a local battery reaction between the semiconductor layers 4 than the material of the first conductive layer 2 (first conductive material) is used. It is also preferable to select a material that makes ohmic contact with the
[0050]
When a semiconductor other than ZnO or a compound semiconductor containing ZnO as a main component is used as a material of the
[0051]
The thickness of the second
[0052]
As the material of the first conductive layer 2 (first conductive material), high-purity aluminum is used from the viewpoint of low specific resistance. However, an aluminum alloy to which an additive is added may be used instead. . Aluminum has a problem that hillocks easily grow after a high-temperature process. However, as in this embodiment, the upper surface is covered with the second
[0053]
A preferred thickness range of the first
[0054]
It is preferable that the thickness of the insulating
[0055]
In this embodiment, the insulating
[0056]
Hereinafter, a method of manufacturing the thin film transistor of FIG. 2 will be described.
[0057]
First, an Al film having a thickness (for example, 100 nm) selected from the range of 50 to 700 nm is deposited on the
[0058]
Next, as shown in FIG. 3A, the shape of the wiring formed integrally with the source / drain electrodes and the source /
[0059]
Next, by etching a portion of the Al / Ti laminated film that is not covered with the resist
[0060]
Next, an insulating
[0061]
It is also possible to form the insulating
[0062]
In the present embodiment, the oxide is formed on the side surface of the first
[0063]
Next, a ZnO film (thickness: for example, 100 nm) and
[0064]
Next, a resist mask for defining the pattern of the gate electrode / wiring is formed by photolithography, and Al / SiO 2 A portion of the / ZnO laminated film not covered with the resist mask is continuously etched. This etching is preferably performed using a highly anisotropic dry etching method using plasma or the like. Thereafter, a peeling and cleaning step is performed to remove the resist mask. Thus, as shown in FIG. 2, the
[0065]
According to the method of the present embodiment, the
[0066]
In the staggered thin film transistor manufactured in this manner, since contact between Al and ZnO can be completely avoided, an electrolytic corrosion reaction does not occur between Al and ZnO, and occurrence of wiring failure can be prevented. .
[0067]
(Embodiment 2)
Hereinafter, a second embodiment of the semiconductor device according to the present invention will be described with reference to FIG.
[0068]
The difference between the semiconductor device according to the present embodiment and the semiconductor device according to the first embodiment lies in the configuration of the source /
[0069]
The source /
[0070]
One of the features of the present embodiment is that the insulating
[0071]
Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS.
[0072]
First, an alkali-free glass substrate (Corning 1737 glass) 1 is prepared as an insulating
[0073]
Next, portions of the Ti / Al laminated film that are not covered by the resist
[0074]
Through the above steps, the structure shown in FIG. 5A is obtained. Next, without removing the resist
[0075]
Thereafter, a step of removing the resist
[0076]
Next, a ZnO film (thickness: for example, 100 nm) and
[0077]
Next, a resist mask (not shown) for defining a gate electrode / wiring pattern is formed by photolithography, and Al / SiO 2 A portion of the / ZnO laminated film not covered with the resist mask is continuously etched. This etching is preferably performed by a highly anisotropic dry etching method using plasma. Thereafter, a peeling and cleaning step is performed to remove the resist mask. Thus, the
[0078]
In the staggered thin film transistor manufactured by the above method, since Al and ZnO are not in contact with each other, an electrolytic corrosion reaction between Al and ZnO is suppressed.
[0079]
In this embodiment, the insulating
[0080]
In addition, since the insulating
[0081]
When the thin film transistors according to the first and second embodiments are used as switching elements in an image display area of a liquid crystal display device, the
[0082]
When a liquid crystal display device is manufactured using the active matrix substrate in each of the above embodiments, a liquid crystal panel is formed by sealing liquid crystal between the opposing substrate and the active matrix substrate by a known manufacturing method. Just fine.
[0083]
(Embodiment 3)
Next, a third embodiment of the semiconductor device according to the present invention will be described with reference to FIG.
[0084]
In this embodiment, a thin film diode is formed on a substrate instead of a thin film transistor. As shown in FIG. 6, the semiconductor device of the present embodiment includes a
[0085]
In the present embodiment, the
[0086]
Hereinafter, a method for manufacturing the semiconductor device of FIG. 6 will be described.
[0087]
First, an insulating
[0088]
Next, the insulating
[0089]
Also in the thin-film diode shown in FIG. 6, since the contact between Al and ZnO is completely avoided, the electrolytic corrosion reaction between Al and ZnO is suppressed.
[0090]
(Embodiment 4)
FIG. 7 shows a cross-sectional configuration of a thin film diode manufactured by the same method as in the above-described third embodiment, except that the insulating
[0091]
In each of the embodiments described above, the semiconductor layer is formed from ZnO, but the present invention is not limited to this. Even when the semiconductor layer is formed from a compound semiconductor containing ZnO as a main component, the effect of preventing electric corrosion of the present invention is exhibited. In addition, even when a silicon layer is used as a semiconductor layer, various effects can be obtained due to direct contact between aluminum and silicon. Aluminum and silicon are liable to mutually diffuse, and if a high-temperature heat treatment is performed in a state of direct contact, there is a problem that aluminum deeply diffuses into the silicon layer. In addition, hillocks are likely to grow from aluminum depending on the heat treatment, which may cause a short circuit in wiring. However, according to the configuration of the above-described embodiment, since the upper surface and the side surfaces of the first conductive layer are covered with a layer formed of a material that is unlikely to generate hillocks, a hillock is generated as a material of the first conductive layer like aluminum. Even if a material that is easy to use is used, a short circuit of the wiring can be prevented. A conductive material containing aluminum as a main component is a material having a low specific resistance and tends to be preferably used as an electrode or a wiring, but has a disadvantage that a hillock is easily formed. According to the present invention, while the second conductive layer effectively suppresses the generation of hillocks extending from the upper surface of the first conductive layer, the insulating protective layer effectively reduces the generation of hillocks extending from the side surface of the first conductive layer. Suppress. When the thickness of the first conductive layer is relatively small, the problem of the hillock extending from the side surface of the first conductive layer is not so important. As the layer becomes thicker, hillocks from the sides can be an important factor of failure. However, according to each of the above embodiments, the occurrence of such side hillocks can be effectively suppressed by the insulating protective layer disposed between the first conductive layer and the semiconductor layer.
[0092]
The material of the first conductive layer (first conductive material) is not limited to aluminum. Even in the case of an alloy or a composite material in which other elements are added to aluminum, it is considered that an electrolytic corrosion reaction occurs with ZnO or a compound semiconductor containing ZnO as a main component. Has the effect.
[0093]
Further, even when the first conductive layer is formed from a conductive material substantially not containing aluminum, the side surface is covered with the insulating protective layer, so that an effect that at least a short circuit or disconnection hardly occurs is obtained. It is thought that it is possible. For this reason, according to the present invention, it is considered that the reliability of the semiconductor device is improved regardless of the combination of the material of the first conductive layer and the material of the semiconductor layer.
[0094]
(Embodiment 5)
A fifth embodiment of the semiconductor device according to the present invention will be described with reference to FIG.
[0095]
A feature of the present embodiment is that each of the
[0096]
According to the present embodiment, direct contact between the upper surface of the first
[0097]
(Embodiment 6)
The sixth embodiment of the semiconductor device according to the present invention will be described with reference to FIG.
[0098]
A feature of this embodiment is that the source /
[0099]
According to the present embodiment, direct contact of the first
[0100]
Note that if the second
[0101]
【The invention's effect】
According to the present invention, since the second conductive layer is disposed between the upper surface of the first conductive layer and the semiconductor layer, a material that is easily corroded between the semiconductor layer and the first conductive layer is used as the material of the first conductive layer. Even if it does, it is possible to suppress the local battery reaction and thereby suppress the electrolytic corrosion. Furthermore, by providing an insulating protective layer between the side surface of the first semiconductor layer and the semiconductor layer, the effect of preventing electrolytic corrosion can be further enhanced, and disconnection caused by a hick extending from the side surface of the first conductive layer can be effectively prevented. Can be prevented.
[0102]
According to the present invention, a semiconductor layer is formed from ZnO or a compound semiconductor containing ZnO as a main component, which is attracting attention as a transparent semiconductor, and aluminum or aluminum which has low resistance as an electrode / wiring material but easily causes an electrolytic corrosion reaction is used. It becomes possible to use an aluminum alloy.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a conventional semiconductor device.
FIG. 2 is a sectional view showing a first embodiment of a semiconductor device according to the present invention.
FIGS. 3A and 3B are process cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a sectional view showing a second embodiment of the semiconductor device according to the present invention.
FIGS. 5A and 5B are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a sectional view showing a third embodiment of the semiconductor device according to the present invention.
FIG. 7 is a sectional view showing a fourth embodiment of the semiconductor device according to the present invention;
FIG. 8 is a sectional view showing a fifth embodiment of the semiconductor device according to the present invention.
FIG. 9 is a sectional view showing a sixth embodiment of a semiconductor device according to the present invention.
[Explanation of symbols]
1 ... substrate
2... First conductive layer of source / drain electrode
3... Second conductive layer of source / drain electrode
4 ... semiconductor layer
5 ... gate insulating layer
6 ... gate electrode
7 ... Insulating protective layer
8 Resist mask
10 first conductive layer of first electrode
11... Second conductive layer of first electrode
12 second electrode
20a: Source electrode
20b ... Drain electrode
25a: Source electrode
25b ... Drain electrode
30 first electrode
Claims (26)
前記基板に支持されている少なくとも1つの電極と、
前記電極の上面の少なくとも一部に接触する半導体層と、
を備えた半導体装置であって、
前記電極は、
第1導電材料から形成された第1導電層と、
前記第1導電層の上面と前記半導体層との間に配置され、前記第1導電材料とは異なる第2導電材料から形成された第2導電層と、
前記半導体層の下面と前記第1導電層の側面との間に位置する絶縁性保護層と、
を有している半導体装置。Board and
At least one electrode supported on the substrate;
A semiconductor layer that contacts at least a part of the upper surface of the electrode,
A semiconductor device comprising:
The electrode is
A first conductive layer formed from a first conductive material;
A second conductive layer formed between a top surface of the first conductive layer and the semiconductor layer and formed of a second conductive material different from the first conductive material;
An insulating protective layer located between a lower surface of the semiconductor layer and a side surface of the first conductive layer;
A semiconductor device having:
前記第2の電極は、前記半導体層の上面に形成されたゲート絶縁膜を介して前記半導体層に対向するゲート電極である請求項11または12に記載の半導体装置。The two electrodes are a source electrode and a drain electrode, respectively.
The semiconductor device according to claim 11, wherein the second electrode is a gate electrode facing the semiconductor layer via a gate insulating film formed on an upper surface of the semiconductor layer.
前記電極を覆うように半導体層を形成する工程と
を含む半導体装置の製造方法であって、
前記電極を形成する工程は、
第1導電材料の膜を形成する工程と、
前記第1導電材料以外の第2導電材料の膜を前記第1導電層材料の膜の上に堆積する工程と、
前記2つの膜をパターニングすることにより、前記第1導電材料から形成された第1導電層と、前記第2導電材料から形成された第2導電層とを含む積層構造を形成する工程と、
前記第1導電層の側面の少なくとも一部を覆う絶縁性保護層を形成する工程と
を含む、製造方法。Forming at least one electrode on a substrate;
Forming a semiconductor layer so as to cover the electrode, a method of manufacturing a semiconductor device,
The step of forming the electrode,
Forming a film of a first conductive material;
Depositing a film of a second conductive material other than the first conductive material on the film of the first conductive layer material;
Forming a stacked structure including a first conductive layer formed from the first conductive material and a second conductive layer formed from the second conductive material by patterning the two films;
Forming an insulating protective layer covering at least a part of the side surface of the first conductive layer.
前記2つの膜の上にレジストマスクを堆積する工程と、
前記2つの膜のうちレジストマスクで覆われてない部分をエッチングする工程とを含む請求項17に記載の製造方法。Patterning the two films,
Depositing a resist mask on the two films;
Etching the portion of the two films that is not covered with the resist mask.
前記レジストマスクを除去する前に、絶縁膜を基板上に堆積する工程と、
前記レジストマスクを除去することにより、前記絶縁膜の不要部分のリフトオフを行い、前記絶縁膜の一部を前記第1導電層の側面に残置する工程と、
を含む請求項17に記載の製造方法。The step of forming the insulating protective layer,
Before removing the resist mask, depositing an insulating film on the substrate,
Removing the resist mask, performing a lift-off of an unnecessary portion of the insulating film, and leaving a part of the insulating film on a side surface of the first conductive layer;
The method according to claim 17, comprising:
前記基板に支持されている少なくとも1つの電極と、
前記電極の上面の少なくとも一部に接触する半導体層と、
を備えた半導体装置であって、
前記半導体層は、ZnOまたはZnOを主成分とした化合物半導体から形成されており、
前記電極は、
アルミニウムを主成分とする第1導電材料から形成された第1導電層と、
前記第1導電層の上面と前記半導体層との間に配置され、前記第1導電材料とは異なる第2導電材料から形成された第2導電層と、
を有しており、
前記第2導電材料は、前記第1導電材料に比べて局部電池反応による腐食が生じにくい半導体装置。Board and
At least one electrode supported on the substrate;
A semiconductor layer that contacts at least a part of the upper surface of the electrode,
A semiconductor device comprising:
The semiconductor layer is formed of ZnO or a compound semiconductor containing ZnO as a main component,
The electrode is
A first conductive layer formed from a first conductive material containing aluminum as a main component,
A second conductive layer formed between a top surface of the first conductive layer and the semiconductor layer and formed of a second conductive material different from the first conductive material;
Has,
The semiconductor device, wherein the second conductive material is less likely to be corroded by a local battery reaction than the first conductive material.
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