US9240487B2 - Method of manufacturing thin film transistor and method of manufacturing organic light emitting display having thin film transistor - Google Patents

Method of manufacturing thin film transistor and method of manufacturing organic light emitting display having thin film transistor Download PDF

Info

Publication number
US9240487B2
US9240487B2 US12/266,797 US26679708A US9240487B2 US 9240487 B2 US9240487 B2 US 9240487B2 US 26679708 A US26679708 A US 26679708A US 9240487 B2 US9240487 B2 US 9240487B2
Authority
US
United States
Prior art keywords
semiconductor layer
forming
layer
thin film
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US12/266,797
Other versions
US20090155940A1 (en
Inventor
Hun-Jung Lee
Jae-Kyeong Jeong
Hyun-Soo Shin
Jong-Han Jeong
Jin-Seong Park
Steve Y. G. Mo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Assigned to SAMSUNG MOBILE DISPLAY CO., LTD. reassignment SAMSUNG MOBILE DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JEONG, JAE-KYEONG, JEONG, JONG-HAN, LEE, HUN-JUNG, MO, STEVE Y.G., PARK, JIN-SEONG, SHIN, HYUN-SOO
Publication of US20090155940A1 publication Critical patent/US20090155940A1/en
Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: SAMSUNG MOBILE DISPLAY CO., LTD.
Application granted granted Critical
Publication of US9240487B2 publication Critical patent/US9240487B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H01L27/3244—
    • H01L27/3262—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • aspects of the present invention relate to a method of manufacturing a thin film transistor and a method of manufacturing an organic light emitting display having the thin film transistor, and more particularly to a method of manufacturing a thin film transistor having a compound semiconductor containing oxygen as a semiconductor layer and a method of manufacturing an organic light emitting display having the thin film transistor.
  • a thin film transistor includes a semiconductor layer including a channel region and source and drain regions, and a gate electrode formed on the channel region and electrically insulated from the semiconductor layer by a gate insulating layer.
  • the semiconductor layer of the thin film transistor configured as above is generally formed of amorphous silicon or poly-silicon. However, if the semiconductor layer is formed of amorphous silicon, charge mobility in the semiconductor layer is low and causes difficulties in implementing a driving circuit to be operated at high speeds. If the semiconductor is formed of the poly-silicon, charge mobility in the semiconductor layer is high whereas threshold voltage in the semiconductor layer becomes uneven and results in additional use of a separate compensation circuit.
  • LTPS low temperature poly-silicon
  • Japanese Patent Publication No. 2004-273614 discloses a thin film transistor using zinc oxide (ZnO) or a compound semiconductor using zinc oxide (ZnO) as a main ingredient as the semiconductor layer.
  • the compound semiconductor is used as the semiconductor layer, a problem arises in that conductivity is reduced due to infiltration of hydrogen (H) when exposed to air.
  • the hydrogen infiltrated into a surface part of the compound semiconductor layer acts as a shallow donor to reduce the conductivity of the semiconductor layer, and such a reduction of the conductivity intensifies according to the exposed time thereof. Therefore, owing to the reduction of the conductivity on the channel region, the electrical property of the thin film transistor is deteriorates, thereby leading to an increase in a leakage current, etc.
  • aspects of the present invention include a method of manufacturing a thin film transistor capable of preventing or reducing an electrical property change of a semiconductor layer due to diffusion (infiltration) of hydrogen ions and a method of manufacturing an organic light emitting display having the thin film transistor.
  • Another aspect of the present invention includes a method of manufacturing a thin film transistor having improved electrical property and reliability, and a method of manufacturing an organic light emitting display having the thin film transistor.
  • An aspect of the present invention includes a method of manufacturing a thin film transistor, including: forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer including oxygen ions on the gate insulating layer, and including a channel region, a source region, and a drain region; forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively; and forming a passivation layer on the semiconductor layer by coating a material, wherein a carrier density of the semiconductor layer is 1E+17 to 1E+18/cm 3 .
  • An aspect of the present invention includes a method of manufacturing a thin film transistor, including: forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer including oxygen ions, on the gate insulating layer, and including a channel region, a source region, and a drain region; forming a passivation layer on the semiconductor layer by coating a material; forming a photoresist film on the passivation layer and then patterning the photoresist film to expose the source region and drain region of the semiconductor layer; and forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively, wherein a carrier density of the semiconductor layer is 1E+17 to 1E+18/cm 3 .
  • An aspect of the present invention includes a method of manufacturing an organic light emitting display having a thin film transistor, including: forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer including oxygen ions on the gate insulating layer, and including a channel region, a source region, and a drain region; forming a passivation layer on the semiconductor layer by coating a material; forming a photoresist film on the passivation layer and then patterning the photoresist film to expose the source region and drain region of the semiconductor layer; forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively; forming a planarization layer over the source electrode or the drain electrode and patterning the planarization layer to expose the source electrode or the drain electrode; forming a first electrode to contact the source electrode or the drain electrode exposed on the planarization layer; forming a pixel definition layer over the first electrode and exposing the first electrode in the light emitting region
  • An aspect of the present invention includes a thin film transistor, including: a substrate; a compound semiconductor layer formed over the substrate, and including a channel region, a source region, and a drain region; a gate electrode formed to correspond to the channel region; and a passivation layer over the substrate and the thin film transistor to seal the compound semiconductor from intrusion of hydrogen.
  • An aspect of the present invention includes a method of manufacturing a thin film transistor, including: forming the thin film transistor on a substrate, the thin film transistor including a compound semiconductor layer comprising a channel region, a source region, and a drain region; and forming a passivation layer over the substrate and the thin film transistor to seal the compound semiconductor from intrusion of hydrogen.
  • FIG. 1 is a cross-sectional view explaining a thin film transistor according to a first aspect of the present invention.
  • FIG. 2 is a cross-sectional view explaining a thin film transistor according to a second aspect of the present invention.
  • FIGS. 3A to 3D are cross-sectional views explaining a method of manufacturing a thin film transistor according to the first aspect of the present invention.
  • FIGS. 4A to 4E are cross-sectional views explaining a method of manufacturing a thin film transistor according to the second aspect of the present invention.
  • FIGS. 5A and 5B are graphs explaining electrical property of a thin film transistor according to aspects of the present invention.
  • FIGS. 6A and 6B are a plan view and a cross-sectional view explaining a method of manufacturing an organic light emitting display having a thin film transistor according to aspects of the present invention.
  • FIG. 7 is a cross-sectional view explaining a method of manufacturing an organic light emitting display having a thin film transistor according to an aspect of the present invention.
  • first element when a first element is described as being coupled to a second element, the first element may be not only directly coupled to the second element but may also be indirectly coupled to the second element via a third element. Further, some of the elements that are not essential to the complete understanding of the invention are omitted for clarity.
  • FIG. 1 is a cross-sectional view explaining a thin film transistor according to a first aspect of the present invention, wherein the thin film transistor having a bottom gate structure is shown, as an example.
  • a gate electrode 11 is formed on a substrate 10 formed of insulating material.
  • a gate insulating layer 12 is formed on an entire upper surface of the substrate 10 including the gate electrode 11 .
  • a semiconductor layer 13 is formed on the gate electrode 11 , is electrically insulated from the gate electrode 11 , and includes a channel region 13 a , a source region 13 b , and a drain region 13 c .
  • the semiconductor layer 13 is formed of a compound semiconductor including oxygen ions, wherein the channel region 13 a is formed to be overlapped with the gate electrode 11 .
  • zinc oxide (ZnO) or a compound semiconductor, etc., using zinc oxide (ZnO) doped with gallium (Ga), indium (In), tin (Sn), etc., as a main ingredient, may be used.
  • a source electrode 14 a and a drain electrode 14 b are formed on the semiconductor layer 13 to correspond to the source and drain regions 13 b and 13 c .
  • a conductive layer 15 to reduce a contact resistance between the source and drain electrodes 14 a and 14 b , and the semiconductor layer 13 may be formed therebetween.
  • a passivation layer 16 is formed over the source and drain electrodes 14 a and 14 b and the semiconductor layer 13 .
  • the passivation layer 16 is formed of at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB).
  • the passivation layer 16 entirely covers the semiconductor layer 13 and the source and drain electrodes 14 a and 14 b to seal them. Accordingly, the passivation layer 16 prevents or reduces infiltration of hydrogen into the semiconductor layer 13 .
  • FIG. 2 is a cross-sectional view explaining a thin film transistor according to a second aspect of the present invention, wherein the thin film transistor having a bottom gate structure is shown, as an example.
  • a buffer layer 21 is formed on a substrate 20 formed of insulating material, and a gate electrode 22 is formed on the buffer layer 21 .
  • a semiconductor layer 24 is formed on the gate electrode 22 , is electrically insulated from the gate electrode 22 by a gate insulating layer 23 , and includes a channel region 24 a , a source region 24 b , and a drain region 24 c .
  • the semiconductor layer 24 is formed of a compound semiconductor including oxygen ions, wherein the channel region 24 a is formed to be overlapped with the gate electrode 22 .
  • zinc oxide (ZnO) or a compound semiconductor, etc., using zinc oxide (ZnO) doped with gallium (Ga), indium (In), tin (Sn), etc., as a main ingredient, may be used.
  • a passivation layer 25 is formed on the entire semiconductor layer 24 , and is formed with contact holes to expose the source and drain regions 24 b and 24 c .
  • the passivation layer 25 is formed of at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB).
  • Source and drain electrodes 27 a and 27 b are formed on the passivation layer 25 , and are contacted to the respective source and drain regions 24 b and 24 c through the contact holes.
  • the passivation layer 25 entirely covers the semiconductor layer 24 and the source and drain electrodes 27 a and 27 b to seal them. Accordingly, the passivation layer 25 prevents or reduces infiltration of hydrogen into the semiconductor layer 24 .
  • FIGS. 3A to 3D are cross-sectional views explaining a method of manufacturing a thin film transistor according to the first aspect of the present invention.
  • a gate electrode 11 is formed on an insulating substrate 10 , and then, a gate insulating layer 12 is formed on an entire upper surface of the substrate 10 including the gate electrode 11 .
  • a semiconductor layer 13 is formed on the gate insulating layer 12 , and over the gate electrode 11 .
  • the semiconductor layer 13 includes a channel region 13 a, a source region 13 b , and a drain region 13 c .
  • the semiconductor layer 13 is a compound semiconductor including oxygen ions, wherein the semiconductor layer 13 may be formed of zinc oxide (ZnO) or a compound semiconductor, etc., using zinc oxide (ZnO) doped with gallium (Ga), indium (In), tin (Sn), etc., as a main ingredient.
  • metal is deposited and then patterned on an entire upper surface of the semiconductor layer 13 to form source and drain electrodes 14 a and 14 b that contact the respective source and drain regions 13 b and 13 c of the semiconductor layer 13 .
  • a conductive layer 15 to reduce a contact resistance between the source and drain electrodes 14 a and 14 b , and the semiconductor layer 13 may further be formed therebetween.
  • a passivation layer 16 is formed on an entire surface of the source and drain electrodes 14 a and 14 b , and that of the semiconductor layer 13 by performing a spin coating or a slit coating thereon of at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB). At this time, the organic material may be cured after being coated.
  • FIGS. 4A to 4E are cross-sectional views explaining a method of manufacturing a thin film transistor according to the second aspect of the present invention.
  • a gate electrode 22 is formed on or over an insulating substrate 20 , and then, a gate insulating layer 23 is formed on the gate electrode 22 and over the insulating substrate 20 .
  • a buffer layer 21 may be formed on the insulating substrate 20 before the gate electrode 22 is formed.
  • the buffer layer 21 may be formed of an insulating material such as silicon oxide or silicon nitride.
  • a semiconductor layer 24 is formed on the gate insulating layer 23 that covers the gate electrode 22 .
  • the semiconductor layer 24 includes a channel region 24 a , a source region 24 b , and a drain region 24 c .
  • the semiconductor layer 24 is a compound semiconductor including oxygen ions, and may be formed of zinc oxide (ZnO) or a compound semiconductor, etc., using zinc oxide (ZnO) doped with gallium (Ga), indium (In), tin (Sn), etc., as a main ingredient.
  • a passivation layer 25 is formed on an entire surface of the semiconductor layer 24 by performing a spin coating or a slit coating thereon of at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB).
  • a photoresist film 26 is formed and then patterned on the passivation layer 25 .
  • the passivation layer 25 in the exposed portion is etched through an etching process using the patterned photoresist film 26 as a mask. Accordingly, contact holes 25 a are formed to expose predetermined portions of the source region 24 b and the drain region 24 c .
  • the photoresist film 26 can be patterned through exposure and development processes using an established mask.
  • source and drain electrodes 27 a and 27 b are formed to be contacted to the source and drain regions 24 b and 24 c of the semiconductor layer 24 through the contact holes 25 a formed on the passivation layer 25 .
  • first and second aspects are described as having a spin coating or a slit coating thereon of a material, by way of example, any physical coating method that does not cause a reaction between materials may also be applied. Also, any material that can be patterned through a photolithography process using the photoresist film 26 can be used in addition to the noted materials.
  • the passivation layers 16 and 25 are formed by coating, for example, an organic material, such is not required.
  • the passivation layers 16 and 25 may be formed by depositing inorganic materials, such as, silicon oxide SiO 2 , silicon nitride SiN, or the like, with plasma deposition equipment.
  • inorganic materials such as, silicon oxide SiO 2 , silicon nitride SiN, or the like.
  • plasma deposition equipment such as hydrogen (H) ions are diffused (infiltrated) into the semiconductor layer to be reacted during the deposition process, a hydrogen density and composition ratio of the semiconductor layer may be changed due to damage by the plasma.
  • a carrier density of the semiconductor layer may increase by ⁇ 1E+20/cm 3 due to the increase of the hydrogen density, and the composition ratio of positive ions and negative ions may be changed due to the damage by the plasma.
  • the ratio (composition ratio) of positive ions and negative ions of InGaZnO may be represented as In x Ga y Zn 1 ⁇ x ⁇ y O z .
  • the carrier density of the semiconductor layer can be stably maintained in a range from about 1E+17 to 1E+18/cm 3 and the conductivity of the channel is not changed even with a composition difference as shown in the following mathematical equation 2.
  • the carrier density of the semiconductor layer between about 1E+19 and 1E+20 cm 3 allows the semiconductor layer to have a conductivity similar to that of metal, while the carrier density of the semiconductor layer less than 1E+15 cm 3 allows the semiconductor layer to have insulative properties.
  • FIG. 5A shows a transfer curve measurement of an electrical property of a thin film transistor to which a plasma enhanced chemical vapor deposition (PECVD) process and a dry etching process have been applied, and having a passivation layer formed with silicon nitride film SiN.
  • PECVD plasma enhanced chemical vapor deposition
  • SiN silicon nitride film
  • FIG. 5B shows a transfer curve measurement of an electrical property of a thin film transistor to which a spin coating process and a photolithography process have been applied, and having a passivation layer formed with organic material.
  • a physical method such as the spin coating process, is used that does not expose a semiconductor layer to hydrogen and does not generate a reaction between materials, and a photolithography process is used that does not cause plasma damage, it can be seen that a carrier density of the semiconductor layer is not changed, and thus a conductivity thereof is not changed.
  • aspects of the present invention uses the photolithography process that uses a photoresist film to pattern the passivation layers 16 and 25 , in order to expose the respective source electrodes 14 a and 27 a and drain electrodes 14 b and 27 b . Therefore, the photolithography process prevents or reduces damage to the passivation layers 16 and 25 arising from plasma etching even in subsequent processes, making it possible to effectively and uniformly maintain the conductivity of the channel.
  • the first and second aspects of the present invention describe a thin film transistor having a bottom gate structure.
  • aspects of the present invention can also be applied to a thin film transistor having any structures using a compound semiconductor, such as a top gate structure, etc., as a semiconductor layer.
  • FIG. 6A is a plan view explaining an organic light emitting display having a thin film transistor according to an aspect of the present invention.
  • FIG. 6A will be schematically explained focused on a display panel 200 displaying an image.
  • a substrate 210 includes a pixel region 220 , and a non-pixel region 230 that is peripheral to the pixel region 220 .
  • a portion of the substrate 210 corresponding to the pixel region 220 includes a plurality of organic light emitting elements 300 that are coupled between scan lines 224 and data lines 226 in a matrix arrangement.
  • a portion of the substrate 210 corresponding to the non-pixel region 230 is formed with portions of the scan lines 224 and data lines 226 that extend from the scan lines 224 and data lines 226 of the pixel region 220 , power supply lines (not shown) used in the operation of the organic light emitting elements 300 , and a scan driver 234 and a data driver 236 to process signals supplied from an external device through a pad 228 and to supply the process signals to the scan lines 224 and the data lines 226 .
  • FIG. 7 is a cross-sectional view explaining a method of manufacturing an organic light emitting display having a thin film transistor according to an aspect of the present invention.
  • an organic light emitting element 300 is formed of an anode electrode 317 , a cathode electrode 320 , and an organic thin film layer 319 formed between the anode electrode 317 and the cathode electrode 320 .
  • the organic thin film layer 319 may include a hole transport layer, an organic light emitting layer, and an electron transport layer.
  • the organic thin film layer 319 may further include a hole injection layer and an electron injection layer.
  • a capacitor to maintaining signals and a thin film transistor to control an operation of the organic light emitting element 300 may further be included.
  • the organic light emitting element 300 including the thin film transistor will be described in more detail with reference to FIGS. 6A and 7 .
  • the thin film transistor has the structure as shown in FIG. 1 or in FIG. 2 .
  • Such a thin film transistor can be manufactured according to a manufacturing method of aspects of the present invention with reference to FIGS. 3A to 3D or FIGS. 4A to 4E .
  • a thin film transistor having a structure as shown in FIG. 2 will be described by way of example.
  • a buffer layer 21 is formed on a substrate 210 , and a gate electrode 22 is formed on the buffer layer 21 in a pixel region 220 .
  • scan lines 224 coupled to the gate electrode 22 are formed in the pixel region 220 .
  • Scan lines 224 in the non-pixel region 230 are those that extend from the scan lines 224 in the pixel region 220 , and a pad 228 to receive signals from the external device, may be formed in the non-pixel region 230 .
  • a gate insulating layer 23 is formed on the upper surface of the buffer layer 21 that includes the gate electrode 22 .
  • a semiconductor layer 24 (that includes a channel region 24 a , a source region 24 b , and a drain region 24 c ) is formed on the gate insulating layer 23 and the gate electrode 22 .
  • the semiconductor layer 24 is a compound semiconductor including oxygen ions, and may be formed of zinc oxide (ZnO) or a compound semiconductor, etc., that uses zinc oxide doped with gallium (Ga), indium (In) and tin (Sn), etc., as a main ingredient.
  • a passivation layer 25 is formed over the entire semiconductor layer 24 and the gate insulating layer 23 by coating at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB).
  • a photoresist film 26 is formed on the passivation layer 25 , and then, the photoresist film 26 is patterned through an exposure process and development processes using an established mask.
  • the passivation layer 25 in an exposed portion is etched through an etching process using the patterned photoresist film 26 as a mask. Thereby, contact holes 25 a are formed to expose predetermined portions of a source region 24 b and a drain region 24 c.
  • source and drain electrodes 27 a and 27 b are formed in order to contact the source and drain regions 24 b and 24 c of the semiconductor layer 24 through the contact holes 25 a formed on a passivation layer 25 .
  • data lines 226 coupled to the source and drain electrodes 27 a and 27 b are formed in a pixel region 220 .
  • Data lines 226 in the non pixel region 230 are those that extend from the data lines 226 in the pixel region 220 , and a pad 228 to receive signals from the external device may be formed in the non-pixel region 230 .
  • a planarization layer 30 is formed on an entire upper surface of the passivation layer 25 , and the source and drain electrodes 27 a and 27 b to form a planar surface.
  • a via hole is formed in the planarization layer 30 in order to expose a predetermined portion of the source electrode 27 a or drain electrode 27 b .
  • an anode electrode 317 is formed and coupled to the source electrode 27 a or the drain electrode 27 b through the via hole.
  • a pixel definition layer 318 is formed on the planarization layer 30 to expose some region (a light emitting region) of the anode electrode 317 , and an organic thin film layer 319 is formed on the exposed region of anode electrode 317 .
  • a cathode electrode 320 is formed on the pixel definition film 318 and the organic thin film layer 319 .
  • an encapsulation substrate 400 to encapsulate a pixel region 220 is disposed over the substrate 210 having the organic light emitting elements 300 .
  • the encapsulation substrate 400 is bonded to the substrate 210 by a sealing material 410 to complete a display panel 200 .
  • aspects of the present invention form a passivation layer by coating organic material through a physical method, such as, a spin coating process where a reaction between materials does not occur, and patterns the passivation layer through a pattern process using a photoresist film. Accordingly, a change of a hydrogen density of a semiconductor layer, a change of composition ratio due to diffusion (infiltration) of hydrogen, and plasma damage are effectively prevented or reduced. Therefore, specific resistance in a channel region is controlled, conductivity in the channel region is stably maintained, making it possible to improve the electrical property of a thin film transistor, such as a non-generation of leakage current, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

A method of manufacturing a thin film transistor having a compound semiconductor with oxygen as a semiconductor layer and a method of manufacturing an organic light emitting display having the thin film transistor include: forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer including oxygen ions on the gate insulating layer, and including a channel region, a source region, and a drain region; forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively; and forming a passivation layer on the semiconductor layer by coating an organic material, wherein a carrier density of the semiconductor layer is maintained in the range of 1E+17 to 1E+18/cm3 to have stable electrical property.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2007-133508 filed on Dec. 18, 2007 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
Aspects of the present invention relate to a method of manufacturing a thin film transistor and a method of manufacturing an organic light emitting display having the thin film transistor, and more particularly to a method of manufacturing a thin film transistor having a compound semiconductor containing oxygen as a semiconductor layer and a method of manufacturing an organic light emitting display having the thin film transistor.
2. Description of the Related Art
Generally, a thin film transistor includes a semiconductor layer including a channel region and source and drain regions, and a gate electrode formed on the channel region and electrically insulated from the semiconductor layer by a gate insulating layer. The semiconductor layer of the thin film transistor configured as above is generally formed of amorphous silicon or poly-silicon. However, if the semiconductor layer is formed of amorphous silicon, charge mobility in the semiconductor layer is low and causes difficulties in implementing a driving circuit to be operated at high speeds. If the semiconductor is formed of the poly-silicon, charge mobility in the semiconductor layer is high whereas threshold voltage in the semiconductor layer becomes uneven and results in additional use of a separate compensation circuit.
Also, a method of manufacturing a typical thin film transistor using low temperature poly-silicon (LTPS) involves high-cost processes such as laser annealing, etc., and control of its property is difficult, and leads to a difficulty in applying the technique to a large area substrate.
In view of the above problems, a study is under way to use the compound semiconductor as the semiconductor layer. Japanese Patent Publication No. 2004-273614 discloses a thin film transistor using zinc oxide (ZnO) or a compound semiconductor using zinc oxide (ZnO) as a main ingredient as the semiconductor layer.
However, if the compound semiconductor is used as the semiconductor layer, a problem arises in that conductivity is reduced due to infiltration of hydrogen (H) when exposed to air. The hydrogen infiltrated into a surface part of the compound semiconductor layer acts as a shallow donor to reduce the conductivity of the semiconductor layer, and such a reduction of the conductivity intensifies according to the exposed time thereof. Therefore, owing to the reduction of the conductivity on the channel region, the electrical property of the thin film transistor is deteriorates, thereby leading to an increase in a leakage current, etc.
Regarding the reduction of the conductivity of the semiconductor layer due to infiltration of hydrogen, a thesis titled, “Role of Intentionally Incorporated Hydrogen I Wide-Band-Gap ZnO Thin Film Prepared by Photo-MOCVD Technique”, cP772, Physics of Semiconductors; 27th International Conference on the Physics of Semiconductors may be referred to.
SUMMARY OF THE INVENTION
Therefore, aspects of the present invention include a method of manufacturing a thin film transistor capable of preventing or reducing an electrical property change of a semiconductor layer due to diffusion (infiltration) of hydrogen ions and a method of manufacturing an organic light emitting display having the thin film transistor.
Another aspect of the present invention includes a method of manufacturing a thin film transistor having improved electrical property and reliability, and a method of manufacturing an organic light emitting display having the thin film transistor.
An aspect of the present invention includes a method of manufacturing a thin film transistor, including: forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer including oxygen ions on the gate insulating layer, and including a channel region, a source region, and a drain region; forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively; and forming a passivation layer on the semiconductor layer by coating a material, wherein a carrier density of the semiconductor layer is 1E+17 to 1E+18/cm3.
An aspect of the present invention includes a method of manufacturing a thin film transistor, including: forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer including oxygen ions, on the gate insulating layer, and including a channel region, a source region, and a drain region; forming a passivation layer on the semiconductor layer by coating a material; forming a photoresist film on the passivation layer and then patterning the photoresist film to expose the source region and drain region of the semiconductor layer; and forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively, wherein a carrier density of the semiconductor layer is 1E+17 to 1E+18/cm3.
An aspect of the present invention includes a method of manufacturing an organic light emitting display having a thin film transistor, including: forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer including oxygen ions on the gate insulating layer, and including a channel region, a source region, and a drain region; forming a passivation layer on the semiconductor layer by coating a material; forming a photoresist film on the passivation layer and then patterning the photoresist film to expose the source region and drain region of the semiconductor layer; forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively; forming a planarization layer over the source electrode or the drain electrode and patterning the planarization layer to expose the source electrode or the drain electrode; forming a first electrode to contact the source electrode or the drain electrode exposed on the planarization layer; forming a pixel definition layer over the first electrode and exposing the first electrode in the light emitting region; and forming an organic thin film layer on the exposed first electrode and forming a second electrode on the pixel definition layer including the organic thin film layer, wherein a carrier density of the semiconductor layer is 1E+17 to 1E+18/cm3.
An aspect of the present invention includes a thin film transistor, including: a substrate; a compound semiconductor layer formed over the substrate, and including a channel region, a source region, and a drain region; a gate electrode formed to correspond to the channel region; and a passivation layer over the substrate and the thin film transistor to seal the compound semiconductor from intrusion of hydrogen.
An aspect of the present invention includes a method of manufacturing a thin film transistor, including: forming the thin film transistor on a substrate, the thin film transistor including a compound semiconductor layer comprising a channel region, a source region, and a drain region; and forming a passivation layer over the substrate and the thin film transistor to seal the compound semiconductor from intrusion of hydrogen.
Additional aspects and/or advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
These and/or other aspects and advantages of the invention will become apparent and more readily appreciated from the following description of the aspects, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a cross-sectional view explaining a thin film transistor according to a first aspect of the present invention.
FIG. 2 is a cross-sectional view explaining a thin film transistor according to a second aspect of the present invention.
FIGS. 3A to 3D are cross-sectional views explaining a method of manufacturing a thin film transistor according to the first aspect of the present invention.
FIGS. 4A to 4E are cross-sectional views explaining a method of manufacturing a thin film transistor according to the second aspect of the present invention.
FIGS. 5A and 5B are graphs explaining electrical property of a thin film transistor according to aspects of the present invention.
FIGS. 6A and 6B are a plan view and a cross-sectional view explaining a method of manufacturing an organic light emitting display having a thin film transistor according to aspects of the present invention.
FIG. 7 is a cross-sectional view explaining a method of manufacturing an organic light emitting display having a thin film transistor according to an aspect of the present invention.
 DETAILED DESCRIPTION OF THE EMBODIMENTS
Reference will now be made in detail to aspects of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The aspects are described below in order to explain the present invention by referring to the figures.
Hereinafter, certain aspects according to the present invention will be described with reference to the accompanying drawings. Here, when a first element is described as being coupled to a second element, the first element may be not only directly coupled to the second element but may also be indirectly coupled to the second element via a third element. Further, some of the elements that are not essential to the complete understanding of the invention are omitted for clarity.
FIG. 1 is a cross-sectional view explaining a thin film transistor according to a first aspect of the present invention, wherein the thin film transistor having a bottom gate structure is shown, as an example. As shown in FIG. 1, a gate electrode 11 is formed on a substrate 10 formed of insulating material. A gate insulating layer 12 is formed on an entire upper surface of the substrate 10 including the gate electrode 11. A semiconductor layer 13 is formed on the gate electrode 11, is electrically insulated from the gate electrode 11, and includes a channel region 13 a, a source region 13 b, and a drain region 13 c. The semiconductor layer 13 is formed of a compound semiconductor including oxygen ions, wherein the channel region 13 a is formed to be overlapped with the gate electrode 11. As the compound semiconductor including oxygen ions, zinc oxide (ZnO) or a compound semiconductor, etc., using zinc oxide (ZnO) doped with gallium (Ga), indium (In), tin (Sn), etc., as a main ingredient, may be used.
A source electrode 14 a and a drain electrode 14 b are formed on the semiconductor layer 13 to correspond to the source and drain regions 13 b and 13 c. Herein, a conductive layer 15 to reduce a contact resistance between the source and drain electrodes 14 a and 14 b, and the semiconductor layer 13 may be formed therebetween. Also, a passivation layer 16 is formed over the source and drain electrodes 14 a and 14 b and the semiconductor layer 13. In aspects of the present invention, the passivation layer 16 is formed of at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB). In aspects of the present invention, the passivation layer 16 entirely covers the semiconductor layer 13 and the source and drain electrodes 14 a and 14 b to seal them. Accordingly, the passivation layer 16 prevents or reduces infiltration of hydrogen into the semiconductor layer 13.
FIG. 2 is a cross-sectional view explaining a thin film transistor according to a second aspect of the present invention, wherein the thin film transistor having a bottom gate structure is shown, as an example. As shown in FIG. 2, a buffer layer 21 is formed on a substrate 20 formed of insulating material, and a gate electrode 22 is formed on the buffer layer 21. A semiconductor layer 24 is formed on the gate electrode 22, is electrically insulated from the gate electrode 22 by a gate insulating layer 23, and includes a channel region 24 a, a source region 24 b, and a drain region 24 c. The semiconductor layer 24 is formed of a compound semiconductor including oxygen ions, wherein the channel region 24 a is formed to be overlapped with the gate electrode 22. As the compound semiconductor including oxygen ions, zinc oxide (ZnO) or a compound semiconductor, etc., using zinc oxide (ZnO) doped with gallium (Ga), indium (In), tin (Sn), etc., as a main ingredient, may be used.
A passivation layer 25 is formed on the entire semiconductor layer 24, and is formed with contact holes to expose the source and drain regions 24 b and 24 c. The passivation layer 25 is formed of at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB). Source and drain electrodes 27 a and 27 b are formed on the passivation layer 25, and are contacted to the respective source and drain regions 24 b and 24 c through the contact holes. In aspects of the present invention, the passivation layer 25 entirely covers the semiconductor layer 24 and the source and drain electrodes 27 a and 27 b to seal them. Accordingly, the passivation layer 25 prevents or reduces infiltration of hydrogen into the semiconductor layer 24.
FIGS. 3A to 3D are cross-sectional views explaining a method of manufacturing a thin film transistor according to the first aspect of the present invention. Referring to FIG. 3A, a gate electrode 11 is formed on an insulating substrate 10, and then, a gate insulating layer 12 is formed on an entire upper surface of the substrate 10 including the gate electrode 11.
Referring to FIG. 3B, a semiconductor layer 13 is formed on the gate insulating layer 12, and over the gate electrode 11. The semiconductor layer 13 includes a channel region 13 a, a source region 13 b, and a drain region 13 c. The semiconductor layer 13 is a compound semiconductor including oxygen ions, wherein the semiconductor layer 13 may be formed of zinc oxide (ZnO) or a compound semiconductor, etc., using zinc oxide (ZnO) doped with gallium (Ga), indium (In), tin (Sn), etc., as a main ingredient.
Referring to FIG. 3C, metal is deposited and then patterned on an entire upper surface of the semiconductor layer 13 to form source and drain electrodes 14 a and 14 b that contact the respective source and drain regions 13 b and 13 c of the semiconductor layer 13. At this time, a conductive layer 15 to reduce a contact resistance between the source and drain electrodes 14 a and 14 b, and the semiconductor layer 13 may further be formed therebetween.
Referring to FIG. 3D, a passivation layer 16 is formed on an entire surface of the source and drain electrodes 14 a and 14 b, and that of the semiconductor layer 13 by performing a spin coating or a slit coating thereon of at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB). At this time, the organic material may be cured after being coated.
FIGS. 4A to 4E are cross-sectional views explaining a method of manufacturing a thin film transistor according to the second aspect of the present invention. Referring to FIG. 4A, a gate electrode 22 is formed on or over an insulating substrate 20, and then, a gate insulating layer 23 is formed on the gate electrode 22 and over the insulating substrate 20. At this time, a buffer layer 21 may be formed on the insulating substrate 20 before the gate electrode 22 is formed. The buffer layer 21 may be formed of an insulating material such as silicon oxide or silicon nitride.
Referring to FIG. 4B, a semiconductor layer 24 is formed on the gate insulating layer 23 that covers the gate electrode 22. The semiconductor layer 24 includes a channel region 24 a, a source region 24 b, and a drain region 24 c. The semiconductor layer 24 is a compound semiconductor including oxygen ions, and may be formed of zinc oxide (ZnO) or a compound semiconductor, etc., using zinc oxide (ZnO) doped with gallium (Ga), indium (In), tin (Sn), etc., as a main ingredient.
Referring to FIG. 4C, a passivation layer 25 is formed on an entire surface of the semiconductor layer 24 by performing a spin coating or a slit coating thereon of at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB).
Referring to FIG. 4D, a photoresist film 26 is formed and then patterned on the passivation layer 25. The passivation layer 25 in the exposed portion is etched through an etching process using the patterned photoresist film 26 as a mask. Accordingly, contact holes 25 a are formed to expose predetermined portions of the source region 24 b and the drain region 24 c. At this time, the photoresist film 26 can be patterned through exposure and development processes using an established mask.
Referring to FIG. 4E, source and drain electrodes 27 a and 27 b are formed to be contacted to the source and drain regions 24 b and 24 c of the semiconductor layer 24 through the contact holes 25 a formed on the passivation layer 25.
Although the first and second aspects are described as having a spin coating or a slit coating thereon of a material, by way of example, any physical coating method that does not cause a reaction between materials may also be applied. Also, any material that can be patterned through a photolithography process using the photoresist film 26 can be used in addition to the noted materials.
As shown in the first and second aspects of the present invention, the passivation layers 16 and 25 are formed by coating, for example, an organic material, such is not required. Thus, the passivation layers 16 and 25 may be formed by depositing inorganic materials, such as, silicon oxide SiO2, silicon nitride SiN, or the like, with plasma deposition equipment. However, as hydrogen (H) ions are diffused (infiltrated) into the semiconductor layer to be reacted during the deposition process, a hydrogen density and composition ratio of the semiconductor layer may be changed due to damage by the plasma.
In other words, if hydrogen (H) included in silan (SiH4) gas (used as a precursor in the deposition process) is diffused (infiltrated) into the semiconductor layer, a carrier density of the semiconductor layer may increase by ˜1E+20/cm3 due to the increase of the hydrogen density, and the composition ratio of positive ions and negative ions may be changed due to the damage by the plasma.
For example, when the semiconductor layer is formed of InGaZnO, the ratio (composition ratio) of positive ions and negative ions of InGaZnO may be represented as InxGayZn1−x−yOz. At this time, the semiconductor layer has an intrinsic property in case of x+y+z=1, while the semiconductor layer is conducting in the following case, wherein the composition ratio of positive ions and negative ions of ZnO may be changed as follows:
Zn1O0.99=1023×0.01˜1021/cm3
Zn1O0.999=1023×0.001˜1020/cm3
Zn1O0.9999=1023×0.0001˜1019/cm3
Therefore, if the composition of positive ions and negative ions is changed, a conductivity of a channel is changed due to a composition difference in the semiconductor layer as shown in the following mathematical equation 1.
z x + y + ( 1 - x - y ) ≥ 0.001 [ Mathematical ⁢ ⁢ Equation ⁢ ⁢ 1 ]
Similar damage due to the plasma also appears in the process to pattern the passivation layer through a plasma etching process.
On the other hand, when the passivation layers 16 and 25 are formed by coating the organic material through a physical method according to aspects of the present invention, because only the physical method is used, the reaction with hydrogen does not occur. Also, as the plasma is not used, it is possible to prevent or reduce the damage due to the plasma. Therefore, in aspects of the present invention, the carrier density of the semiconductor layer can be stably maintained in a range from about 1E+17 to 1E+18/cm3 and the conductivity of the channel is not changed even with a composition difference as shown in the following mathematical equation 2. The carrier density of the semiconductor layer between about 1E+19 and 1E+20 cm3 allows the semiconductor layer to have a conductivity similar to that of metal, while the carrier density of the semiconductor layer less than 1E+15 cm3 allows the semiconductor layer to have insulative properties.
z x + y + ( 1 - x - y ) ≤ 0.001 [ Mathematical ⁢ ⁢ Equation ⁢ ⁢ 2 ]
FIG. 5A shows a transfer curve measurement of an electrical property of a thin film transistor to which a plasma enhanced chemical vapor deposition (PECVD) process and a dry etching process have been applied, and having a passivation layer formed with silicon nitride film SiN. Referring to FIG. 5A, it can be seen that a carrier density of a semiconductor layer changes for being exposed to hydrogen and being damaged by plasma during processing using silan (SiH4), etc., to result in changes in a conductivity thereof.
On the other hand, FIG. 5B shows a transfer curve measurement of an electrical property of a thin film transistor to which a spin coating process and a photolithography process have been applied, and having a passivation layer formed with organic material. Referring to FIG. 5B, since a physical method, such as the spin coating process, is used that does not expose a semiconductor layer to hydrogen and does not generate a reaction between materials, and a photolithography process is used that does not cause plasma damage, it can be seen that a carrier density of the semiconductor layer is not changed, and thus a conductivity thereof is not changed.
Also, aspects of the present invention uses the photolithography process that uses a photoresist film to pattern the passivation layers 16 and 25, in order to expose the respective source electrodes 14 a and 27 a and drain electrodes 14 b and 27 b. Therefore, the photolithography process prevents or reduces damage to the passivation layers 16 and 25 arising from plasma etching even in subsequent processes, making it possible to effectively and uniformly maintain the conductivity of the channel.
The first and second aspects of the present invention describe a thin film transistor having a bottom gate structure. However, aspects of the present invention can also be applied to a thin film transistor having any structures using a compound semiconductor, such as a top gate structure, etc., as a semiconductor layer.
FIG. 6A is a plan view explaining an organic light emitting display having a thin film transistor according to an aspect of the present invention. FIG. 6A will be schematically explained focused on a display panel 200 displaying an image. Referring to FIG. 6A, a substrate 210 includes a pixel region 220, and a non-pixel region 230 that is peripheral to the pixel region 220. A portion of the substrate 210 corresponding to the pixel region 220 includes a plurality of organic light emitting elements 300 that are coupled between scan lines 224 and data lines 226 in a matrix arrangement. A portion of the substrate 210 corresponding to the non-pixel region 230 is formed with portions of the scan lines 224 and data lines 226 that extend from the scan lines 224 and data lines 226 of the pixel region 220, power supply lines (not shown) used in the operation of the organic light emitting elements 300, and a scan driver 234 and a data driver 236 to process signals supplied from an external device through a pad 228 and to supply the process signals to the scan lines 224 and the data lines 226.
FIG. 7 is a cross-sectional view explaining a method of manufacturing an organic light emitting display having a thin film transistor according to an aspect of the present invention. Referring to FIG. 7, an organic light emitting element 300 is formed of an anode electrode 317, a cathode electrode 320, and an organic thin film layer 319 formed between the anode electrode 317 and the cathode electrode 320. The organic thin film layer 319 may include a hole transport layer, an organic light emitting layer, and an electron transport layer. In aspects of the present invention, the organic thin film layer 319 may further include a hole injection layer and an electron injection layer. Also, a capacitor to maintaining signals and a thin film transistor to control an operation of the organic light emitting element 300 may further be included.
The organic light emitting element 300 including the thin film transistor will be described in more detail with reference to FIGS. 6A and 7. The thin film transistor has the structure as shown in FIG. 1 or in FIG. 2. Such a thin film transistor can be manufactured according to a manufacturing method of aspects of the present invention with reference to FIGS. 3A to 3D or FIGS. 4A to 4E. For this discussion, a thin film transistor having a structure as shown in FIG. 2 will be described by way of example.
Referring to FIGS. 6A, 7 and 4A, a buffer layer 21 is formed on a substrate 210, and a gate electrode 22 is formed on the buffer layer 21 in a pixel region 220. At this time, scan lines 224 coupled to the gate electrode 22 are formed in the pixel region 220. Scan lines 224 in the non-pixel region 230 are those that extend from the scan lines 224 in the pixel region 220, and a pad 228 to receive signals from the external device, may be formed in the non-pixel region 230. Thereafter, a gate insulating layer 23 is formed on the upper surface of the buffer layer 21 that includes the gate electrode 22.
Referring to FIGS. 7 and 4B, a semiconductor layer 24 (that includes a channel region 24 a, a source region 24 b, and a drain region 24 c) is formed on the gate insulating layer 23 and the gate electrode 22. The semiconductor layer 24 is a compound semiconductor including oxygen ions, and may be formed of zinc oxide (ZnO) or a compound semiconductor, etc., that uses zinc oxide doped with gallium (Ga), indium (In) and tin (Sn), etc., as a main ingredient.
Referring to FIGS. 7 and 4C, a passivation layer 25 is formed over the entire semiconductor layer 24 and the gate insulating layer 23 by coating at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB).
Referring to FIGS. 7 and 4D, a photoresist film 26 is formed on the passivation layer 25, and then, the photoresist film 26 is patterned through an exposure process and development processes using an established mask. The passivation layer 25 in an exposed portion is etched through an etching process using the patterned photoresist film 26 as a mask. Thereby, contact holes 25 a are formed to expose predetermined portions of a source region 24 b and a drain region 24 c.
Referring to FIGS. 7 and 4E, source and drain electrodes 27 a and 27 b are formed in order to contact the source and drain regions 24 b and 24 c of the semiconductor layer 24 through the contact holes 25 a formed on a passivation layer 25. At this time, data lines 226 coupled to the source and drain electrodes 27 a and 27 b are formed in a pixel region 220. Data lines 226 in the non pixel region 230 are those that extend from the data lines 226 in the pixel region 220, and a pad 228 to receive signals from the external device may be formed in the non-pixel region 230.
Referring to FIG. 7, a planarization layer 30 is formed on an entire upper surface of the passivation layer 25, and the source and drain electrodes 27 a and 27 b to form a planar surface. A via hole is formed in the planarization layer 30 in order to expose a predetermined portion of the source electrode 27 a or drain electrode 27 b. Thereafter, an anode electrode 317 is formed and coupled to the source electrode 27 a or the drain electrode 27 b through the via hole.
Thereafter, a pixel definition layer 318 is formed on the planarization layer 30 to expose some region (a light emitting region) of the anode electrode 317, and an organic thin film layer 319 is formed on the exposed region of anode electrode 317. A cathode electrode 320 is formed on the pixel definition film 318 and the organic thin film layer 319.
Referring to FIG. 6B, an encapsulation substrate 400 to encapsulate a pixel region 220 is disposed over the substrate 210 having the organic light emitting elements 300. The encapsulation substrate 400 is bonded to the substrate 210 by a sealing material 410 to complete a display panel 200.
As described above, aspects of the present invention form a passivation layer by coating organic material through a physical method, such as, a spin coating process where a reaction between materials does not occur, and patterns the passivation layer through a pattern process using a photoresist film. Accordingly, a change of a hydrogen density of a semiconductor layer, a change of composition ratio due to diffusion (infiltration) of hydrogen, and plasma damage are effectively prevented or reduced. Therefore, specific resistance in a channel region is controlled, conductivity in the channel region is stably maintained, making it possible to improve the electrical property of a thin film transistor, such as a non-generation of leakage current, etc.
In the figures, the dimensions of layers and regions may be exaggerated for clarity. It will also be understood that when a layer or element is referred to as being “on” or “over” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” or “below” another layer, it can be directly under, or one or more intervening layers may also be present.
Although a few aspects of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in the aspects without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

Claims (12)

What is claimed is:
1. A method of manufacturing a thin film transistor comprising:
forming a gate electrode on an insulating substrate;
forming a gate insulating layer on the gate electrode;
forming a semiconductor layer including oxygen ions on the gate insulating layer, the semiconductor layer including a channel region, a source region, and a drain region;
forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively; and
forming a passivation layer directly on the semiconductor layer and directly on the source and drain electrodes by coating a material, wherein the material is coated through a slit coating method,
wherein a carrier density of the semiconductor layer is 1E+17 to 1E+18/cm3.
2. The method of manufacturing the thin film transistor as claimed in claim 1, wherein the semiconductor layer is formed of zinc oxide (ZnO).
3. The method of manufacturing the thin film transistor as claimed in claim 1, wherein the semiconductor layer is formed of zinc oxide (ZnO) doped with at least one of gallium (Ga), indium (In), and tin (Sn).
4. The method of manufacturing the thin film transistor as claimed in claim 1, wherein the material is at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB).
5. A method of manufacturing a thin film transistor comprising:
forming a gate electrode on an insulating substrate;
forming a gate insulating layer on the gate electrode;
forming a semiconductor layer including oxygen ions on the gate insulating layer, the semiconductor layer including a channel region, a source region, and a drain region;
forming a passivation layer directly on the semiconductor layer by coating a material, wherein the material is coated through a slit coating method;
forming a photoresist film on the passivation layer and then patterning the photoresist film to expose the source region and drain region of the semiconductor layer; and
forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively,
wherein a carrier density of the semiconductor layer is 1 E+17 to 1E+18/cm3.
6. The method of manufacturing the thin film transistor as claimed in claim 5, wherein the semiconductor layer is formed of zinc oxide (ZnO).
7. The method of manufacturing the thin film transistor as claimed in claim 5, wherein the semiconductor layer is formed of zinc oxide (ZnO) doped with at least one of gallium (Ga), indium (In), and tin (Sn).
8. The method of manufacturing the thin film transistor as claimed in claim 5, wherein the material is at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB).
9. A method of manufacturing an organic light emitting display comprising:
forming a gate electrode on an insulating substrate;
forming a gate insulating layer on the gate electrode;
forming a semiconductor layer including oxygen ions on the gate insulating layer, the semiconductor layer including a channel region, a source region, and a drain region on the gate insulating layer;
forming a passivation layer directly on the semiconductor layer by coating a material, wherein the material is coated through a slit coating method;
forming a photoresist film on the passivation layer and then patterning the photoresist film to expose the source region and drain region of the semiconductor layer;
forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively;
forming a planarization layer on the passivation layer, the source electrode, and the drain electrode, and patterning the planarization layer to expose the source electrode or the drain electrode;
forming a first electrode on the planarization layer to contact the exposed source electrode or the drain electrode;
forming a pixel definition layer on the planarization layer and the first electrode, and exposing the first electrode in a light emitting region thereof; and
forming an organic thin film layer on the exposed first electrode and forming a second electrode on the pixel definition layer and the organic thin film layer,
wherein a carrier density of the semiconductor layer is 1E+17 to 1E+18/cm3.
10. The method of manufacturing the organic light emitting display as claimed in claim 9, wherein the semiconductor layer is formed of zinc oxide (ZnO).
11. The method of manufacturing the organic light emitting display as claimed in claim 9, wherein the semiconductor layer is formed of zinc oxide (ZnO) doped with at least one of gallium (Ga), indium (In), and tin (Sn).
12. The method of manufacturing the organic light emitting display as claimed in claim 9, wherein the material is at least one material selected from the group consisting of polyimide, polyacryl, spin on glass (SOG), photoresist film, and benzocyclobutane (BCB).
US12/266,797 2007-12-18 2008-11-07 Method of manufacturing thin film transistor and method of manufacturing organic light emitting display having thin film transistor Active 2031-01-13 US9240487B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070133508A KR100936874B1 (en) 2007-12-18 2007-12-18 Method of manufacturing a thin film transistor and A method of manufacturing an organic light emitting display having the thin film transistor
KR2007-133508 2007-12-18

Publications (2)

Publication Number Publication Date
US20090155940A1 US20090155940A1 (en) 2009-06-18
US9240487B2 true US9240487B2 (en) 2016-01-19

Family

ID=40753803

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/266,797 Active 2031-01-13 US9240487B2 (en) 2007-12-18 2008-11-07 Method of manufacturing thin film transistor and method of manufacturing organic light emitting display having thin film transistor

Country Status (2)

Country Link
US (1) US9240487B2 (en)
KR (1) KR100936874B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10797054B2 (en) 2009-12-28 2020-10-06 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1998373A3 (en) 2005-09-29 2012-10-31 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device having oxide semiconductor layer and manufacturing method thereof
KR101015338B1 (en) * 2008-03-13 2011-02-16 삼성모바일디스플레이주식회사 Method of manufacturing thin film transistor
KR102267235B1 (en) 2008-07-10 2021-06-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Light-emitting device and electronic device using the same
US8383470B2 (en) * 2008-12-25 2013-02-26 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor (TFT) having a protective layer and manufacturing method thereof
KR102526493B1 (en) 2009-07-31 2023-04-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and manufacturing method thereof
TWI582951B (en) * 2009-08-07 2017-05-11 半導體能源研究所股份有限公司 Semiconductor device and phone, watch, and display device comprising the same
KR101064442B1 (en) * 2009-08-21 2011-09-14 삼성모바일디스플레이주식회사 Organic Light Emitting Display device
WO2011027656A1 (en) 2009-09-04 2011-03-10 Semiconductor Energy Laboratory Co., Ltd. Transistor and display device
KR101746198B1 (en) 2009-09-04 2017-06-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device and electronic device
KR101751908B1 (en) 2009-10-21 2017-06-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Voltage regulator circuit
KR101789309B1 (en) 2009-10-21 2017-10-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Analog circuit and semiconductor device
CN102598248B (en) * 2009-10-21 2015-09-23 株式会社半导体能源研究所 Semiconductor device
SG10201406934WA (en) * 2009-10-29 2014-11-27 Semiconductor Energy Lab Semiconductor device
KR101788521B1 (en) 2009-10-30 2017-10-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
IN2012DN03080A (en) * 2009-10-30 2015-07-31 Semiconductor Energy Lab
KR101867003B1 (en) 2009-12-18 2018-06-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Liquid crystal display device and electronic device
US20130023086A1 (en) * 2009-12-21 2013-01-24 Sharp Kabushiki Kaisha Active matrix substrate, display panel provided with same, and method for manufacturing active matrix substrate
US20130092923A1 (en) * 2010-01-13 2013-04-18 Sharp Kabushiki Kaisha Active matrix substrate and method for manufacturing the same
KR102237655B1 (en) * 2010-01-15 2021-04-09 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for driving the same
CN106057162B (en) 2010-01-24 2019-01-22 株式会社半导体能源研究所 Display device
KR20120020073A (en) * 2010-08-27 2012-03-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 A method for designing a semiconductor
KR101563409B1 (en) * 2010-11-04 2015-10-26 샤프 가부시키가이샤 Semiconductor device, display device, and production method for semiconductor device and display device
KR101900525B1 (en) * 2011-03-18 2018-09-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Oxide semiconductor film, semiconductor device, and manufacturing method of semiconductor device
US9130044B2 (en) 2011-07-01 2015-09-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP6116149B2 (en) 2011-08-24 2017-04-19 株式会社半導体エネルギー研究所 Semiconductor device
JP6239227B2 (en) * 2011-11-30 2017-11-29 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method of semiconductor device
KR102044971B1 (en) * 2013-02-12 2019-11-15 삼성디스플레이 주식회사 Thin film transistor substrate and method of manufacturing the same
KR20140106042A (en) * 2013-02-25 2014-09-03 삼성디스플레이 주식회사 Thin film transistor substrate and method of manufacturing the same
JP6516978B2 (en) 2013-07-17 2019-05-22 株式会社半導体エネルギー研究所 Semiconductor device
KR102294507B1 (en) * 2013-09-06 2021-08-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
CN106252362B (en) * 2016-08-31 2019-07-12 深圳市华星光电技术有限公司 A kind of array substrate and preparation method thereof
KR102571610B1 (en) 2017-02-13 2023-08-30 삼성디스플레이 주식회사 Semiconductor device and method for fabricating the same

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4772927A (en) * 1985-10-23 1988-09-20 Hitachi, Ltd. Thin film FET doped with diffusion inhibitor
JP2002289859A (en) 2001-03-23 2002-10-04 Minolta Co Ltd Thin-film transistor
JP2004273614A (en) 2003-03-06 2004-09-30 Sharp Corp Semiconductor device and its fabricating process
KR20050046954A (en) 2003-11-15 2005-05-19 백홍구 A oeld(organic electro luminescence display) device of high packing density passivation for polymer substrate
KR20060007984A (en) 2004-07-23 2006-01-26 주식회사 하이닉스반도체 Passivation method for semiconductor device
KR20070035373A (en) 2005-09-27 2007-03-30 삼성에스디아이 주식회사 Transparent thin film transistor and manufacturing method thereof
US20070087487A1 (en) * 2005-10-14 2007-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070132365A1 (en) * 2005-12-09 2007-06-14 Tae-Wook Kang Flat panel display and method of fabricating the same
US20070241327A1 (en) * 2006-04-18 2007-10-18 Samsung Electronics Co. Ltd. Fabrication methods of a ZnO thin film structure and a ZnO thin film transistor, and a ZnO thin film structure and a ZnO thin film transistor
US20070267633A1 (en) * 2006-05-17 2007-11-22 Lg Philips Lcd Co., Ltd. Flat panel display device and method for fabricating same
US20070275512A1 (en) * 2006-05-25 2007-11-29 Lg.Philips Lcd Co., Ltd. Method for manufacturing thin film transistor substrate using maskless exposing device
US20070272922A1 (en) * 2006-04-11 2007-11-29 Samsung Electronics Co. Ltd. ZnO thin film transistor and method of forming the same
US20070297039A1 (en) * 2006-06-22 2007-12-27 Samsung Electronics Co., Ltd Electrophoretic display and manufacturing method thereof
US20080023703A1 (en) * 2006-07-31 2008-01-31 Randy Hoffman System and method for manufacturing a thin-film device
US20080158108A1 (en) * 2006-12-27 2008-07-03 Lg Philips Lcd Co., Ltd. Organic light emitting device and method for manufacturing the same
US20080296568A1 (en) * 2007-05-29 2008-12-04 Samsung Electronics Co., Ltd Thin film transistors and methods of manufacturing the same
US20090174012A1 (en) * 2006-01-30 2009-07-09 Canon Kabushiki Kaisha Field Effect Transistor
US7829444B2 (en) * 2004-11-10 2010-11-09 Canon Kabushiki Kaisha Field effect transistor manufacturing method

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4772927A (en) * 1985-10-23 1988-09-20 Hitachi, Ltd. Thin film FET doped with diffusion inhibitor
JP2002289859A (en) 2001-03-23 2002-10-04 Minolta Co Ltd Thin-film transistor
JP2004273614A (en) 2003-03-06 2004-09-30 Sharp Corp Semiconductor device and its fabricating process
KR20050046954A (en) 2003-11-15 2005-05-19 백홍구 A oeld(organic electro luminescence display) device of high packing density passivation for polymer substrate
KR20060007984A (en) 2004-07-23 2006-01-26 주식회사 하이닉스반도체 Passivation method for semiconductor device
US7829444B2 (en) * 2004-11-10 2010-11-09 Canon Kabushiki Kaisha Field effect transistor manufacturing method
KR20070035373A (en) 2005-09-27 2007-03-30 삼성에스디아이 주식회사 Transparent thin film transistor and manufacturing method thereof
US20070087487A1 (en) * 2005-10-14 2007-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070132365A1 (en) * 2005-12-09 2007-06-14 Tae-Wook Kang Flat panel display and method of fabricating the same
US20090174012A1 (en) * 2006-01-30 2009-07-09 Canon Kabushiki Kaisha Field Effect Transistor
US20070272922A1 (en) * 2006-04-11 2007-11-29 Samsung Electronics Co. Ltd. ZnO thin film transistor and method of forming the same
US20070241327A1 (en) * 2006-04-18 2007-10-18 Samsung Electronics Co. Ltd. Fabrication methods of a ZnO thin film structure and a ZnO thin film transistor, and a ZnO thin film structure and a ZnO thin film transistor
US20070267633A1 (en) * 2006-05-17 2007-11-22 Lg Philips Lcd Co., Ltd. Flat panel display device and method for fabricating same
US20070275512A1 (en) * 2006-05-25 2007-11-29 Lg.Philips Lcd Co., Ltd. Method for manufacturing thin film transistor substrate using maskless exposing device
US20070297039A1 (en) * 2006-06-22 2007-12-27 Samsung Electronics Co., Ltd Electrophoretic display and manufacturing method thereof
US20080023703A1 (en) * 2006-07-31 2008-01-31 Randy Hoffman System and method for manufacturing a thin-film device
US20080158108A1 (en) * 2006-12-27 2008-07-03 Lg Philips Lcd Co., Ltd. Organic light emitting device and method for manufacturing the same
US20080296568A1 (en) * 2007-05-29 2008-12-04 Samsung Electronics Co., Ltd Thin film transistors and methods of manufacturing the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Office Action issued Oct. 7, 2009, in corresponding Korean Application No. 10-2007-0133508.
Seung Yeop Myong and Koeng Su Lim, titled "Role of Intentionally Incorporated Hydrogen I Wide-Band-Gap ZnO Thin Film Prepared by Photo-MOCVD Technique", cP772, Physics of Semiconductors; 27th International Conference on the Physics of Semiconductors.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10797054B2 (en) 2009-12-28 2020-10-06 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device
US11424246B2 (en) 2009-12-28 2022-08-23 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device

Also Published As

Publication number Publication date
KR100936874B1 (en) 2010-01-14
KR20090065951A (en) 2009-06-23
US20090155940A1 (en) 2009-06-18

Similar Documents

Publication Publication Date Title
US9240487B2 (en) Method of manufacturing thin film transistor and method of manufacturing organic light emitting display having thin film transistor
US11984451B2 (en) Display device and method for making the same
US11177293B2 (en) Array substrate and fabricating method thereof, and display device
US8178884B2 (en) Thin film transistor including compound semiconductor oxide, method of manufacturing the same and flat panel display device having the same
US10153304B2 (en) Thin film transistors, arrays substrates, and manufacturing methods
US8278665B2 (en) Organic light emitting diode display
US8324629B2 (en) Organic light emitting display device and method of manufacturing the same
KR100936871B1 (en) Organic light emitting display device and method of manufacturing the same
US20100176388A1 (en) Thin film transistor, method of manufacturing the same and flat panel display device having the same
KR20110037220A (en) Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device having the thin film transistor
CN110729313A (en) Display panel, display panel preparation method and display device
US12080731B2 (en) Light detection substrate, manufacturing method thereof and light detection apparatus
KR20090105561A (en) Semiconductor device and flat panel display device having the same
KR101600475B1 (en) Thin film transistor and active matrix organic light emitting diode assembly and method for manufacturing the same
US8598781B2 (en) Organic light emitting display (OLED) and its method of fabrication
CN210723028U (en) Display panel and display device
US10957713B2 (en) LTPS TFT substrate and manufacturing method thereof
CN115411057B (en) Array substrate, preparation method thereof and display device
CN114792694A (en) Thin film transistor array substrate, preparation method thereof and display panel
JP2022146789A (en) thin film transistor substrate
US10361226B2 (en) Array substrate, manufacturing method for the same and display panel
KR20090106051A (en) Thin film transistor, method of manufacturing the thin film transistor and flat panel display device having the thin film transistor
US11088229B1 (en) Pixel driving circuit and manufacturing method thereof
CN116581130B (en) Display panel and preparation method thereof
CN116799016B (en) Array substrate, manufacturing method thereof and display panel

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG MOBILE DISPLAY CO., LTD., KOREA, REPUBLIC

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, HUN-JUNG;JEONG, JAE-KYEONG;SHIN, HYUN-SOO;AND OTHERS;REEL/FRAME:021867/0269

Effective date: 20081030

AS Assignment

Owner name: SAMSUNG DISPLAY CO., LTD., KOREA, REPUBLIC OF

Free format text: MERGER;ASSIGNOR:SAMSUNG MOBILE DISPLAY CO., LTD.;REEL/FRAME:028868/0413

Effective date: 20120702

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8