JP2002289859A - Thin-film transistor - Google Patents

Thin-film transistor

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Publication number
JP2002289859A
JP2002289859A JP2001086175A JP2001086175A JP2002289859A JP 2002289859 A JP2002289859 A JP 2002289859A JP 2001086175 A JP2001086175 A JP 2001086175A JP 2001086175 A JP2001086175 A JP 2001086175A JP 2002289859 A JP2002289859 A JP 2002289859A
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Prior art keywords
film
gate insulating
semiconductor active
insulating film
active layer
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JP2001086175A
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Japanese (ja)
Inventor
Tomoji Kawai
Takeshi Kitamura
Satoshi Masuda
Shigehiro Miyatake
Yoshihiro Okumura
Hitoshi Tabata
健 北村
敏 増田
佳弘 奥村
茂博 宮武
知二 川合
仁 田畑
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Minolta Co Ltd
ミノルタ株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor, having an ZnO film as a semiconductor active layer, where the leakage current of a gate insulating film is suppressed, to provide proper transistor characteristics. SOLUTION: A thin-film transistor T1 is formed on an insulating substrate 1. On the substrate 1, a gate electrode 2, a gate insulating film 21, an intermediate layer 32, and a semiconductor active layer 4 of ZnO are formed sequentially; a source electrode 5 and a drain electrode 6 are formed on the semiconductor active layer 4; and the intermediate layer 32, comprising silicon nitride, is provided so as to prevent movable ions (Zn ion) from infiltrating the gate insulating film 32 from the semiconductor active layer (ZnO film) 4.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、酸化亜鉛(Zn The present invention relates to a zinc oxide (Zn
O)を半導体活性層とする薄膜トランジスタに関する。 The O) concerning a thin film transistor and the semiconductor active layer.

【0002】 [0002]

【従来の技術】従来の薄膜トランジスタ(TFT)の一例の概略断面図を図8に示す。 BACKGROUND OF THE INVENTION The schematic sectional view of an example of a conventional thin film transistor (TFT) is shown in FIG.

【0003】図8の薄膜トランジスタは逆スタガ構造(ボトムゲート構造)のものであり、基板1上に形成されている。 [0003] The thin film transistor of FIG. 8 is of inverted staggered structure (bottom gate structure) is formed on the substrate 1. さらに詳しく言うと、基板1上には、ゲート電極2、ゲート絶縁膜3、半導体活性層(半導体層)4 More particularly, on the substrate 1, a gate electrode 2, the gate insulating film 3, the semiconductor active layer (semiconductor layer) 4
が形成されている。 There has been formed. 半導体活性層4上にはさらにソース電極5とドレイン電極6が形成されている。 On the semiconductor active layer 4 is further formed a source electrode 5 and drain electrode 6.

【0004】ゲート電極、ソース電極、ドレイン電極としては、Al等の金属薄膜や、ITO等の透明導電膜が用いられている。 [0004] The gate electrode, the source electrode, the drain electrode, and a metal thin film of Al or the like, a transparent conductive film of ITO or the like is used.

【0005】ゲート絶縁膜としては、絶縁性の極めて高いSiO 2膜が多く用いられている。 [0005] As the gate insulating film is often used a very high SiO 2 film insulating.

【0006】半導体活性層としては、アモルファスシリコン膜や、ポリシリコン膜が多用されているが、酸化亜鉛(ZnO)膜を用いることも提案されている。 [0006] As the semiconductor active layer, or amorphous silicon film, but a polysilicon film is frequently used, it has also been proposed to use a zinc oxide (ZnO) film.

【0007】アモルファスシリコン膜やポリシリコン膜を半導体活性層とするTFTにおいては、半導体活性層に光が入射すると、光によって生成される光生成キャリアの影響を受けて、正常な動作ができなくなることがある。 [0007] In the TFT of an amorphous silicon film or a polysilicon film and a semiconductor active layer, the light in the semiconductor active layer enters, under the influence of photogenerated carriers generated by light made it impossible normal operation there is.

【0008】これに対してZnO膜を半導体活性層とするTFTにおいては、半導体活性層に光が入射しても、 [0008] In the TFT of the ZnO film and the semiconductor active layer with respect to this, even if the light is incident on the semiconductor active layer,
ZnO膜が可視光に対して透明であるため、半導体活性層は光の影響をほとんど受けない。 Because ZnO film is transparent to visible light, the semiconductor active layer is hardly affected by the light. そのため、ZnO膜を半導体活性層とするTFTは、光が入射しても正常な動作ができなくなるという不具合はほとんど生じない。 Therefore, TFT to the ZnO film and the semiconductor active layer, a problem that light can not be normal operation incident hardly occurs.

【0009】 [0009]

【発明が解決しようとする課題】しかしながら、本発明者らの研究によると、ZnO膜を半導体活性層とする薄膜トランジスタにおいてゲート絶縁膜がSiO 2膜である場合、何らかの原因によって、SiO 2膜(ゲート絶縁膜)の絶縁性能が低下してしまうことがあることが判明した。 However [0007], according to the study of the present inventors, if the gate insulating film in a thin film transistor for the ZnO film and the semiconductor active layer is a SiO 2 film, for some reason, SiO 2 film (gate insulation performance of the insulating film) has been found that may be lowered. ゲート絶縁膜の絶縁性能が低下すると、ゲート絶縁膜におけるリーク電流が増大し、トランジスタ特性が得られないという不具合が生じる。 If the insulation performance of the gate insulating film is lowered, the leakage current is increased in the gate insulating film, a problem that the transistor characteristics can not be obtained.

【0010】そこで本発明は、ZnO膜を半導体活性層とする薄膜トランジスタであって、ゲート絶縁膜のリーク電流を抑制し、良好なトランジスタ特性が得られる薄膜トランジスタを提供することを課題とする。 [0010] The present invention is a thin film transistor of the ZnO film and the semiconductor active layer, to suppress the leakage current of the gate insulating film, and to provide a good TFT transistor characteristics can be obtained.

【0011】 [0011]

【課題を解決するための手段】[1] 前記課題を解決するために本発明は、半導体活性層、ゲート電極、ソース電極、ドレイン電極及び前記ゲート電極と前記半導体活性層の間に配置されたゲート絶縁膜を有し、前記半導体活性層が酸化亜鉛(ZnO)からなり、前記ゲート絶縁膜と前記半導体活性層との間に前記ゲート絶縁膜の材料とは異なる組成の材料からなる中間層が設けられていることを特徴とする薄膜トランジスタを提供する。 Means for Solving the Problems] [1] The present invention in order to solve the above problems, a semiconductor active layer, a gate electrode, disposed between the source electrode, the drain electrode and the gate electrode and the semiconductor active layer a gate insulating film, the result semiconductor active layer is of zinc oxide (ZnO), an intermediate layer made of a material having a composition different from the material of the gate insulating film between said gate insulating film semiconductor active layer it is provided to provide a thin film transistor according to claim. [1−1] 本発明の薄膜トランジスタ(TFT:Thin [1-1] The thin film transistor of the present invention (TFT: Thin
Film Transistor)は、半導体活性層、ゲート電極、ソース電極、ドレイン電極及びゲート絶縁膜を有している。 Film Transistor) has a semiconductor active layer, a gate electrode, a source electrode, a drain electrode and a gate insulating film.

【0012】ゲート絶縁膜は、ゲート電極と半導体活性層とを電気的に絶縁するなどのために、ゲート電極と半導体活性層の間に配置されている。 [0012] The gate insulating film, a gate electrode and a semiconductor active layer, such as for electrically insulating, is disposed between the gate electrode and the semiconductor active layer. つまり、ゲート電極はゲート絶縁膜を介して半導体活性層に臨んでいる。 That is, the gate electrode faces the semiconductor active layer via a gate insulating film.

【0013】ゲート絶縁膜は、電気的に高抵抗であり、 [0013] The gate insulating film is an electrically high resistance,
非常に高い絶縁性を有している。 It has a very high insulation property. ゲート絶縁膜の抵抗率は、例えば、10 7 Ωcm以上、より好ましくは10 9 The resistivity of the gate insulating film, for example, 10 7 [Omega] cm or higher, more preferably 10 9
Ωcm以上、さらに好ましくは10 12 Ωcm以上とすればよい。 [Omega] cm or higher, further preferably lower 10 12 [Omega] cm or more. ゲート絶縁膜の抵抗率にはゲート絶縁膜を設ける目的(ゲート電極と半導体活性層の間の絶縁)からして特段の上限はないが、成膜の容易性、材料の入手容易性、価格等を考慮して、抵抗率は10 16 Ωcm以下とすればよい。 Although no particular upper limit to the purpose of providing the gate insulating film (insulation between the gate electrode and the semiconductor active layer) in the resistivity of the gate insulating film, ease of deposition, easy availability of material, price, etc. taking into account the resistivity may be set to 10 16 [Omega] cm or less.

【0014】ソース電極は半導体活性層に臨んでいる。 [0014] The source electrode faces the semiconductor active layer.
ソース電極は半導体活性層に直接接する位置に設けてもよく、ソース電極と半導体活性層の間には別の層(例えばオーミックコンタクト層)を設けてもよい。 The source electrode may be provided at a position in direct contact with the semiconductor active layer may be provided another layer (e.g., ohmic contact layer) is formed between the source electrode and the semiconductor active layer.

【0015】ドレイン電極も半導体活性層に臨んでいる。 The drain electrode is also faces the semiconductor active layer. ドレイン電極は半導体活性層に直接接する位置に設けてもよく、ドレイン電極と半導体活性層の間には別の層(例えばオーミックコンタクト層)を設けてもよい。 The drain electrode may be provided at a position in direct contact with the semiconductor active layer may be provided another layer (e.g., ohmic contact layer) is formed between the drain electrode and the semiconductor active layer.

【0016】半導体活性層、ゲート電極、ソース電極、 The semiconductor active layer, a gate electrode, a source electrode,
ドレイン電極及びゲート絶縁膜は、例えば、逆スタガ構造(ボトムゲート構造)又は正スタガ構造(トップゲート構造)となるように配置すればよい。 Drain electrode and the gate insulating film, for example, may be arranged such that the reverse stagger structure (bottom gate structure) or staggered structure (top gate structure).

【0017】本発明の薄膜トランジスタにおいては、半導体活性層は酸化亜鉛(ZnO)からなる。 [0017] In the thin film transistor of the present invention, the semiconductor active layer comprises zinc oxide (ZnO).

【0018】また、本発明の薄膜トランジスタにおいては、半導体活性層(ZnO膜)とゲート絶縁膜の間には、ゲート絶縁膜材料とは異なる組成の材料からなる中間層が配置されている。 [0018] In the thin film transistor of the present invention, between the semiconductor active layer (ZnO film) and the gate insulating film, and is an intermediate layer is arranged made of a material having a composition different from the gate insulating film material. つまり、半導体活性層(ZnO That is, the semiconductor active layer (ZnO
膜)、中間層、ゲート絶縁膜、ゲート電極の順にこれらは配置されている。 Film), an intermediate layer, a gate insulating film, they are in the order of the gate electrode is formed. なお、これらの間には別の層を設けてもよい。 It is also possible to provide another layer between these.

【0019】半導体活性層とゲート絶縁膜との間に配置された中間層は、ゲート絶縁膜の絶縁性が低下するのを防止するために設けられている。 The semiconductor active layer and the intermediate layer disposed between the gate insulating film includes an insulating gate insulating film is provided in order to prevent deterioration.

【0020】先に述べたように、SiO 2膜等のゲート絶縁膜を半導体活性層としてのZnO膜に直接接する位置に配置すると、ゲート絶縁膜の絶縁性が低下して、薄膜トランジスタが正常に動作しなくなる恐れがある。 [0020] As previously mentioned, placing the gate insulating film such as SiO 2 film is directly in contact located ZnO film as the semiconductor active layer, an insulating gate insulating film is reduced, the thin film transistor is operating normally there is a possibility that no longer.

【0021】このようにゲート絶縁膜の絶縁性能が低下してしまう確かな原因は不明ではあるが、ZnO膜(半導体活性層)からゲート絶縁膜への可動イオン(特にZ [0021] While certain causes of insulation performance is lowered in this way the gate insulating film is is not known, the mobile ions (especially Z from ZnO film (semiconductor active layer) to the gate insulating film
nイオン)の侵入によって、ゲート絶縁膜の絶縁性能が低下するものと推測される。 The n ion) from entering the insulating performance of the gate insulating film is assumed to decrease. また、薄膜トランジスタを作製するときにおいてゲート絶縁膜を形成した後に、Z Further, after forming the gate insulating film at the time of making a thin film transistor, Z
nO膜(半導体活性層)を形成する場合には、ZnO膜の成膜時における原子や粒子などの衝突によってゲート絶縁膜が受けるダメージが、ゲート絶縁膜の絶縁性能の低下の一因であるとも推測される。 When forming nO film (semiconductor active layer), it damages the gate insulating film is subjected by the collision, such as atoms or particles during formation of the ZnO film is also to contribute to the reduction in the insulation performance of the gate insulating film It is estimated.

【0022】本発明者らは、上記のようにZnO膜(半導体活性層)とゲート絶縁膜との間に、ゲート絶縁膜とは異なる組成からなる材料の中間層を配置することで、 [0022] The present inventors have found that during the above and ZnO film (semiconductor active layer) and the gate insulating film, by disposing the intermediate layer of material of different composition than the gate insulating film,
可動イオンのゲート絶縁膜への侵入や、ZnO膜の成膜に伴うゲート絶縁膜のダメージに起因すると考えられるゲート絶縁膜の絶縁性能の低下を抑制できることを見いだした。 Intrusion and to the gate insulating film of the movable ions, found that the decrease in the insulation performance of the possible gate insulating film to be due to the damage of the gate insulating film due to the formation of the ZnO film can be suppressed.

【0023】本発明の薄膜トランジスタにおいては、上記のようにゲート絶縁膜と半導体活性層(ZnO膜)との間に、ゲート絶縁膜とは異なる組成の材料からなる中間層が配置されているため、半導体活性層(ZnO膜) [0023] In the thin film transistor of the present invention, between the gate insulating film and the semiconductor active layer as described above (ZnO film), because it is an intermediate layer is arranged made of a material having a composition different from the gate insulating film, semiconductor active layer (ZnO film)
からゲート絶縁膜への可動イオン(特にZnイオン)が侵入してゲート絶縁膜へ拡散したり、ゲート絶縁膜上に別の膜(例えば半導体活性層としてのZnO膜)を形成するときの原子や粒子などの衝突によってゲート絶縁膜がダメージを受けたりすることが原因と考えられるゲート絶縁膜の絶縁性能の低下を抑制できる。 Or diffused into the mobile ions (especially Zn ions) from entering the gate insulating film of the gate insulating film from Ya atom for forming the (ZnO film as for example, a semiconductor active layer) another film on the gate insulating film the reduction in the insulation performance of the gate insulating film is considered to cause the gate insulating film or damaged by collision of such particles can be suppressed. これにより、 As a result,
本発明の薄膜トランジスタにおいては、ゲート絶縁膜は高い絶縁性を安定して維持することができる。 In the thin film transistor of the present invention, the gate insulating film can be stably maintaining high insulating properties. したがって、ゲート絶縁膜におけるリーク電流を抑制でき、本発明の薄膜トランジスタにおいては安定したトランジスタ特性が得られる。 Therefore, it is possible to suppress the leakage current in the gate insulating film, in the thin film transistor of the present invention stable transistor characteristics can be obtained.

【0024】また、半導体活性層としてのZnO膜は可視光に対して透明であるので、半導体活性層に可視光が入射しても、本発明の薄膜トランジスタはトランジスタ特性の変化等の影響を受けにくい。 Further, since the ZnO film as the semiconductor active layer is transparent to visible light, even if visible light is incident on the semiconductor active layer, a thin film transistor of the present invention is less susceptible to changes in transistor characteristics . したがって、本発明の薄膜トランジスタには遮光層を設ける必要がなく、それだけ工程少なく作製することができる。 Accordingly, the thin film transistor of the present invention there is no need to provide a light shielding layer can be manufactured correspondingly step less.

【0025】また、半導体活性層が可視光に対して透明であるので、本発明の薄膜トランジスタを例えば液晶表示素子等の表示素子におけるスイッチング素子として利用する場合には、その開口率を高めることができる。 Further, since the semiconductor active layer is transparent to visible light, in the case of using a thin film transistor of the present invention for example as switching elements in display devices such as a liquid crystal display device can increase the aperture ratio . また、本発明の薄膜トランジスタを例えば表示素子におけるスイッチング素子として利用する場合には、その開口率を高め、表示素子から射出される光の光量を増大させることができる。 In the case of using a thin film transistor of the present invention as a switching element, for example in display devices, the aperture ratio increased, thereby increasing the amount of light emitted from the display element. 本発明の薄膜トランジスタを例えば光電変換素子におけるスイッチング素子として利用する場合には、その開口率を高め、素子への入射光量を増大させることができる。 When using a thin film transistor of the present invention as a switching element for example in the photoelectric conversion element, the aperture ratio increased, it is possible to increase the quantity of light incident on the element. [1−2] 本発明の薄膜トランジスタについて以下さらに説明する。 Further described below thin film transistor [1-2] present invention. (a)ゲート絶縁膜 ゲート絶縁膜は、絶縁性(例えば少なくとも10 7 Ωc (A) a gate insulating film The gate insulating film includes an insulating (e.g., at least 10 7 .omega.c
m以上の抵抗率)が得られるのであれば、どのような材料からなるものでもよい。 If the m or more resistivity) is obtained, it may be made of any material.

【0026】好適なゲート絶縁膜としては、例えば、酸化シリコンを主成分とする膜(酸シリコンのみからなる膜を含む。以下、単に酸化シリコン膜という)を挙げることができる。 [0026] Suitable gate insulating film, for example, film mainly containing silicon oxide (including a film made of only silicon oxy. Hereinafter, simply referred to as a silicon oxide film) can be exemplified. 酸化シリコン膜は、絶縁性を損なわない範囲で不純物を含んでいてもよい。 Silicon oxide film may contain impurities within a range not to impair the insulating properties. 酸化シリコン膜は、 Silicon film is oxidized,
例えば、SiO 2からなる膜、或いは、SiO 2を主成分とする膜とすればよい。 For example, a film made of SiO 2, or may be a film composed mainly of SiO 2. なお、十分な絶縁性が得られるのであれば、成膜条件などによって化学量論比がSi Incidentally, as long as sufficient insulation is obtained, the stoichiometric ratio, such as by deposition condition Si
2から多少ずれていてもよく、本明細書において酸化シリコンという場合には、このように化学量論比がSi May be slightly deviated from O 2, in the case of silicon oxide used herein, thus stoichiometry Si
2から多少ずれたものも含む。 O including 2 that somewhat deviated from.

【0027】酸化シリコン膜は、電気的に極めて高抵抗な膜であるが、絶縁破壊の原因となるピンホールを含んでいることがある。 The silicon oxide film is electrically is a very high-resistance film, it may comprise a pinhole causing dielectric breakdown. また、ナトリウム(Na)、銅(C Further, sodium (Na), copper (C
u)、亜鉛(Zn)等の可動イオンが酸化シリコン膜に侵入して拡散すると、酸化シリコン膜の絶縁性能は著しく低下してしまう。 u), the zinc (Zn) is movable ions such as diffuse invade the silicon oxide film, the insulating performance of the silicon oxide film is significantly lowered. しかし、本発明の薄膜トランジスタにおいては、ゲート絶縁膜として酸化シリコン膜を採用しても、前述のように、半導体活性層(ZnO膜)と酸化シリコン膜(ゲート絶縁膜)との間に、ゲート絶縁膜と異なる組成の材料からなる中間層が設けられているため、酸化シリコン膜の絶縁性能の低下を抑制できる。 However, in the thin film transistor of the present invention, be employed a silicon oxide film as a gate insulating film, as described above, between the semiconductor active layer (ZnO film) and a silicon oxide film (gate insulating film), a gate insulating since the intermediate layer of a material film and the different compositions are provided, it is possible to suppress the deterioration of the insulating performance of the silicon oxide film. また、酸化シリコン膜(ゲート絶縁膜)を形成した後にZ Further, Z after forming the silicon oxide film (gate insulating film)
nO膜(半導体活性層)を形成する場合には、そのZn When forming a nO film (semiconductor active layer), the Zn
O膜を成膜するときの原子や粒子などの衝突によるダメージから、酸化シリコン膜を中間層によって保護することができ、酸化シリコン膜の絶縁性能の低下を抑制することができる。 The O film from damage due to collisions, such atoms or particles at the time of film formation, it is possible to protect the silicon oxide film by the intermediate layer, it is possible to suppress the reduction in the insulation performance of a silicon oxide film.

【0028】ゲート絶縁膜は、代表的には、SiO 2を主成分とする膜(SiO 2のみからなる膜を含む。以降、単にSiO 2膜という)とすればよい。 [0028] The gate insulating film is typically film composed mainly of SiO 2 (including the film made of only SiO 2. Hereinafter, simply referred to as SiO 2 film) may be set to.

【0029】SiO 2膜は、例えば、平行平板型RFプラズマCVD法によって、TEOS[Tetraethoxysilan The SiO 2 film, for example, a parallel plate type RF plasma CVD method, TEOS [Tetraethoxysilan
e:Si(OC 2 H 5 ) 4 ]とO 2を原料として形成することができる。 e: Si a (OC 2 H 5) 4] and O 2 can be formed as a raw material. この方法によって得られるSiO 2膜は、抵抗率が10 14 Ωcm以上と極めて高い絶縁性を示し、降伏電界も5MV/cm以上と高い。 SiO 2 film obtained by this method, the resistivity showed an extremely high insulating property and 10 14 [Omega] cm or more, the breakdown electric field 5 MV / cm or more and high.

【0030】SiO 2膜は、ECRプラズマCVD法によって形成してもよい。 The SiO 2 film may be formed by ECR plasma CVD method. この方法によって得られるSi Si obtained by this method
2膜は、抵抗率が10 15 Ωcm以上と極めて高い絶縁性を示し、降伏電界も10MV/cm以上と高い。 O 2 film, the resistivity showed an extremely high insulating property and 10 15 [Omega] cm or more, the breakdown electric field 10 MV / cm or more and high. また、この方法によるSiO 2膜の成膜は、ECRの高い反応性を利用しているため、基板加熱なしで高耐圧の絶縁膜が得られる。 Further, the deposition of the SiO 2 film by this method, because it uses the high reactivity of the ECR, the insulating film of the high breakdown voltage can be obtained without heating the substrate. 基板加熱の必要がないので、使用できる基板材料の条件が緩和され、基板材料の選択範囲が広がる。 Because no need for substrate heating, the relaxed condition of the substrate material that can be used, the selection of the substrate material is increased. (b)中間層 中間層は、ゲート絶縁膜とは異なる組成の材料で形成されている。 (B) Intermediate layer The intermediate layer is formed of a material having a composition different from the gate insulating film. 中間層は、半導体活性層(ZnO膜)からゲート絶縁膜への可動イオンの侵入を防止できるもの、又は(及び)、ゲート絶縁膜を形成した後にゲート絶縁膜とは異なる膜(例えば半導体活性層としてのZnO膜) The intermediate layer, which semiconductor active layer from (ZnO film) can be prevented from entering the mobile ions into the gate insulating film, or (and), different membrane (e.g. semiconductor active layer and the gate insulating film after forming the gate insulating film ZnO film as)
を形成するときのゲート絶縁膜のダメージを防止できるものであることが好ましい。 It is preferable that prevents damage to the gate insulating film when forming the. このような観点からは、中間層はゲート絶縁膜より硬質であること、又は(及び)、中間層はゲート絶縁膜よりも緻密な膜であることが好ましい。 From this point of view, it intermediate layer is harder than the gate insulating film, or (and), it is preferred that the intermediate layer is a dense film than the gate insulating film. 中間層は、必ずしも絶縁性である必要はないが、例えば絶縁性を有するものとすればよい。 Intermediate layer is not necessarily be insulative, for example may be to have an insulating property.

【0031】好適な中間層としては、例えば、窒化シリコンを主成分とする膜(窒化シリコンのみからなる膜も含む。以下、単に窒化シリコン(SiN)膜という) [0031] Suitable interlayers include, for example, film mainly containing silicon nitride (film made of only the silicon nitride including. Hereinafter simply silicon nitride (SiN) as film)
や、酸窒化シリコンを主成分とする膜(酸窒化シリコンのみからなる膜も含む。以下、単に酸窒化シリコン膜という)を挙げることができる。 And, a film composed mainly of silicon oxynitride (film made of only silicon oxynitride including. Hereinafter, simply referred to as silicon oxynitride film) and the like. 中間層としての窒化シリコン膜や酸窒化シリコン膜は、その所期の目的を達成できる範囲で、不純物を含んでいてもよい。 Silicon silicon nitride film or oxynitride film as an intermediate layer is within the range that can achieve its intended purpose, may contain impurities. 窒化シリコン(SiN)膜は、例えば、アモルファスSiN又はSi Silicon nitride (SiN) film, for example, amorphous SiN or Si
34からなる膜、或いは、アモルファスSiN又はS Film made of 3 N 4, or amorphous SiN, or S
34を主成分とする膜とすればよい。 The i 3 N 4 may be the film mainly. なお、成膜条件等によって、化学量論比がSi 34から多少ずれていても構わず、本明細書において窒化シリコンという場合には、このように化学量論比がSi 34から多少ずれているものも含む。 Incidentally, depending on the film forming conditions and the like, the stoichiometric ratio is not may be slightly deviated from the Si 3 N 4, when referred to the silicon nitride herein, the thus stoichiometry Si 3 N 4 including those that are slightly shifted. また、中間層としての酸窒化シリコン膜は、例えば、SiONからなる膜や、SiONを主成分とする膜とすればよい。 Further, a silicon oxynitride film as an intermediate layer, for example, film or made of SiON, may be a film composed mainly of SiON. 成膜条件等によって、化学量論比がSiONから多少ずれていてもよく(例えば、Nに対するOの比が1より大きい場合や小さい場合など)、本明細書において酸窒化シリコンという場合には、このように化学量論比がSiONから多少ずれているものも含む。 The deposition conditions and the like, may be stoichiometric ratio slightly deviated from SiON (e.g., when the ratio of O to N or when a small greater than 1, etc.), in the case of silicon oxynitride herein, Thus including those stoichiometric ratio is slightly deviated from the SiON.

【0032】中間層としての窒化シリコン膜や酸窒化シリコン膜は、例えば、ECRプラズマCVD法によって形成することができる。 [0032] Intermediate layer as a silicon film or silicon oxynitride film nitride of, for example, can be formed by ECR plasma CVD method. この方法はECRの高い反応性を利用しているので、基板加熱なしで緻密な膜が得られる。 This method utilizes the high reactivity of the ECR, dense film can be obtained without heating the substrate. 窒化シリコン膜や酸窒化シリコン膜は、スパッタ法等によっても形成することができる。 Silicon silicon nitride film or oxynitride film can be also formed by sputtering or the like.

【0033】中間層としてのアモルファスSiNを主成分とする膜(以下、単にアモルファスSiN膜という) The film mainly composed of amorphous SiN as an intermediate layer (hereinafter referred to simply as an amorphous SiN film)
や酸窒化シリコン膜は、例えば、プラズマCVD法によって形成することができる。 And silicon oxynitride film, for example, can be formed by a plasma CVD method. この方法によると、比較的低温で緻密なアモルファスSiN膜や酸窒化シリコン膜を得ることができる。 According to this method, it is possible to obtain a relatively low temperature in a dense amorphous SiN film or a silicon oxynitride film.

【0034】中間層は、可動イオンのゲート絶縁膜への侵入を防止する機能を高めるには、できるだけ硬質な膜、又は(及び)できるだけ緻密な膜であることが好ましい。 The intermediate layer, to increase the function of preventing the penetration of the gate insulating film of the movable ions, possible hard film, or (and) it is preferred that as much as possible dense film. このような観点から言うと、中間層として窒化シリコン膜を採用する場合には、化学量論組成に近い組成であるSi 34からなる膜、或いは、Si 34を主成分とする膜を中間層とすることが好ましい。 From a this point of view, in case of employing the silicon nitride film as the intermediate layer, the film made of Si 3 N 4 having a composition close to the stoichiometric composition, or film mainly made of Si 3 N 4 it is preferable that the intermediate layer. また、中間層として酸窒化シリコン膜を採用する場合には、Si Further, when employing a silicon oxynitride film as the intermediate layer, Si
ONからなる膜、或いは、SiONを主成分とする膜を中間層とすることが好ましい。 Film made ON, or it is preferable that the film mainly composed of SiON and intermediate layer.

【0035】中間層の層厚は、例えば、10Å以上10 [0035] The thickness of the intermediate layer is, for example, 10Å more than 10
00Å以下、好ましくは100Å以上800Å以下とすればよい。 00Å or less, preferably if 100Å or 800Å or less. 中間層の層厚は薄すぎると、十分な可動イオンのブロッキング性能が得られず、厚すぎると薄膜トランジスタの特性が悪くなる。 When the layer thickness of the intermediate layer is too thin, not blocking performance sufficient mobile ions is obtained, is too thick characteristics of the thin film transistor is degraded. 中間層の緻密性が高く、可動イオンのブロッキング性能が高ければ、それだけゲート絶縁膜の薄膜化が可能となる。 High density of the intermediate layer, the higher the blocking performance of the mobile ions, it is possible to correspondingly thinner gate insulating film. (c)半導体活性層 半導体活性層は前述のようにZnO膜である。 (C) a semiconductor active layer semiconductor active layer is a ZnO film as described above.

【0036】ここでZnO膜は透明導電膜として一般的に利用されているが、本発明の薄膜トランジスタの半導体活性層として用いるZnO膜はキャリア濃度が10 18 [0036] Although here ZnO film is generally used as a transparent conductive film, ZnO film is used as the semiconductor active layer of the thin film transistor of the present invention is a carrier concentration of 10 18
cm cm -3以下に制御されている。 -3 it is controlled below. ZnO膜等の導電性酸化膜においては、一般的にその化学量論組成から少し還元気味にずれることにより酸素空孔などの真性欠陥がドナー順位を形成するため、キャリア濃度が10 18 〜10 19 In the conductive oxide film of the ZnO film and the like, since the intrinsic defects such as oxygen vacancies by deviating slightly reduced slightly from generally the stoichiometric composition to form a donor rank, the carrier concentration is 1018 19
cm -3程度にまで達する。 reach to about cm -3. キャリア濃度が10 18 cm -3 A carrier concentration of 10 18 cm -3
よりも増えるとフェルミ準位が伝導体に達して縮退の状態になり、ZnOは金属のような振る舞いをする。 More than when the Fermi level is in the state of degeneration reached the conductor, ZnO is the behavior, such as a metal. 反対にこのキャリア濃度を10 18 cm -3以下にしてやると縮退の状態が解け、ZnO膜を半導体活性層として用いることができる。 Opposed to solve the state of degeneration and give proper the carrier concentration in the 10 18 cm -3 or less, it is possible to use a ZnO film as the semiconductor active layer.

【0037】半導体活性層としてのZnO膜は、例えば、パルスレーザ蒸着法(PLD法)によって形成することができる。 The ZnO film as the semiconductor active layer, for example, can be formed by a pulsed laser deposition method (PLD method). PLD法によると、ZnO膜中の酸素濃度や不純物濃度を調整して、容易にキャリア濃度、導電率を制御することができる。 According to the PLD method, by adjusting the oxygen concentration, the impurity concentration in the ZnO film, it is possible to easily control the carrier concentration, electrical conductivity.

【0038】半導体活性層としてのZnO膜は、そのキャリア濃度が10 18 cm -3以下で縮退が解けた状態になるのであれば、どのような手法で形成してもよい。 The ZnO film as the semiconductor active layer, if the carrier concentration is in a state where degeneracy is solved in 10 18 cm -3 or less, may be formed by any method. (d)ゲート電極、ソース電極、ドレイン電極 電極(ゲート電極、ソース電極、ドレイン電極)は、例えば、インジウム(In)、アルミニウム(Al)等の金属薄膜とすればよい。 (D) a gate electrode, a source electrode, a drain electrode electrode (gate electrode, source electrode, the drain electrode) is, for example, indium (In), may be a metal thin film of aluminum (Al) or the like.

【0039】電極を可視光に対して透明にする場合には、電極は透明導電膜とすればよい。 [0039] The electrodes in the case of a transparent to visible light, the electrode may be a transparent conductive film. 電極としての透明導電膜は、可視光に対して透明であって、低抵抗率が得られるのであれば、どのような材料からなるものでもよい。 The transparent conductive film as an electrode is transparent to visible light, as long as the low resistivity is obtained, it may be made of any material. 例えば、酸化インジウム(In 23 )、酸化錫(SnO 2 )、ZnO等の酸化物材料や、この酸化物材料に不純物をドープしたものを透明導電膜材料として採用することができる。 For example, indium oxide (In 2 O 3), tin oxide (SnO 2), or oxide materials such as ZnO, a material obtained by doping an impurity into the oxide material may be employed as the transparent conductive film material. In In 23 、SnO 2 、ZnO等の酸化物材料(酸化物半導体)は、元々抵抗率が10 -1 2 O 3, the oxide material of SnO 2, ZnO or the like (oxide semiconductor) was originally resistivity of 10 -1
〜10 -3 Ωcm程度と低いn型の縮退半導体である。 To 10 -3 [Omega] cm about and a low n-type degenerate semiconductor. このような酸化物材料に不純物をドープすることで、キャリア密度を10 20 〜10 21 cm -3程度に増大させ、抵抗率を10 -3 〜10 -4 Ωcm程度にまでさらに低減することができる。 By such an oxide doped with an impurity material, the carrier density is increased to about 10 20 to 10 21 cm -3, the resistivity can be further reduced to 10 -3 to 10 -4 about Ωcm . 具体的に言うと、透明導電膜材料としては、例えば、In 23に錫(Sn)をドープしたもの(一般的にITO(Indium Tin Oxide)と呼ばれる)、 Specifically, the transparent conductive film material, for example, (commonly referred to as ITO (Indium Tin Oxide)) doped with tin (Sn) in an In 2 O 3,
SnO 2にアンチモン(Sb)又はフッ素(F)をドープしたもの、ZnOにInをドープしたもの、ZnOにガリウム(Ga)をドープしたもの(一般的にGZOと呼ばれる)、ZnOにAlをドープしたもの(一般的にAZOと呼ばれる)などを採用すればよい。 Doped with antimony (Sb) or fluorine (F) to SnO 2, doped with In to ZnO, doped with gallium (Ga) to ZnO (commonly referred to as GZO), Al-doped into ZnO things (commonly referred to as AZO) may be adopted, and the like.

【0040】ゲート電極、ソース電極及びドレイン電極の材料は、全て同じものとしてもよく、異なるものとしてもよい。 The gate electrode, a source electrode and a drain electrode material, all may be same or may be different. (e)基板 本発明の薄膜トランジスタは、例えば、絶縁性基板上に形成すればよい。 (E) a thin film transistor substrate present invention, for example, may be formed on an insulating substrate. 基板は、例えば、ガラス基板とすればよい。 Substrate may be, for example, a glass substrate. 基板は、薄膜トランジスタ(電極、半導体活性層、ゲート絶縁膜、中間層等)を形成するときの成膜温度等にもよるが、有機材料や高分子材料、例えば、ポリエーテルスルホン(PES)、ポリカーボネイト(P Substrate, a thin film transistor (the electrodes, the semiconductor active layer, a gate insulating film, an intermediate layer, etc.) depending on the deposition temperature or the like when forming the organic material or a polymer material, for example, polyether sulfone (PES), polycarbonate (P
C)、ポリエチレンテレフタレート(PET)、ポリアリレート(PA)、ポリエーテルエーテルケトン(PE C), polyethylene terephthalate (PET), polyarylate (PA), polyetheretherketone (PE
EK)、アクリル(PMMA)、ABS、ポリ四フッ化エチレンからなるものとしてもよい。 EK), acrylic (PMMA), ABS, may consist of polytetrafluoroethylene. 基板は、可撓性を有するものとしてもよい。 The substrate may be one having flexibility. (f) 本発明の薄膜トランジタにおいては、ZnOからなる半導体活性層は前述のように可視光に対して透明であり、開口率を高めることができる。 In the thin film Toranjita of (f) the present invention, a semiconductor active layer composed of ZnO is transparent to visible light as mentioned above, it is possible to increase the aperture ratio.

【0041】開口率をさらに高めるなどのために、ゲート絶縁膜、中間層、ゲート電極、ソース電極及びドレイン電極のうちの少なくとも一つを透明にしてもよい。 [0041] For such further increase the aperture ratio, the gate insulating film, an intermediate layer, a gate electrode, at least one may be transparent of the source electrode and the drain electrode. さらに言うと、これらのうちの少なくとも一つを可視光に対して透明にしてもよい。 More say, may be at least one of them transparent to visible light. 例えば、エネルギーバンドギャップが3eV以上である材料によって、ゲート絶縁膜、中間層、ゲート電極、ソース電極又はドレイン電極を形成すれば、それを可視光に対して透明にすることができる。 For example, a material the energy band gap is greater than or equal to 3 eV, the gate insulating film, an intermediate layer, a gate electrode, by forming the source electrode or the drain electrode can be made transparent it to visible light.

【0042】ゲート絶縁膜、中間層、ゲート電極、ソース電極及びドレイン電極の全てを透明にすることで、開口率ほぼ100%を達成することができる。 The gate insulating film, an intermediate layer, by a transparent all gate electrodes, the source electrode and the drain electrode, it is possible to achieve near aperture ratio of 100%.

【0043】また、薄膜トランジタを形成する基板も透明にしてもよい。 [0043] It is also possible to also transparent substrate to form a thin film Toranjita.

【0044】 [0044]

【発明の実施の形態】[2] 以下、本発明の実施の形態を図面を参照して説明する。 DETAILED DESCRIPTION OF THE INVENTION [2] Hereinafter, an embodiment of the present invention with reference to the drawings.

【0045】本発明の薄膜トランジスタ(TFT)の一例の概略構成図を図1に示す。 [0045] An example schematic diagram of a thin film transistor (TFT) of the present invention shown in FIG.

【0046】図1に示す薄膜トランジスタT1は、ボトムゲート型の薄膜トランジスタである。 The thin film transistor T1 shown in FIG. 1 is a bottom-gate thin film transistor.

【0047】薄膜トランジスタT1は、絶縁性基板1上に形成されている。 The thin film transistor T1 is formed on the insulating substrate 1. 基板1上には、ゲート電極2、ゲート絶縁膜31、中間層32、半導体活性層4がこの順に形成されている。 On the substrate 1, a gate electrode 2, the gate insulating film 31, the intermediate layer 32, the semiconductor active layer 4 is formed in this order. 半導体活性層4上には、さらにソース電極5とドレイン電極6が形成されている。 On the semiconductor active layer 4 is further formed a source electrode 5 and drain electrode 6.

【0048】半導体活性層4は、酸化亜鉛(ZnO)からなり、可視光に対して透明である。 The semiconductor active layer 4 is made of zinc oxide (ZnO), transparent to visible light. 半導体活性層4としてのZnO膜は、そのキャリア濃度が10 18 cm -1以下となるように形成されたものである。 ZnO film as the semiconductor active layer 4, one whose carrier concentration is formed so as to be 10 18 cm -1 or less.

【0049】ゲート絶縁膜31は、抵抗率が10 7 Ωc The gate insulating film 31, the resistivity is 10 7 .omega.c
m以上であり、本例ではSiO 2からなる。 not less than m, made of SiO 2 in this embodiment.

【0050】中間層32は、本例では窒化シリコンからなる。 The intermediate layer 32 is made of silicon nitride in this example.

【0051】本発明の薄膜トランジスタT1においては、半導体活性層4とゲート絶縁膜31の間に中間層3 [0051] In the thin film transistor T1 of the present invention, the semiconductor active layer 4 and the intermediate layer 3 between the gate insulating film 31
2を設けたことによって、半導体活性層4(ZnO膜) By providing two semiconductor active layer 4 (ZnO film)
からゲート絶縁膜31へのZnイオンの侵入をブロックすることができ、Znイオンがゲート絶縁膜31において拡散することを抑制できる。 Intrusion of Zn ions into the gate insulating film 31 can block the possible to prevent the Zn ions diffuse in the gate insulating film 31. これにより、Znイオンによるゲート絶縁膜31(SiO 2膜)の絶縁性能の低下を抑制でき、ゲート絶縁膜31は安定して高い絶縁性を維持することができる。 This can suppress a decrease in insulation performance of the gate insulating film 31 (SiO 2 film) by Zn ions, the gate insulating film 31 can be maintained high and stable insulation. また、ゲート絶縁膜31を中間層32で覆った後に、半導体活性層(ZnO膜)4が形成されるため、ZnO膜4を形成するときの原子や粒子などの衝突によるダメージからゲート絶縁膜31を中間層32によって保護することができ、これによってもゲート絶縁膜31の絶縁性能の低下を抑制することができる。 Further, the gate insulating film 31 was covered with the intermediate layer 32, since the semiconductor active layer (ZnO film) 4 is formed, the gate insulating damage from the collision of such atoms or particles when forming a ZnO film 4 film 31 the can be protected by the intermediate layer 32, which also can suppress the reduction in the insulation performance of the gate insulating film 31. このようにゲート絶縁膜31は高い絶縁性を長期にわたり安定して維持することができるため、ゲート絶縁膜31におけるリーク電流を長期にわたり安定して抑制できる。 The gate insulating film 31 as is because it is possible to stably maintain a high insulating property over a long period, the leakage current in the gate insulating film 31 can be stably suppressed over a long period. その結果、本発明の薄膜トランジスタT1によると安定したトランジスタ特性が得られる。 As a result, stable transistor characteristics can be obtained according to the thin film transistor T1 of the present invention.

【0052】また、半導体活性層4としてのZnO膜は可視光に対して透明であるので、半導体活性層4に可視光が入射しても、本発明の薄膜トランジスタT1はトランジスタ特性の変化等の影響を受けにくい。 [0052] Further, since the ZnO film as the semiconductor active layer 4 is transparent to visible light, even if visible light is incident on the semiconductor active layer 4, the thin film transistor T1 of the present invention the effect of changes in transistor characteristics less susceptible. したがって、本発明の薄膜トランジスタT1には遮光層を設ける必要がなく、それだけ工程少なく作製することができる。 Accordingly, the thin film transistor T1 of the present invention there is no need to provide a light shielding layer can be manufactured correspondingly step less.

【0053】また、半導体活性層4が可視光に対して透明であるので、表示素子、光電変換素子等において本発明の薄膜トランジスタT1を使用するときには、その開口率を高めることができる。 [0053] Further, since the semiconductor active layer 4 is transparent to visible light, when using a thin film transistor T1 of the present invention in a display device, a photoelectric conversion element or the like can increase the aperture ratio.

【0054】なお、本発明の薄膜トランジスタは、ボトムゲート型に限定されるものではなく、トップゲート型にしてもよい。 [0054] Incidentally, the thin film transistor of the present invention is not limited to the bottom gate type, or may be a top gate type. [3]実施例1、比較例1 実施例1においては、中間層を有する薄膜トランジスタを次のように作製し、そのトランジスタ特性等を調べた。 [3] Example 1, Comparative Example 1 In Example 1, to prepare a thin film transistor having an intermediate layer as follows, were examined their transistor properties.

【0055】本発明の薄膜トランジスタとの比較のために、比較例1においては、中間層を有しない薄膜トランジスタも作製し、そのトランジスタ特性等も調べた。 [0055] For comparison with the thin film transistor of the present invention, in Comparative Example 1 also produced a thin film transistor having no intermediate layer was also examined the transistor characteristics. [3−1] まず、実施例1において作製した薄膜トランジスタT2の概略構造を図2を参照して説明する。 [3-1] First, the schematic structure of a thin film transistor T2 prepared in Example 1 will be described with reference to FIG. 薄膜トランジスタT2は、ボトムゲート型の薄膜トランジスタである。 Thin film transistor T2 is a bottom-gate thin film transistor.

【0056】薄膜トランジスタT2は、透明絶縁性の基板1上に形成されている。 [0056] The thin film transistor T2 is formed on the substrate 1 of the transparent insulating. 基板1はガラス基板である。 The substrate 1 is a glass substrate.

【0057】基板1上にはCrからなるゲート電極2、 [0057] The gate electrode 2 made of Cr on the substrate 1,
ゲート電極を覆うように酸化シリコン(SiO 2 )からなるゲート絶縁膜31、窒化シリコンからなる中間層3 The gate insulating film 31 made of silicon oxide so as to cover the gate electrode (SiO 2), an intermediate layer 3 made of silicon nitride
2が形成されている。 2 is formed. 中間層32上には、キャリア密度や導電率が所定値に制御されたZnOからなる半導体活性層4が形成されている。 On the intermediate layer 32 has a carrier density and electrical conductivity are semiconductor active layer 4 made of ZnO which has been controlled to a predetermined value is formed.

【0058】半導体活性層4の上には、チャネル保護とパッシベーションのための保護層7が形成されている。 [0058] On the semiconductor active layer 4, a protective layer 7 for channel protection and passivation is formed.

【0059】また、半導体活性層4等の上には、半導体活性層4の一部、中間層32の露出する部分、ゲート絶縁膜31の露出する部分を覆うように、層間絶縁膜8 [0059] Further, on such semiconductor active layer 4, part of the semiconductor active layer 4, so as to cover the exposed portion of the intermediate layer 32, the exposed portions of the gate insulating film 31, the interlayer insulating film 8
1、82が形成されている。 1,82 are formed.

【0060】保護層7や層間絶縁膜81、82の材料は、例えば、酸化シリコン、窒化シリコン、フッ素を含んだ酸化シリコン等の無機系材料、ポリイミド、アクリル、ポリアミド、ベンゾシクロブテン(BCB)などとすればよい。 [0060] Materials of the protective layer 7 and the interlayer insulating film 81 and 82, for example, silicon oxide, silicon nitride, an inorganic material such as silicon oxide containing fluorine, polyimide, acrylic, polyamide, benzocyclobutene (BCB), etc. And it is sufficient.

【0061】半導体活性層4上には、さらに、Inからなるソース電極5とドレイン電極6が、保護層7や層間絶縁膜81、82の一部を覆うように形成されている。 [0061] On the semiconductor active layer 4, furthermore, the source electrode 5 and drain electrode 6 made of In is formed so as to cover a part of the protective layer 7 and the interlayer insulating film 81. [3−2] 実施例1においては、薄膜トランジスタT [3-2] In Example 1, a thin film transistor T
2を次のようにして作製した。 It was produced 2 in the following manner. (a)ゲート電極2 まず、ゲート電極2とする所定形状のCr膜を基板1上に次のようにして形成した。 (A) a gate electrode 2 First, a Cr film having a predetermined shape as a gate electrode 2 was formed as follows on the substrate 1.

【0062】はじめに、マグネトロンスパッタリング法によって室温下で、厚みが約3000ÅのCr膜を基板1上に形成した。 [0062] First, at room temperature by magnetron sputtering, the thickness was formed Cr film of about 3000Å ​​on the substrate 1. このCr膜をフォトリソグラフィー法を利用してエッチングすることで、Cr膜を所定形状にパターニングして、ゲート電極2を得た。 The Cr film is etched by using a photolithography method, by patterning the Cr film in a predetermined shape, to obtain a gate electrode 2. (b)ゲート絶縁膜31 次いで、ゲート絶縁膜31とする酸化シリコン膜をゲート電極2上に次のようにして形成した。 (B) a gate insulating film 31 was then a silicon oxide film as a gate insulating film 31 was formed as follows on the gate electrode 2.

【0063】ゲート絶縁膜31としての酸化シリコン膜は、平行平板型RFプラズマCVD法によって、基板温度を400°Cにし、TEOS[Tetraethoxysilane:Si [0063] a silicon oxide film as a gate insulating film 31, a parallel plate type RF plasma CVD method, the substrate temperature to 400 ° C, TEOS [Tetraethoxysilane: Si
(OC 2 H 5 ) 4 ]とO 2を原料にして形成した。 (OC 2 H 5) 4] that the O 2 was formed in the material. この方法により、SiO 2を主成分とする酸化シリコン膜を形成した。 This method was formed a silicon oxide film composed mainly of SiO 2. 酸化シリコン膜の厚みは約2500Åとした。 The thickness of the silicon oxide film was about 2500 Å. この酸化シリコン膜の抵抗率は10 14 Ωcm以上と極めて高く、降伏電界も5MV/cm以上と高かった。 Resistivity of the silicon oxide film is extremely high as 10 14 [Omega] cm or higher, as high as breakdown field also 5 MV / cm or more. (c)中間層32 次いで、中間層32とする窒化シリコン膜をゲート絶縁膜31上に次のようにして形成した。 (C) the intermediate layer 32 then a silicon nitride film to the intermediate layer 32 was formed as follows on the gate insulating film 31.

【0064】中間層としての窒化シリコン膜は、平行平板型RFプラズマCVD法によって、SiH 4ガスとN [0064] Silicon nitride film as an intermediate layer, a parallel plate type RF plasma CVD method, SiH 4 gas and N
3ガスを原料にして形成した。 Of H 3 gas was formed in the material. 窒化シリコン膜は、約500Åの厚みに形成した。 Silicon nitride film was formed to a thickness of about 500 Å.

【0065】プラズマCVD法による窒化シリコン膜の形成手法には、その反応過程の違いから、シランラジカル型とアミノシラン型がある。 [0065] The method of forming the silicon nitride film by the plasma CVD method, a difference in the reaction process, there is a silane radical type and aminosilane type. 緻密な良質の窒化シリコン膜を得るためには、アミノシラン堆積法で形成するのが好ましい。 To obtain a dense high quality silicon nitride film is preferably formed by aminosilane deposition method. この方法は、SiH 4の全てをNH 3と反応させ、堆積種をSi(NH 23とするものである。 This method, all the SiH 4 is reacted with NH 3, the deposition species it is an Si (NH 2) 3.
原料ガスのNH 3 /SiH 4の流量比を大きくする、S The flow ratio of NH 3 / SiH 4 source gas is increased, S
iH 4流量を少なくする、RFパワーを大きくする、又は(及び)成膜装置内でのアミノシラン分子の形成を促進するため相対的に原料ガスの滞留時間を長くすることで、良質な窒化シリコン膜が得られる(DTMurler et to reduce the iH 4 flow rate, increasing the RF power, or (and) by prolonging the residence time of the relatively raw material gas for promoting the formation of the aminosilane molecules in the film forming apparatus, high-quality silicon nitride film is obtained (DTMurler et
al.,J.Non Crys.Solids,Vol.187,p324(1995))。 al., J.Non Crys.Solids, Vol.187, p324 (1995)).

【0066】ここでは、流量比NH 3 /SiH 4 =80 [0066] Here, the flow rate ratio NH 3 / SiH 4 = 80
/10、RFパワー=80W、圧力=60Pa、基板温度=200°Cの条件下にて、平行平板型RFプラズマCVD装置を用いてアミノシラン堆積法によって、中間層32としてのアモルファス窒化シリコン膜を形成した。 / 10, RF power = 80W, pressure = 60 Pa, under conditions of a substrate temperature = 200 ° C, the aminosilane deposition method using a parallel plate RF plasma CVD apparatus, an amorphous silicon nitride film as the intermediate layer 32 did. なお、滞留時間を長くするために高い圧力(本例では60Pa)にて、成膜を行った。 Incidentally, at a high pressure in order to lengthen the residence time (60 Pa in this example) A film was formed. (d)半導体活性層4 次いで、半導体活性層4とするZnO膜を中間層32上に次のようにして形成した。 (D) a semiconductor active layer 4 was then formed as follows the ZnO film to be the semiconductor active layer 4 on the intermediate layer 32.

【0067】半導体活性層4としてのZnO膜は、パルスレーザー蒸着法によって、基板温度を450°Cにして形成した。 [0067] ZnO film as the semiconductor active layer 4, a pulse laser deposition method to form by a substrate temperature of 450 ° C. ZnO膜は、約500Åの厚みに形成した。 ZnO film was formed to a thickness of about 500 Å. ZnO膜中の酸素濃度を調整することで、ZnO膜のキャリア密度及び導電率を所定値に調整した。 By adjusting the oxygen concentration in the ZnO film was adjusted carrier density and conductivity of the ZnO film to a predetermined value. (e)保護層7及び層間絶縁膜81、82 次いで、保護層7及び層間絶縁膜81、82とする窒化シリコン膜を半導体活性層4等の上に次のようにして形成した。 (E) then a protective layer 7 and the interlayer insulating film 81, a silicon nitride film and the protective layer 7 and the interlayer insulating film 81 and 82 was formed as follows on, such as a semiconductor active layer 4.

【0068】保護層7及び層間絶縁膜81、82としての窒化シリコン膜は、プラズマCVD法によって約25 [0068] Silicon nitride film as the protective layer 7 and the interlayer insulating film 81 and 82, about the plasma CVD method 25
00Åの厚みに形成した。 It was formed to a thickness of 00Å. この窒化シリコン膜に、フォトリソグラフィー法を利用したエッチングによって、ソース電極5及びドレイン電極6用のコンタクトホールを形成した。 This silicon nitride film, by etching using a photolithography method to form contact holes for the source electrode 5 and drain electrode 6. このように保護層7及び層間絶縁膜81、8 Thus protective layer 7 and the interlayer insulating film 81,8
2は同時に形成した。 2 was formed at the same time. (f)ソース電極5及びドレイン電極6 次いで、ソース電極5及びドレイン電極6とするIn膜を次のように形成した。 (F) then the source electrode 5 and drain electrode 6, to form an In film and the source electrode 5 and drain electrode 6 as follows.

【0069】はじめに、半導体活性層4や保護層7等の上に、抵抗加熱蒸着法によって約1500Åの厚みのI [0069] First, on such semiconductor active layer 4 and the protective layer 7, approximately 1500Å thick by a resistance heating evaporation method I
n膜を形成した。 n film was formed. このIn膜をフォトリソグラフィー法を利用してエッチングすることで、ソース電極5とする所定形状のIn膜と、ドレイン電極6とする所定形状のIn膜を形成した。 The In film is etched using photolithography, thereby forming the In film having a predetermined shape with the source electrode 5, an In film having a predetermined shape with the drain electrode 6.

【0070】これらにより、図2の薄膜トランジスタT [0070] These thin film transistor T in FIG. 2
2を得た。 2 was obtained. [3−3] なお、保護層や層間絶縁膜の構造、形成方法は上記のものに限定されず、種々変更可能である。 [3-3] The structure of the protective layer or an interlayer insulating film, forming method is not limited to the above, various modifications are possible.

【0071】例えば、図3に示す薄膜トランジスタT3 [0071] For example, a thin film transistor T3 shown in FIG. 3
のようにしてもよい。 It may be of.

【0072】薄膜トランジスタT3は、基板1上に次のようにして形成されたものである。 [0072] The thin film transistor T3 is one formed as follows on the substrate 1. まず、実験例1の薄膜トランジタT1と同様にして、基板1上にゲート電極2、ゲート絶縁膜31、中間層32及び半導体活性層4 First, similar to the thin film Toranjita T1 of Example 1, the gate electrode 2 on the substrate 1, a gate insulating film 31, the intermediate layer 32 and the semiconductor active layer 4
を形成する。 To form.

【0073】次いで、保護層7とする窒化シリコン膜を次のように形成する。 [0073] Then, a silicon nitride film as a protective layer 7 is formed as follows. まず、ゲート絶縁膜31、中間層32及び半導体活性層4を覆うように窒化シリコン膜を形成し、その後フォトリソグラフィー法を利用して、その窒化シリコン膜を所定形状にパターニングすることで、所定形状の保護層7を得る。 First, the gate insulating film 31, the intermediate layer 32 and a silicon nitride film so as to cover the semiconductor active layer 4, and thereafter utilizing the photolithography method, by patterning the silicon nitride film in a predetermined shape, a predetermined shape obtain a protective layer 7.

【0074】次いで、パッシベーション膜83及び層間絶縁膜81、82とするポリイミド膜を次のように形成する。 [0074] Then, a polyimide film to the passivation film 83 and the interlayer insulating film 81 and 82 as follows. まず、ゲート絶縁膜31、中間層32、半導体活性層4及び保護層7を覆うようにポリイミド膜を形成する。 First, the gate insulating film 31, the intermediate layer 32, to form a polyimide film so as to cover the semiconductor active layer 4 and the protective layer 7. この後、このポリイミド膜のソース電極及びドレイン電極を形成する領域にフォトリソグラフィー法を利用して、コンタクトホールを形成して、半導体活性層4の一部を露出させる。 Thereafter, this region forming a source electrode and a drain electrode of the polyimide film by using a photolithography method, to form a contact hole to expose a portion of the semiconductor active layer 4. これにより、半導体活性層等の所定部分を覆う所定形状のパッシベーション膜83及び層間絶縁膜81、82を得る。 This gives a passivation film 83 and the interlayer insulating film 81 and 82 having a predetermined shape to cover a predetermined portion such as a semiconductor active layer.

【0075】最後に、ソース電極5及びドレイン電極6 [0075] Finally, source and drain electrodes 5 and 6
を実施例1と同様に形成して、薄膜トランジスタT3を得る。 The form in the same manner as in Example 1 to obtain a thin film transistor T3. [3−4] 比較例1においては、上記の薄膜トランジスタT2と同様にして、中間層を有しない薄膜トランジスタを形成した。 In [3-4] Comparative Example 1, in the same manner as in the above thin film transistor T2, thereby forming a thin film transistor having no intermediate layer. つまり、比較例1においては、ゲート電極2と半導体活性層4の間にゲート絶縁膜31だけしか配置されていない薄膜トランジスタを形成した。 That is, in Comparative Example 1 was formed a thin film transistor is not disposed only the gate insulating film 31 between the gate electrode 2 and the semiconductor active layer 4.

【0076】実施例1の薄膜トランジスタと、比較例1 [0076] a thin film transistor of Example 1, Comparative Example 1
の薄膜トランジスタの違いは、ゲート絶縁膜(SiO 2 Difference of the thin film transistor, a gate insulating film (SiO 2
膜)31と、半導体活性層(ZnO膜)4の間に、中間層(窒化シリコン膜)32が配置されているか否かだけである。 A film) 31, the semiconductor active layer (between the ZnO film) 4, an intermediate layer (silicon nitride film) 32 is only whether it is located. [3−5] 実施例1の薄膜トランジスタT2と、比較例1の薄膜トランジスタにおけるゲート絶縁膜のリーク電流を次表1に示す。 [3-5] and the thin-film transistor T2 of example 1 shows a leakage current of the gate insulating film in the thin film transistor of Comparative Example 1 in Table 1 below.

【0077】 [0077]

【表1】 [Table 1]

【0078】表1から、中間層(窒化シリコン膜)32 [0078] From Table 1, the intermediate layer (silicon nitride film) 32
を有する実施例1の薄膜トランジスタは、中間層32を有しない比較例1の薄膜トランジスタよりも、そのリーク電流が5桁低減していることがわかる。 The thin film transistor of Example 1 with, rather than a thin film transistor of Comparative Example 1 having no intermediate layer 32, it is found that the leakage current is reduced 5 digits. これにより、 As a result,
中間層(窒化シリコン膜)32によって、半導体活性層(ZnO膜)4からゲート絶縁膜(SiO 2膜)へのZ Z of the intermediate layer (silicon nitride film) 32, the semiconductor active layer to the (ZnO film) 4 from the gate insulating film (SiO 2 film)
nイオンの拡散が抑制されるなどして、リーク電流を低減できることがわかる。 And a diffusion of n ions is suppressed, it is possible to reduce the leakage current.

【0079】図4に実施例1の薄膜トランジスタT2のVds(ドレイン−ソース間電圧)−Id(ドレイン電流)特性を示す。 [0079] Vds of the TFT T2 in the first embodiment in FIG. 4 - shows a (drain-source voltage) -Id (drain current) characteristic. なお、図4において、Vg 1 〜Vg 7 Incidentally, in FIG. 4, Vg 1 through Vg 7
はゲート電圧であり、Vg 1 、Vg 2 、・・・、Vg 7 A gate voltage, Vg 1, Vg 2, ··· , Vg 7
の順にゲート電圧は高い。 Gate voltage in the order of the high.

【0080】図4から、実施例1の薄膜トランジスタT [0080] From Figure 4, in the first embodiment the thin film transistor T
2においては、数Vのゲート電圧の変化で、ドレイン電流Idが大きく変化していることがわかる。 In 2, the change of the gate voltage of several V, it can be seen that the drain current Id is changed significantly. つまり、実施例1の薄膜トランジスタT2が良好なスイッチング特性を有していることがわかる。 In other words, it can be seen that the thin film transistor T2 of Example 1 has a good switching characteristic.

【0081】これに対して、比較例1の薄膜トランジスタは、リーク電流が大きいため、スイッチング動作しないか、動作してもゲート電圧の変化に対してほんのわずかなドレイン電流の変化しか見られなかった。 [0081] In contrast, the thin-film transistor of Comparative Example 1, since the leakage current is large, or not switching operations, were observed only change only a small drain current to a change in gate voltage in operation. 比較例1 Comparative Example 1
の薄膜トランジスタのVds−Id特性を図9に示す。 It shows the Vds-Id characteristic of the TFT in FIG.
なお、図9においてVg 1 〜Vg 7は図4のものに対応している。 Incidentally, Vg 1 through Vg 7 in FIG. 9 corresponds to that of FIG. 図9から、比較例1の薄膜トランジスタでは、スイッチング特性が得られないことがわかる。 9, the thin film transistor of Comparative Example 1, it can be seen that the switching characteristics can not be obtained. なお、比較例1の薄膜トランジスタのドレイン電流Id Incidentally, the thin film transistor Comparative Example 1 the drain current Id
は、ゲート絶縁膜のリーク電流が大きいため、実施例1 Since the leakage current of the gate insulating film is large, Example 1
の薄膜トランジスタのドレイン電流Idに比べて大きくなっているものと考えられる。 It is considered that is larger than the drain current Id of the TFT.

【0082】これらにより、中間層(窒化シリコン膜) [0082] These intermediate layers (silicon nitride film)
を有する実施例1の薄膜トランジスタによると、中間層を有しない比較例1の薄膜トランジスタに比べて、良好なスイッチング特性が得られることがわかる。 According to the thin film transistor of Example 1 having, as compared with the intermediate layer to the thin film transistor of Comparative Example 1 having no, it is found that a good switching characteristic can be obtained. また、実施例1の薄膜トランジスタT2においては、バンドギャップの広いZnO膜を半導体活性層に用いているため、 In the thin-film transistor T2 of the first embodiment, the use of a wide ZnO film band gap semiconductor active layer,
遮光層を設けなくても、光による特性変化等の影響を受けにくい。 Without providing a light shielding layer, hardly affected by the characteristic change or the like by light. [3−6] なお、実施例1においては、中間層32として、プラズマCVD法により形成したアモルファス窒化シリコン膜を用いたが、可動イオンのブロック効果が大きく、硬度や緻密性が高ければ他の材料からなる膜を中間層としてもよい。 [3-6] In Example 1, as an intermediate layer 32, but using an amorphous silicon nitride film formed by plasma CVD method, blocks the effects of mobile ions is large, the other the higher the hardness and denseness film may be used as the intermediate layer of material. また、中間層32は透明でなくてもよく、有機材料や高分子材料からなる膜を中間層として用いてもよい。 The intermediate layer 32 may not be transparent, it may be used a film made of an organic material or a polymer material as an intermediate layer.

【0083】また、実施例1においては、中間層32としての窒化シリコン膜の膜厚を500Åとしたが、可動イオンのブロッキング性能や緻密性が確保できるのであれば、もっと薄くしてもよい。 [0083] In Example 1, the thickness of the silicon nitride film as the intermediate layer 32 was a 500 Å, if the blocking performance and compactness of mobile ions can be secured, it may be thinner. 中間層32を薄くすれば、薄膜トランジスタの特性が向上する。 Thinner intermediate layer 32, characteristics of the thin film transistor are improved. [4]実施例2 実施例2においては、図2の薄膜トランジスタと同じ構造の薄膜トランジスタを形成した。 [4] In Example 2 Example 2 was formed a thin film transistor having the same structure as the thin film transistor of FIG. なお、実施例1の薄膜トランジスタと、実施例2の薄膜トランジスタは、電極等を透明にした点などが異なっている。 Incidentally, the thin film transistor of the thin film transistor and, in Example 2 of Example 1, such that the electrodes and the like on the transparent are different.

【0084】実施例2においては、薄膜トランジスタは透明なガラス基板1上に次のように形成した。 [0084] In Example 2, the thin film transistor was formed as follows on a transparent glass substrate 1.

【0085】まず、ゲート電極2とするITO膜を基板1上に次のようにして形成した。 [0085] First, an ITO film having a gate electrode 2 was formed as follows on the substrate 1. はじめに、スパッタリング法によって、厚みが約500ÅのITO膜を基板1 First, by a sputtering method, a substrate an ITO film having a thickness of about 500 Å 1
上に形成した。 It was formed in the above. このITO膜をフォトリソグラフィー法を利用してエッチングすることで、ITO膜を所定形状にパターニングし、ゲート電極2を得た。 The ITO film is etched by using photolithography, patterning the ITO film into a predetermined shape, to obtain a gate electrode 2.

【0086】次いで、実施例1と同様にして、ゲート絶縁膜31とする酸化シリコン膜、中間層32とする窒化シリコン膜、半導体活性層4とするZnO膜、保護層7 [0086] Then, in the same manner as in Example 1, a silicon oxide film as a gate insulating film 31, the intermediate layer 32 to the silicon nitride film, a semiconductor active layer 4 to the ZnO film, the protective layer 7
とする窒化シリコン膜、層間絶縁膜81、82とする窒化シリコン膜を順に形成した。 A silicon nitride film, a silicon nitride film as the interlayer insulating film 81 and 82 are formed in this order.

【0087】次いで、ソース電極5及びドレイン電極6 [0087] Then, the source electrode 5 and drain electrode 6
とするITO膜を次のように形成した。 The ITO film that was formed in the following manner. はじめに、半導体活性層4や保護層7等上に、スパッタリング法によって約1500Åの厚みのITO膜を形成した。 First, the semiconductor active layer 4 and the protective layer 7, etc. was formed on the ITO film of about 1500Å in thickness by sputtering. このIT The IT
O膜をフォトリソグラフィー法を利用してエッチングすることで、ソース電極5とする所定形状のITO膜と、 O film is etched by using photolithography, and the ITO film having a predetermined shape with the source electrode 5,
ドレイン電極6とする所定形状のITO膜を形成した。 ITO film having a predetermined shape with the drain electrode 6 were formed.

【0088】これらにより、薄膜トランジスタを得た。 [0088] These, to obtain a thin film transistor.

【0089】実施例2の薄膜トランジスタによると、実施例1の薄膜トランジスタと同様に、リーク電極を抑制でき、良好なスイッチング特性が得られる。 [0089] According to the thin film transistor of Example 2, similarly to the thin film transistor of Example 1 can suppress the leakage electrode, good switching characteristic can be obtained.

【0090】実施例2の薄膜トランジスタにおいては、 [0090] In the thin film transistor of Example 2,
半導体活性層(ZnO膜)4の他に、基板1が透明で、 Semiconductor active layer to another (ZnO film) 4, the substrate 1 is transparent,
ゲート電極2、ソース電極5及びドレイン電極6が透明導電膜であるITO膜であるため、実施例1の薄膜トランジスタに比べて、薄膜トランジスタ中の透明部分の面積が大きくなっている。 Since the gate electrode 2, the source electrode 5 and drain electrode 6 is an ITO film which is a transparent conductive film, as compared to the thin film transistor of Example 1, the area of ​​the transparent portion in the thin film transistor is increased. したがって、実施例2の薄膜トランジスタを例えば光電変換素子、発光素子、表示素子(液晶表示素子等)において例えばスイッチング素子として利用するときには、開口率を高めることができる。 Thus, a thin film transistor, for example, a photoelectric conversion element of Example 2, the light emitting element, when utilizing the display device (liquid crystal display element or the like) for example as a switching element, it is possible to increase the aperture ratio.

【0091】なお、実施例2においては、可動イオンをブロックするなどのための透明な中間層32として窒化シリコン膜を用いたが、硬度や緻密性が高く、可動イオン等のブロック効果が大きい材料で、エネルギーバンドギャップが3eV以上であれば、他の材料からなる膜を中間層としてもよく、上記述べたプラズマCVD法以外の方法により中間層を形成してもよい。 [0091] In Example 2, a transparent as the intermediate layer 32 is a silicon nitride film, hardness and high denseness, large blocks effects such as mobile ions materials for such blocking mobile ions in, if the energy band gap 3eV or more, a film made of another material may be a middle layer, an intermediate layer may be formed by a method other than plasma CVD method described above.

【0092】また、実施例2においては、高抵抗な透明なゲート絶縁膜31としてSiO 2膜を用いたが、高抵抗でエネルギーバンドギャップが3eV以上であれば、 [0092] In Example 2, was used SiO 2 film as a high-resistance transparent gate insulating film 31, if the energy band gap 3eV or a high resistance,
他の材料からなる膜をゲート絶縁膜としてもよい。 A film made of other materials may be used as the gate insulating film.

【0093】また、実施例2においては、中間層32としての窒化シリコン膜の膜厚を500Åとしたが、可動イオンのブロッキング性能や緻密性が確保できるのであれば、もっと薄くしてもよい。 [0093] In Example 2, the thickness of the silicon nitride film as the intermediate layer 32 was a 500 Å, if the blocking performance and compactness of mobile ions can be secured, it may be thinner. 中間層32を薄くすれば、薄膜トランジスタの特性が向上する。 Thinner intermediate layer 32, characteristics of the thin film transistor are improved. [5] 本発明の薄膜トランジスタは、例えば、光電変換素子(受光素子)、液晶表示素子、発光素子(EL素子、LED素子等)においてスイッチング素子として利用することができる。 [5] The thin film transistor of the present invention, for example, a photoelectric conversion element (light receiving element), a liquid crystal display device can be used as a switching element in a light-emitting device (EL device, LED elements or the like).

【0094】本発明の薄膜トランジスタを備える光電変換表示装置の一例の概略平面図を図5に示す。 [0094] An example schematic plan view of the photoelectric conversion panel display device having a TFT of the present invention shown in FIG. また、この表示装置の図5のX−X線に沿う概略断面図を図6に示す。 Moreover, a schematic cross-sectional view taken along the line X-X in FIG. 5 of the display device in FIG.

【0095】図5及び図6に示す表示装置においては、 [0095] In the display device shown in FIGS. 5 and 6,
基板1上に複数の画素部Pがマトリクス状に形成されている。 A plurality of pixel portions P on the substrate 1 are formed in a matrix. 各画素部Pに対してそれぞれ本発明の薄膜トランジスタT2が次のように設けられている。 TFT T2 of the present invention respectively provided as follows: for each pixel unit P.

【0096】基板1上には、対向電極(下部電極)9 [0096] On the substrate 1, the counter electrode (lower electrode) 9
5、表示媒体層96、画素電極97、層間絶縁膜98が形成されている。 5, the display medium layer 96, the pixel electrode 97, an interlayer insulating film 98 is formed. 対向電極95、表示媒体層96、画素電極97によって一つの表示素子部が構成されている。 The counter electrode 95, the display medium layer 96, one display element unit by the pixel electrode 97 is formed.
対向電極95は各画素部Pに対して共通のものであり、 Counter electrode 95 is common to each pixel unit P,
画素電極97は各画素部Pに対してそれぞれ設けられている。 Pixel electrodes 97 are provided for each pixel unit P.

【0097】薄膜トランジスタT2は、層間絶縁膜98 [0097] The thin film transistor T2, an interlayer insulation film 98
の上に形成されている。 It is formed on the.

【0098】薄膜トランジスタT2のドレイン電極6 [0098] The drain of the thin-film transistor T2 electrode 6
は、対応する画素電極97に接続されている。 It is connected to the corresponding pixel electrode 97. ドレイン電極6は層間絶縁膜98に設けられているコンタクトホールを介して画素電極97に接続されている。 A drain electrode 6 is connected to the pixel electrode 97 through a contact hole provided in the interlayer insulating film 98.

【0099】薄膜トランジスタT2のソース電極5は、 [0099] The source electrode 5 of the thin-film transistor T2 is,
ITOからなる透明な信号電極931又は932に接続されている。 It is connected to the transparent signal electrodes 931 or 932 made of ITO. なお、ソース電極と信号電極は一体的に形成されているものであり、信号電極の一部の部分が薄膜トランジスタT2におけるソース電極5として機能する。 Note that the source electrode and the signal electrode are those which are integrally formed, part of the portion of the signal electrode serving as a source electrode 5 in the thin-film transistor T2.

【0100】薄膜トランジスタT2のゲート電極2は、 [0100] The gate electrode 2 of the thin-film transistor T2 is,
ITOからなる透明な走査電極941又は942に接続されている。 It is connected to the transparent scan electrode 941 or 942 made of ITO. なお、ゲート電極と走査電極は一体的に形成されているものであり、走査電極の一部の部分が薄膜トランジスタT2におけるゲート電極2として機能する。 Incidentally, the gate electrode and the scan electrode is one which is integrally formed, part of the portion of the scan electrode functions as a gate electrode 2 in the thin-film transistor T2.

【0101】実施例2の薄膜トランジスタT2のゲート電極2、ゲート絶縁膜31、中間層32、半導体活性層4、ドレイン電極5及びソース電極6は前述のように透明であるため、各画素部Pに設けられている薄膜トランジスタT2は全体に透明である。 [0102] The gate electrode 2 of the TFT T2 in the second embodiment, the gate insulating film 31, the intermediate layer 32, the semiconductor active layer 4, since the drain electrode 5 and the source electrode 6 is transparent as mentioned above, in each pixel portion P provided the thin-film transistor T2 is transparent throughout. したがって、画素部P Thus, the pixel portion P
への入射光量或いは画素部Pからの射出光量を増大させることができる。 Amount of light emitted from the incident light amount or the pixel portion P to may be increased. この表示装置においては、各画素部P In this display device, each pixel unit P
において薄膜トランジスタT2の占める面積にかかわらず、開口率100%を達成することができる。 In spite of the area occupied by the thin film transistor T2, it is possible to achieve a 100% opening ratio.

【0102】図5及び図6の表示装置の作製方法としては、基板に表示素子部及び薄膜トランジスタを順次形成していく方法や、はじめに薄膜トランジスタを透明絶縁性基板上に形成し、その薄膜トランジスタを形成した基板の背面と、別の基板との間に表示媒体層を挟持する方法がある。 [0102] As a method for manufacturing a display device of FIG. 5 and 6, a method of successively forming a display element portion and the thin film transistor substrate, initially forming a thin film transistor on a transparent insulating substrate to form the thin film transistor there is a method of sandwiching the rear surface of the substrate, a display medium layer between the different substrates. 後者の場合、図6の層間絶縁膜98がガラス基板等に変更される。 In the latter case, the interlayer insulating film 98 in FIG. 6 is changed to the glass substrate or the like.

【0103】図7は、表示装置の他の例の概略断面図である。 [0103] Figure 7 is a schematic cross-sectional view of another example of the display device. この表示装置においては、薄膜トランジスタT2 In this display device, the thin-film transistor T2
は基板11上に直接形成されている。 It is directly formed on the substrate 11. 薄膜トランジスタT2上には、厚みが均一になるように、層間絶縁膜98 Over the thin film transistor T2, as the thickness becomes uniform, the interlayer insulating film 98
が形成されている。 There has been formed. この層間絶縁膜98には画素電極9 Pixel electrodes 9 on the interlayer insulating film 98
7のためのコンタクトホールが形成されており、画素電極97はコンタクトホールを介してドレイン電極6と接続している。 A contact hole is formed for the 7, the pixel electrode 97 is connected to the drain electrode 6 through a contact hole. 画素電極97に対向する位置には、基板1 At a position opposite to the pixel electrode 97, the substrate 1
2上に形成された対向電極95が配置されている。 Counter electrode 95 is arranged which is formed on the 2. そして、画素電極97と対向電極95の間に液晶層等の表示媒体層96が配置されている。 The display medium layer 96 of the liquid crystal layer or the like is disposed between the pixel electrode 97 and the counter electrode 95.

【0104】以上の説明した表示装置においては、薄膜トランジスタはボトムゲート型であるが、トップゲート型としてもよい。 [0104] In the display device above description, the thin film transistor is a bottom gate type may be a top gate type.

【0105】 [0105]

【発明の効果】以上説明したように本発明は、ZnO膜を半導体活性層とする薄膜トランジスタであって、ゲート絶縁膜のリーク電流を抑制し、良好なトランジスタ特性が得られる薄膜トランジスタを提供することができる。 The present invention described above, according to the present invention may be a thin film transistor for the ZnO film and the semiconductor active layer, to suppress the leakage current of the gate insulating film, to provide good TFT transistor characteristics can be obtained it can.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明に係る薄膜トランジスタの一例の概略構成図である。 1 is a schematic diagram of an example of a thin film transistor according to the present invention.

【図2】本発明に係る薄膜トランジスタの他の例の概略断面図である。 2 is a schematic cross-sectional view of another example of a thin film transistor according to the present invention.

【図3】本発明に係る薄膜トランジスタのさらに他の例の概略断面図である。 Figure 3 is a further schematic cross-sectional view of another example of a thin film transistor according to the present invention.

【図4】実施例1において作製した薄膜トランジスタのVds−Id特性を示す図である。 4 is a diagram illustrating the Vds-Id characteristic of the TFT manufactured in Example 1.

【図5】本発明に係る薄膜トランジスタを備える表示装置の一例の概略平面図である。 5 is a schematic plan view of an example of a display device having a TFT according to the present invention.

【図6】図5の表示装置の概略断面図である。 6 is a schematic cross-sectional view of a display device of FIG.

【図7】本発明に係る薄膜トランジスタを備える表示装置の他の例の概略断面図である。 7 is a schematic cross-sectional view of another example of a display device having a TFT according to the present invention.

【図8】従来の薄膜トランジスタの一例の概略断面図である。 8 is a schematic sectional view of an example of a conventional thin film transistor.

【図9】比較例1において作製した薄膜トランジスタのVds−Id特性を示す図である。 9 is a diagram showing the Vds-Id characteristic of the TFT manufactured in Comparative Example 1.

【符号の説明】 DESCRIPTION OF SYMBOLS

T1、T2、T3 薄膜トランジスタ 1、11、12 基板 2 ゲート電極 3 ゲート絶縁膜 31 ゲート絶縁膜 32 中間層 4 半導体活性層 5 ソース電極 6 ドレイン電極 7 保護層 81、82 層間絶縁膜(層間絶縁層) 931、932 信号電極 941、942 走査電極 P 画素部 95 対向電極 96 表示媒体層 97 画素電極 98 層間絶縁膜 T1, T2, T3 TFT 1, 11, 12 substrate 2 gate electrode 3 gate insulating film 31 a gate insulating film 32 interlayer 4 semiconductor active layer 5 source electrode 6 drain electrode 7 protective layers 81 and 82 an interlayer insulating film (interlayer insulating layer) 931, 932 signal electrodes 941 and 942 scanning electrodes P pixel portion 95 counter electrode 96 display medium layer 97 pixel electrode 98 interlayer insulating film

───────────────────────────────────────────────────── フロントページの続き (72)発明者 北村 健 大阪府大阪市中央区安土町二丁目3番13号 大阪国際ビル ミノルタ株式会社内 (72)発明者 宮武 茂博 大阪府大阪市中央区安土町二丁目3番13号 大阪国際ビル ミノルタ株式会社内 (72)発明者 田畑 仁 大阪府吹田市上山田5−1−603 (72)発明者 川合 知二 大阪府箕面市小野原東5−26−15−615 Fターム(参考) 5F110 AA30 BB01 CC05 CC07 DD01 DD02 DD06 EE02 EE03 EE04 EE07 EE44 FF02 FF03 FF04 FF05 FF09 FF28 FF30 FF31 GG01 GG06 GG25 GG42 HL02 HL03 HL22 NN02 NN12 NN23 NN24 NN27 NN35 NN72 ────────────────────────────────────────────────── ─── of the front page continued (72) inventor Ken Kitamura Chuo-ku, Osaka-shi, Azuchi-chome No. 3 No. 13 Osaka International building Minolta within Co., Ltd. (72) inventor Shigehiro Miyatake Chuo-ku, Osaka-shi, Azuchi chome No. 3 No. 13 Osaka International building Minolta within Co., Ltd. (72) inventor Hitoshi Tabata Suita, Osaka Prefecture Kamiyamada 5-1-603 (72) inventor Tomoji Kawai Osaka Prefecture Mino Onoharahigashi 5-26-15- 615 F-term (reference) 5F110 AA30 BB01 CC05 CC07 DD01 DD02 DD06 EE02 EE03 EE04 EE07 EE44 FF02 FF03 FF04 FF05 FF09 FF28 FF30 FF31 GG01 GG06 GG25 GG42 HL02 HL03 HL22 NN02 NN12 NN23 NN24 NN27 NN35 NN72

Claims (9)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】半導体活性層、ゲート電極、ソース電極、 1. A semiconductor active layer, a gate electrode, a source electrode,
    ドレイン電極及び前記ゲート電極と前記半導体活性層の間に配置されたゲート絶縁膜を有し、 前記半導体活性層が酸化亜鉛(ZnO)からなり、 前記ゲート絶縁膜と前記半導体活性層との間に前記ゲート絶縁膜の材料とは異なる組成の材料からなる中間層が設けられていることを特徴とする薄膜トランジスタ。 Has placed a gate insulating film between the drain electrode and the gate electrode and the semiconductor active layer, wherein become semiconductor active layer is of zinc oxide (ZnO), between the said gate insulating film semiconductor active layer a thin film transistor wherein the intermediate layer of a material of different composition than the material of the gate insulating film is provided.
  2. 【請求項2】前記ゲート絶縁膜は、10 7 Ωcm以上の抵抗率を有する請求項1記載の薄膜トランジスタ。 Wherein said gate insulating film, a thin film transistor of claim 1 having 10 7 [Omega] cm or more resistivity.
  3. 【請求項3】前記中間層は、前記ゲート絶縁膜よりも硬質な材料からなる請求項1又は2記載の薄膜トランジスタ。 Wherein the intermediate layer according to claim 1 or 2 thin film transistor according made of a hard material than the gate insulating film.
  4. 【請求項4】前記中間層が窒化シリコンを主成分とする膜である請求項1から3のいずれかに記載の薄膜トランジスタ。 4. A thin film transistor according to any one of 3 claims 1 intermediate layer is a film mainly containing silicon nitride.
  5. 【請求項5】前記中間層が酸窒化シリコンを主成分とする膜である請求項1から3のいずれかに記載の薄膜トランジスタ。 5. The thin film transistor according to any one of 3 claims 1 intermediate layer is a film mainly containing silicon oxynitride.
  6. 【請求項6】前記ゲート絶縁膜が酸化シリコンを主成分とする膜である請求項1から5のいずれかに記載の薄膜トランジスタ。 6. The thin film transistor according to any one of 5 claims 1 gate insulating film is a film mainly composed of silicon oxide.
  7. 【請求項7】前記中間層の層厚が10Å以上1000Å 7. A thickness of the intermediate layer is 10Å or more 1000Å
    以下である請求項1から6のいずれかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 6, which follows.
  8. 【請求項8】前記ゲート絶縁膜、前記中間層、前記ゲート電極、前記ソース電極及び前記ドレイン電極のうちの少なくとも一つが透明である請求項1から7のいずれかに記載の薄膜トランジスタ。 Wherein said gate insulating film, the intermediate layer, the gate electrode, the thin film transistor according to claim 1, wherein at least one of which is transparent of the source electrode and the drain electrode.
  9. 【請求項9】透明な絶縁性基板上に形成されている請求項1から8のいずれかに記載の薄膜トランジスタ。 9. The thin film transistor according to any one of claims 1 to 8 formed on a transparent insulating substrate.
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