JP4166105B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4166105B2
JP4166105B2 JP2003059905A JP2003059905A JP4166105B2 JP 4166105 B2 JP4166105 B2 JP 4166105B2 JP 2003059905 A JP2003059905 A JP 2003059905A JP 2003059905 A JP2003059905 A JP 2003059905A JP 4166105 B2 JP4166105 B2 JP 4166105B2
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layer
semiconductor device
conductive
semiconductor
electrode
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JP2004273614A (en
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英男 大野
雅司 川崎
利典 杉原
達也 藤田
久雄 越智
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シャープ株式会社
英男 大野
雅司 川崎
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【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、半導体装置およびその製造方法に関している。 The present invention is directed to a semiconductor device and a manufacturing method thereof.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
液晶表示装置の表示パネルに用いられる薄膜トランジスタの半導体部分は、通常、アモルファスシリコン(a−Si)や多結晶シリコン(poly−Si)から形成されている。 Semiconductor portions of the thin film transistor used for a display panel of a liquid crystal display device is typically formed of amorphous silicon (a-Si) or polycrystalline silicon (poly-Si).
【0003】 [0003]
これらの半導体材料は可視光を吸収するため、光の照射によって半導体中に電子・正孔対が形成され、トランジスタ特性が劣化する。 These semiconductor materials for absorbing visible light, electron-hole pairs are formed in the semiconductor by light irradiation, the transistor characteristics are deteriorated. 具体的には、トランジスタがオフ状態にあるときでも、光の照射によって半導体層のチャネル領域にキャリアが生成され、ソース領域とドレイン領域との間に電流が流れる。 Specifically, even when the transistor is in the off state, carriers are generated in the channel region of the semiconductor layer by light irradiation, the current flows between the source region and the drain region. オフ時のトランジスタを流れる電流は「オフリーク電流」と呼ばれ、この値が大きいと、表示バネルが正常に動作しないという問題がある。 Current flowing through the transistor in the OFF is referred to as "off-leak current", this value is large, there is a problem that the display Bunnell does not work properly. このため、光が半導体層を照射しないように遮光膜のパターンを形成することが行われている。 Therefore, the light forms a pattern of light-shielding film so as not to irradiate the semiconductor layer is performed. しかし、遮光膜のパターンを形成するには、遮光膜の堆積工程やフォトリソグラフィ・エッチング工程が必要になるため、工程が煩雑になる。 However, in order to form a pattern of light-shielding film, since the deposition process and photolithographic etching process of the light-shielding film is required, the process becomes complicated.
【0004】 [0004]
このような問題を解決するため、近年、禁制帯幅(バンドギャップ)が3.4eVと広い直接遷移型の半導体である酸化亜鉛(ZnO)やZnOを主成分とした化合物半導体から形成した透明トランジスタが注目されている。 To solve such a problem, in recent years, transparent transistor bandgap (bandgap) is formed of a compound semiconductor whose main component is zinc oxide (ZnO) or ZnO is 3.4eV and a wide direct transition type semiconductor There has been attracting attention. このような透明トランジスタでは、半導体のバンドギャップが可視光帯域の光エネルギよりも大きく、可視光を吸収しないため、光の照射を受けてもオフリーク電流は増大しないという利点を有し、注目されている。 In such a transparent transistor, the band gap of the semiconductor is greater than the light energy in the visible light band, because it does not absorb visible light, has the advantage that even under irradiation of light leak current does not increase, it is noted there.
【0005】 [0005]
ZnOを半導体層に用いたスタガ型薄膜トランジスタは、例えば、特許文献1に開示されている。 Staggered thin film transistor using ZnO for the semiconductor layer, for example, disclosed in Patent Document 1. 図1を参照しながら、ZnOを半導体層に用いたスタガ型薄膜トランジスタの構成を説明する。 With reference to FIG. 1, the structure of staggered thin film transistor using ZnO for the semiconductor layer.
【0006】 [0006]
図1の薄膜トランジスタは、絶縁性基板1上に形成されたソース電極20aおよびドレイン電極20bと、ソース・ドレイン電極20a、20bに接触するように配置されたZnO層4と、ZnO層4上に積層されたゲート絶縁層5およびゲート電極6とを備えている。 TFT of FIG. 1, a source electrode 20a and drain electrode 20b formed on the insulating substrate 1, the source and drain electrodes 20a, ZnO layer 4 arranged so as to be in contact with 20b, layered on the ZnO layer 4 and a gate insulating layer 5 and the gate electrode 6.
【0007】 [0007]
この薄膜トランジスタは、ZnO層4の下方にソース・ドレイン電極20a、20bを有し、かつ、ZnO層4の上方にゲート電極6を有するスタガ構成を備えている。 This thin film transistor, ZnO layer 4 of the source and drain electrodes 20a downward, have 20b, and has a staggered configuration having a gate electrode 6 above the ZnO layer 4. このようなスタガ型薄膜トランジスタを形成するには、ソース・ドレイン電極材料膜をパターニングする工程と、ZnO膜、ゲート絶縁材料膜、およびゲート電極材料膜の積層体をパターニングする工程とが必要であるが、そのために必要なフォトリソグラフィ工程でのマスクアライメントは最低2回であり、製造コストの削減が期待できる。 To form such a staggered thin film transistor includes a step of patterning the source and drain electrode material film, ZnO film, the gate insulating material film, and a step of patterning the stack of the gate electrode material film is necessary , the mask alignment in the photolithography process required therefor is at least twice, can be expected reduction in manufacturing cost.
【0008】 [0008]
一方、近年の表示パネルの大型化および高精細化に伴って、ソース・ドレイン電極20a、20bやソース電極20aと一体的に形成されるソースバス配線の材料として、電気抵抗がより低い金属を用いることが求められている。 On the other hand, as the size and higher definition in recent years of the display panel, the source and drain electrodes 20a, as the material of the source bus lines formed to 20b and the source electrode 20a and the integral electrical resistance use lower metal it has been demanded. このために、従来から広く用いられているTaなどの高融点金属よりも比抵抗が低いアルミニウム(Al)またはAlを主成分とするAl合金が注目されている。 For this, Al alloy than the high melting point metal such as Ta, which has been widely used is the resistivity as a main component low aluminum (Al) or Al is noted.
【0009】 [0009]
【特許文献1】 [Patent Document 1]
特開2000−150900号公報【0010】 Japanese Unexamined Patent Publication No. 2000-150900 Publication [0010]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかしながら、本発明者の検討によると、図1に示されるスタガ型薄膜トランジスタのソース・ドレイン電極20a、20bのための導電材料としてAlを用いた場合、ソース・ドレイン電極20a、20bとZnO層4との接触部において、ソース・ドレイン電極20a、20bに一部欠落などの欠陥・不良が生じることがわかった。 However, according to the study of the present inventors, the source and drain electrodes 20a of the staggered thin film transistor shown in FIG. 1, the case of using Al as the conductive material for the 20b, the source and drain electrodes 20a, 20b and the ZnO layer 4 in the contact portion, it was found that the source and drain electrodes 20a, defect-defect such as a missing part 20b occurs.
【0011】 [0011]
このよう欠陥・不良は、現像液などの電解質を含んだ溶液や大気中に水分と薄膜トランジスタとが接触することにより発生した。 Such defects or defective, and water and a thin film transistor occurs by contacting the solution or the atmosphere containing electrolyte such as a developer. このため、ソース・ドレイン電極20a、20bとZnO層4との接触部で局部電池反応が生じ、その結果、電蝕反応が進行して断線等の不良を引き起こしてしまうと考えられる。 Therefore, the source and drain electrodes 20a, local cell reaction occurs at the contact portion between 20b and ZnO layer 4, As a result, it is considered that an electrolytic corrosion reaction will cause defects such as disconnection in progress.
【0012】 [0012]
本発明は、上記事情に鑑みてなされたものであり、その目的とするところは、ZnOから半導体層を形成し、かつ、電極・配線材料としてアルミニウム用いた場合でも電蝕による欠陥・不良が生じない半導体装置を提供することにある。 The present invention has been made in view of the above circumstances, and has as its object the formation of the semiconductor layer from ZnO, and even electrodeposition when using aluminum corrosion defects, defects caused by the electrodes and wiring materials to provide a no semiconductor device.
【0013】 [0013]
【課題を解決するための手段】 In order to solve the problems]
本発明による半導体装置は、基板と、前記基板に支持されている少なくとも1つの電極と、前記電極の上面の少なくとも一部に接触する半導体層とを備えた半導体装置であって、前記電極は、第1導電材料から形成された第1導電層と、前記第1導電層の上面と前記半導体層との間に配置され、前記第1導電材料とは異なる第2導電材料から形成された第2導電層と、前記半導体層の下面と前記第1導電層の側面との間に位置する絶縁性保護層とを有している。 The semiconductor device according to the present invention is a semiconductor device including the a substrate, at least one electrode is supported on said substrate, and a semiconductor layer in contact with at least a portion of the upper surface of the electrode, the electrode, a first conductive layer formed of a first conductive material, wherein the upper surface of the first conductive layer disposed between the semiconductor layer, a second formed of a different second conductive material than the first conductive material a conductive layer, and an insulating protective layer located between the side surface of the lower surface and the first conductive layer of the semiconductor layer.
【0014】 [0014]
ある好ましい実施形態において、前記半導体層は、バンドギャップが3eV以上の半導体から形成されている。 In a preferred embodiment, the semiconductor layer, the band gap is formed from the above semiconductor 3 eV.
【0015】 [0015]
ある好ましい実施形態において、前記半導体層は、ZnOまたはZnOを主成分とした化合物半導体から形成されている。 In a preferred embodiment, the semiconductor layer is formed of a compound semiconductor whose main component is ZnO or ZnO.
【0016】 [0016]
ある好ましい実施形態において、前記第1導電体材料は、主としてアルミニウムを含む。 In a preferred embodiment, the first conductive material comprises predominantly aluminum.
【0017】 [0017]
ある好ましい実施形態において、前記絶縁性保護層は、前記第1導電材料の酸化物および/または窒化物から形成されている。 In a preferred embodiment, the insulating protective layer is formed from an oxide and / or nitride of the first conductive material.
【0018】 [0018]
ある好ましい実施形態において、前記第1導電材料の比抵抗は、前記第2導電材料の比抵抗よりも低く、前記第2導電材料は前記第1導電材料に比べて局部電池反応による腐食が生じにくい。 In certain preferred embodiments, the resistivity of the first conductive material, the second conductive material lower than the resistivity of the second conductive material is less likely to occur corrosion due to a local cell reaction as compared to the first conductive material .
【0019】 [0019]
ある好ましい実施形態において、前記第2導電材料と前記半導体層との間でオーミック性を有する接触が生じている。 In certain preferred embodiments, the contact occurs with an ohmic resistance between said second conductive material and the semiconductor layer.
【0020】 [0020]
ある好ましい実施形態において、前記第2導電材料は、第IV族、第V族、もしくは第VI族の金属またはこれらの金属の窒化物である。 In certain preferred embodiments, the second conductive material, IV, V, or a Group VI metal or a nitride of these metals.
【0021】 [0021]
ある好ましい実施形態において、前記金属は、Ti、Ta、およびMoからなる群から選択された少なくとも1つの金属である。 In certain preferred embodiments, the metal is at least one metal selected Ti, Ta, and from the group consisting of Mo.
【0022】 [0022]
ある好ましい実施形態において、前記少なくとも1つの電極は、前記基板上において離れた位置に形成された2つの電極を含んでいる。 In certain preferred embodiments, the at least one electrode includes two electrodes formed at a position apart in the substrate.
【0023】 [0023]
ある好ましい実施形態において、前記2つの電極の各々における前記絶縁性保護層は、前記基板上において連続している。 In a preferred embodiment, the insulating protective layer in each of the two electrodes is continuous in the substrate.
【0024】 [0024]
ある好ましい実施形態において、前記絶縁性保護層は、可視光を透過する材料から形成されている。 In a preferred embodiment, the insulating protective layer is formed from a material which transmits visible light.
【0025】 [0025]
ある好ましい実施形態において、前記絶縁性保護層は、SiO 2 、Al 23 、Ta 23 、およびSiNx(0≦x<3)からなる群から選択された少なくとも1つの絶縁材料から形成されている。 In a preferred embodiment, the insulating protective layer is formed from at least one insulating material selected from SiO 2, Al 2 O 3, Ta 2 O 3, and the group consisting of SiNx (0 ≦ x <3) ing.
【0026】 [0026]
ある好ましい実施形態において、前記半導体層の上面側に配置され、前記半導体層と接触する第2の電極を更に有している。 In a preferred embodiment, is disposed on the upper surface side of the semiconductor layer further includes a second electrode in contact with the semiconductor layer.
【0027】 [0027]
ある好ましい実施形態において、前記2つの電極は、それぞれ、ソース電極およびドレイン電極であり、前記第2の電極は、前記半導体層の上面に形成されたゲート絶縁膜を介して前記半導体層に対向するゲート電極である。 In a preferred embodiment, the two electrodes, respectively, a source electrode and a drain electrode, the second electrode is opposed to the semiconductor layer via a gate insulating film formed on the upper surface of said semiconductor layer a gate electrode.
【0028】 [0028]
本発明の表示装置は、上記のいずれかに記載の半導体装置を備えている。 Display device of the present invention includes a semiconductor device according to any of the above.
【0029】 [0029]
本発明による半導体装置の製造方法は、少なくとも1つの電極を基板上に形成する工程と、前記電極を覆うように半導体層を形成する工程とを含む半導体装置の製造方法であって、前記電極を形成する工程は、第1導電材料の膜を形成する工程と、前記第1導電材料以外の第2導電材料の膜を前記第1導電層材料の膜の上に堆積する工程と、前記2つの膜をパターニングすることにより、前記第1導電材料から形成された第1導電層と、前記第2導電材料から形成された第2導電層とを含む積層構造を形成する工程と、前記第1導電層の側面の少なくとも一部を覆う絶縁性保護層を形成する工程とを含む。 The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device comprising forming at least one electrode on a substrate, and forming a semiconductor layer to cover the electrodes, the electrode forming includes the steps of forming a film of a first conductive material, depositing a layer of a second conductive material other than the first conductive material on the membrane of the first conductive layer material, said two by patterning the film, a first conductive layer formed from the first conductive material to form a laminated structure including a second conductive layer formed from the second conductive material, the first conductive and forming at least a portion of the cover insulating protective layer side of the layer.
【0030】 [0030]
ある好ましい実施形態において、前記2つの膜をパターニングする工程は、前記2つの膜の上にレジストマスクを堆積する工程と、前記2つの膜のうちレジストマスクで覆われてない部分をエッチングする工程とを含む。 In certain preferred embodiments, the step of patterning the two film, and etching the steps of depositing a resist mask on the two films, the portion not covered with the resist mask of the two films including.
【0031】 [0031]
ある好ましい実施形態において、前記絶縁性保護層を形成する工程は、前記第1導電層の側面を酸化および/または窒素する工程を含む。 In certain preferred embodiments, the step of forming the insulating protective layer comprises a step of oxidizing and / or nitrogen sides of the first conductive layer.
【0032】 [0032]
ある好ましい実施形態において、前記絶縁性保護層を形成する工程は、前記レジストマスクを除去する前に、絶縁膜を基板上に堆積する工程と、前記レジストマスクを除去することにより、前記絶縁膜の不要部分のリフトオフを行い、前記絶縁膜の一部を前記第1導電層の側面に残置する工程とを含む。 In another preferred embodiment, the step of forming an insulating protective layer, before removing the resist mask, depositing an insulating film on a substrate, by removing the resist mask, the insulating film perform lift-off of the unnecessary portions, and a step of leaving a portion of the insulating film on the side surface of the first conductive layer.
【0033】 [0033]
本発明による他の半導体装置は、基板と、前記基板に支持されている少なくとも1つの電極と、前記電極の上面の少なくとも一部に接触する半導体層とを備えた半導体装置であって、前記半導体層は、ZnOまたはZnOを主成分とした化合物半導体から形成されており、前記電極は、アルミニウムを主成分とする第1導電材料から形成された第1導電層と、前記第1導電層の上面と前記半導体層との間に配置され、前記第1導電材料とは異なる第2導電材料から形成された第2導電層とを有しており、前記第2導電材料は、前記第1導電材料に比べて局部電池反応による腐食が生じにくい。 Another semiconductor device according to the present invention is a semiconductor device including the a substrate, at least one electrode is supported on said substrate, and a semiconductor layer in contact with at least a portion of the upper surface of said electrode, said semiconductor layer is formed of ZnO or ZnO of a compound semiconductor as a main component, the electrode includes a first conductive layer formed of a first conductive material mainly composed of aluminum, the upper surface of the first conductive layer and the disposed between the semiconductor layer, wherein the first conductive material and a second conductive layer formed from a different second conductive material, the second conductive material, the first conductive material corrosion due to a local cell reaction is unlikely to occur compared to.
【0034】 [0034]
ある好ましい実施形態において、前記第2導電層は、前記第1導電層の上面および側面の両方を覆っている。 In certain preferred embodiments, the second conductive layer covers both the top and side surfaces of the first conductive layer.
【0035】 [0035]
ある好ましい実施形態において、前記少なくとも1つの電極は、前記基板上において離れた位置に形成された2つの電極を含んでおり、前記2つの電極の各々における前記第2導電層は、前記基板上において電気的に分離されている。 In certain preferred embodiments, the at least one electrode includes a two electrodes formed at separate positions in the substrate, the second conductive layer in each of the two electrodes in the substrate They are electrically separated.
【0036】 [0036]
ある好ましい実施形態において、前記第2導電材料と前記半導体層との間でオーミック性を有する接触が生じている。 In certain preferred embodiments, the contact occurs with an ohmic resistance between said second conductive material and the semiconductor layer.
【0037】 [0037]
ある好ましい実施形態において、前記第2導電材料は、第IV族、第V族、もしくは第VI族の金属またはこれらの金属の窒化物である。 In certain preferred embodiments, the second conductive material, IV, V, or a Group VI metal or a nitride of these metals.
【0038】 [0038]
ある好ましい実施形態において、前記金属は、Ti、Ta、およびMoからなる群から選択された少なくとも1つの金属である。 In certain preferred embodiments, the metal is at least one metal selected Ti, Ta, and from the group consisting of Mo.
【0039】 [0039]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下、図面を参照しながら、本発明の好ましい実施形態を説明する。 Hereinafter, with reference to the accompanying drawings, illustrating a preferred embodiment of the present invention.
【0040】 [0040]
(実施形態1) (Embodiment 1)
まず、図2を参照しながら、本発明による半導体装置の第1の実施形態の構成を説明する。 First, referring to FIG. 2, illustrating the configuration of a first embodiment of a semiconductor device according to the present invention. 本実施形態の半導体装置は、液晶表示装置などの表示パネルに好適に用いられるアクティブマトリクス基板である。 The semiconductor device of the present embodiment is an active matrix substrate is suitably used for a display panel such as a liquid crystal display device.
【0041】 [0041]
なお、本明細書における「半導体装置」の用語は、基板上に形成された薄膜トランジスタなどの半導体素子そのものを指し示すのではなく、薄膜トランジスタなどの半導体素子が形成された基板を備える構造物、または当該構造物を備えた装置を広く指し示すものとする。 Incidentally, the term "semiconductor device" in this specification does not indicate the semiconductor device itself such as a thin film transistor formed on a substrate, the structure comprising a substrate on which semiconductor elements such as thin film transistors are formed or the structure, It shall indicate broad a device with an object. また、基板上に形成される半導体素子は、薄膜トランジスタなどの三端子素子に限定されず、発光素子やスイッチング素子として機能するダイオードをも含むものとする。 Further, the semiconductor device formed on a substrate is not limited to the three-terminal element such as a thin film transistor, the category includes a diode functioning as a light-emitting element and a switching element.
【0042】 [0042]
以下、簡単のため、複数の薄膜トランジスタが行および列からなるマトリクス状に配列されたアクティブマトリクス基板上の単一の薄膜トランジスタに着目して本実施形態を詳述する。 Hereinafter, for simplicity, a plurality of thin film transistors are described in detail to the present exemplary embodiment focuses on a single thin film transistor on the active matrix substrate arranged in a matrix of rows and columns. 図面には、単一の薄膜トランジスタのみを記載しているが、実際の基板上には複数の薄膜トランジスタが形成されている。 The drawings and are described only a single thin film transistor, the actual substrate has a plurality of thin film transistors are formed.
【0043】 [0043]
本実施形態の半導体装置は、図2に示すように、基板1と、基板1に支持されたソース電極20aおよびドレイン電極20bと、ソース・ドレイン電極20a、20bの各々の上面の少なくとも一部に接触する半導体層4とを備えている。 The semiconductor device of the present embodiment, as shown in FIG. 2, a substrate 1, a source electrode 20a and drain electrode 20b, which is supported on the substrate 1, source and drain electrodes 20a, at least a portion of each of the upper surface of 20b and a semiconductor layer 4 in contact. 半導体層4の上には、ゲート絶縁膜5およびゲート電極6がこの順序で積層されており、薄膜トランジスタか構成されている。 On the semiconductor layer 4, the gate insulating film 5 and gate electrode 6 are laminated in this order, and is configured or TFT. なお、図示してはいないが、現実のアクティブマトリクス基板には、上記の薄膜トランジスタに接続されたソースバスライン、ゲートバスライン、および画素電極が形成されており、また、これらを覆う絶縁膜や配向膜が堆積されている。 Although not shown, in reality the active matrix substrate, said thin film transistors connected source bus lines are gate bus lines, and pixel electrodes are formed, The insulating film and the orientation covering them film is deposited.
【0044】 [0044]
本実施形態における基板1は、液晶表示装置用の無アルカリガラス(コーニング社製1737ガラス)から形成されている。 Substrate 1 in this embodiment is formed of alkali-free glass for liquid crystal display device (Corning 1737 glass). 基板1は、ガラスやプラスチックなどの透明材料から形成することが好ましいが、用途によっては、必ずしも透明な絶縁性材料から形成される必要はない。 Substrate 1 is preferably formed from a transparent material such as glass or plastic, depending on the application need not necessarily be formed of a transparent insulating material.
【0045】 [0045]
半導体層4は、ZnOから形成されている。 The semiconductor layer 4 is formed of ZnO. 前述したように、ZnOは、バンドギャップが3eVを超える化合物半導体であり、可視光を透過する。 As mentioned above, ZnO has a band gap of a compound semiconductor of more than 3 eV, it transmits visible light. 透過型の液晶表示装置に用いるアクティブマトリクス基板は、背面側に可視光の光源(バックライト)を配置するため、図示されている薄膜トランジスタもバックライトからの光で照射されることになる。 The active matrix substrate used in a transmission type liquid crystal display device, for placing a visible light source (backlight) on the back side will be also irradiated thin film transistor depicted with light from the backlight. 従来のようにシリコンを用いて形成した薄膜トランジスタの場合、バックライトからの光が薄膜トランジスタを照射しないように遮光膜を適切に配置する必要があるが、本実施形態では、そのような必要はない。 In the case of a thin film transistor formed using silicon as in the prior art, it is necessary to properly position the light shielding film so that light is not irradiated thin film transistors from a backlight, but in the present embodiment, such need not be.
【0046】 [0046]
ゲート絶縁層5は、SiO 2から形成され、ゲート電極6は、Alから形成されている。 The gate insulating layer 5 is formed of SiO 2, a gate electrode 6 is formed from Al. これらゲート絶縁層5およびゲート電極6の材料は、ここに示したものに限定されず、適宜最適な材料を選択して、用いることができる。 Materials of these gate insulating layer 5 and the gate electrode 6 is not limited to those shown here, by selecting the most suitable materials can be used.
【0047】 [0047]
ソース・ドレイン電極20a、20bの各々は、アルミニウム(Al)から形成された第1導電層2と、チタニウム(Ti)から形成された第2導電層3と、第1導電層2および第2導電層3の側面を覆う絶縁性保護層7とを有している。 Source and drain electrodes 20a, 20b each comprises a first conductive layer 2 formed of aluminum (Al), and the second conductive layer 3 formed of titanium (Ti), first conductive layer 2 and the second conductive and an insulating protective layer 7 covering the side surfaces of the layer 3. 言い換えると、第1導電層2の上面と半導体層4との間には第2導電層3が配置され、第1導電層2の側面と半導体層4の下面との間には絶縁性保護層7が配置されている。 In other words, the insulating protective layer between the lower surface of the second conductive layer 3 is arranged, of the first conductive layer 2 side and the semiconductor layer 4 is formed between the upper and the semiconductor layer 4 of the first conductive layer 2 7 is disposed.
【0048】 [0048]
本実施形態では、このように第1導電層2と半導体層4との直接的な接触が避けられているため、第1導電層2にAlを用い、半導体層4にZnOを用いた場合でも、局部電池反応による電蝕が生じないため、ソース・ドレイン電極20a、20bの断線などの欠陥・不良の発生を防止することができる。 In the present embodiment, since the direct contact is avoided between the way the first conductive layer 2 and the semiconductor layer 4, with Al on the first conductive layer 2, even in the case of using ZnO for the semiconductor layer 4 since the galvanic corrosion due to local cell reaction does not occur, it is possible to prevent the occurrence of defects, defects such as source and drain electrodes 20a, 20b of the disconnection.
【0049】 [0049]
第2導電層3の材料(第2導電材料)としては、第1導電層2の材料(第1導電材料)に比べて、半導体層4の間で局部電池反応による腐食が生じにくい材料を用いることが好ましく、また、半導体層4との間でオーミック性を有する接触が生じる材料を選択することが好ましい。 As the second conductive layer 3 of the material (second conductive material), as compared to the first conductive layer 2 material (first conductive material), using a hardly occurs Corrosion due to local cell reaction between the semiconductor layer 4 it is preferable, also, it is preferable to select a material which contact occurs with an ohmic resistance between the semiconductor layer 4. 半導体層4の材料としてZnOやZnOを主成分とする化合物半導体を用いる場合、第2導電材料としては、第IV族、第V族、もしくは第IV族の金属またはこれらの金属の窒化物を用いることが可能であり、これらの金属は、具体的にはTi、Ta、および/またはMoである。 When using a compound semiconductor mainly composed of ZnO or ZnO as the material of the semiconductor layer 4, as the second conductive material, IV, V, or Group IV metal or nitride of these metals using it is possible, these metals, specifically Ti, Ta, and / or Mo.
【0050】 [0050]
半導体層4の材料として、ZnOやZnOを主成分とする化合物半導体以外の半導体を用いる場合は、その半導体との間で電蝕が生じにくく、かつ、オーミック接触の可能な材料を適宜選択すればよい。 As the material of the semiconductor layer 4, the case of using a semiconductor other than the compound semiconductor mainly composed of ZnO or ZnO is less likely to occur electrolytic corrosion between that semiconductor, and be appropriately selected material capable of ohmic contact good.
【0051】 [0051]
第2導電層3の厚さは、第1導電層2と半導体層4との間にあって電蝕防止効果を発揮し得る大きさを有しておればよい。 The thickness of the second conductive layer 3 may be I have a size capable of exhibiting electrolytic corrosion prevention effect there between the first conductive layer 2 and the semiconductor layer 4. また、第2導電層3を厚く形成しすぎると、第2導電材料の堆積に要する工程時間が長くなるため、好ましくない。 Also, if too thick forming a second conductive layer 3, since the process time required for the deposition of the second conductive material becomes longer, which is not preferable. 第2導電層3の厚さは、例えば30nm以上200nm以下の範囲に設定され得る。 The thickness of the second conductive layer 3 may be set, for example, in the range of 30nm or more 200nm or less.
【0052】 [0052]
第1導電層2の材料(第1導電材料)は、比抵抗が低いという観点から純度の高いアルミニウムを使用しているが、この代わりに添加物が付与されたアルミニウム合金などを用いても良い。 The first conductive layer 2 of the material (first conductive material), although the specific resistance is using aluminum high in terms of purity of low, or the like may be used aluminum alloy additions has been granted to this place . アルミニウムには、温度の高いプロセスを経ると、ヒロックが成長しやすいという問題があるが、本実施形態のように、上面を第2導電層3で覆い、かつ側面を絶縁性保護層7で覆うことにより、ヒロックの発生・成長を抑制する効果も得られる。 The aluminum, when going through the high temperature process, there is a problem that hillock is likely to grow, as in this embodiment, covering the upper surface in the second conductive layer 3, and covers the side surface with an insulating protective layer 7 by the effect of suppressing the occurrence and growth of hillocks is also obtained. 配線抵抗をより低くするためには、第1導電層2を厚く形成することが好ましく、液晶表示装置が大画面化すると、今までよりも第1導電層2を厚く形成することが必要になる。 To the wiring resistance lower, it is preferred to form a thick first conductive layer 2, the liquid crystal display device is large screen, it is necessary to form a thick first conductive layer 2 than ever . 第1導電層2が厚くなるほど、第2導電層2の側面から成長するヒロックによる短絡などが問題になり得るが、本実施形態のように側面が絶縁性保護層7で覆われていると、そのようなヒロックを効果的に抑制できるという利点が得られる。 As the first conductive layer 2 becomes thicker, but such short-circuiting due to hillock grown from the second side surface of the conductive layer 2 can be a problem, if side as in this embodiment is covered with an insulating protective layer 7, advantage that such hillocks can be effectively suppressed can be obtained.
【0053】 [0053]
第1導電層2の好ましい厚さ範囲は、例えば50nm以上700nm以下である。 The preferred thickness range of the first conductive layer 2 is, for example, 50nm or more 700nm or less. 第1導電層2が50nmよりも薄くなると、抵抗低減効果がほんど得られないから好ましくなく、また、第1導電層2が700nmを超えて厚くなると、表面段差が大きくなりすぎるため、好ましくない。 When the first conductive layer 2 is thinner than 50 nm, undesirably because resistance reducing effect can not be obtained Mainland, also, when the first conductive layer 2 is increased beyond 700 nm, since the surface level difference is too large, unfavorably .
【0054】 [0054]
絶縁性保護層7の厚さは、電蝕防止効果を示すに充分な絶縁性を示す大きさを持つことが好ましい。 The thickness of the insulating protective layer 7 preferably has a size that exhibit sufficient insulating properties are shown galvanic corrosion prevention effect. 絶縁性保護層7を厚く形成しすぎると、そのために必要な工程時間が長くなるため、好ましくない。 If too thick form an insulating protective layer 7, since the process time required therefor becomes long, which is not preferable. このため、絶縁性保護層7の厚さは、例えば5nm以上50nm以下の範囲に設定され得る。 Therefore, the thickness of the insulating protective layer 7 may be set in the range of, for example 5nm or more 50nm or less.
【0055】 [0055]
本実施形態では、絶縁性保護層7を第1導電層2の側面に選択的に形成した絶縁膜から形成している。 In the present embodiment, it is formed from selectively forming an insulating film insulating protective layer 7 on the side surface of the first conductive layer 2. このため、特別のパターニング工程が不要である。 For this reason, special patterning step is not required.
【0056】 [0056]
以下、図2の薄膜トランジスタの製造方法を説明する。 Hereinafter, a manufacturing method of a thin film transistor FIG.
【0057】 [0057]
ます、DCスパッタ成膜方法などの薄膜堆積技術を用いて、50〜700nmの範囲から選択された厚さ(例えば100nm)を有するAl膜を基板1上に堆積した後、Al膜上に30〜200nmの範囲から選択された厚さ(例えば50nm)を有するTi膜を堆積する。 Masu, using a thin film deposition technique such as DC sputtering method, after deposition thickness selected from a range of 50~700nm an Al film having a (e.g. 100 nm) on the substrate 1, 30 on the Al film depositing a Ti film having a thickness selected from the range of 200nm (for example, 50 nm).
【0058】 [0058]
次に、図3(a)に示すように、上記積層金属膜(Al/Ti積層膜)上に、ソース・ドレイン電極およびソース・ドレイン電極20a、20bと一体的に形成される配線の形状を規定するレジストマスク8を形成する。 Next, as shown in FIG. 3 (a), on the laminated metal film (Al / Ti layered film), a source-drain electrode and the source and drain electrodes 20a, 20b and the shape of the integrally formed a wiring forming a resist mask 8 defining. レジストマスク8は、公知のフォトリソグラフィ技術によってフォトレジスト材料を露光・現像することによって作製される。 Resist mask 8 is produced by exposing and developing the photoresist material by a known photolithography technique.
【0059】 [0059]
次に、上記のAl/Ti積層膜のうちレジストマスク8に覆われていない部分をエッチングすることにより、図3(a)に示すような第1導電層2および第2導電層3のTi/Al積層体を作製する。 Next, by etching the portion not covered with the resist mask 8 of the above Al / Ti layered film, the first conductive layer 2 and the second conductive layer 3 as shown in FIG. 3 (a) Ti / to produce an Al laminate. このエッチングは、好ましくは、プラズマを用いた異方性の高いドライエッチング技術で行う。 This etching is preferably carried out at a highly anisotropic dry etching technique using plasma.
【0060】 [0060]
次に、Ti/Al積層体の側面に対して絶縁性保護層7を形成する。 Next, an insulating protective layer 7 with respect to the side surface of the Ti / Al laminate. 本実施形態では、酸素プラズマ処理により、絶縁性保護層7を形成する。 In the present embodiment, the oxygen plasma treatment to form an insulating protective layer 7. 具体的には、まず、基板1をプラズマ処理装置のチャンバー内に挿入し、チャンバー内の圧力が400〜1000mTorrになるよう酸素ガスを導入する。 Specifically, first, insert the substrate 1 into a chamber of a plasma processing apparatus, the pressure in the chamber to introduce the oxygen gas so that the 400~1000MTorr. 次に、基板1が置かれる下部電極と、それに対向して配置されてい上部電極との間に例えば13.6MHzの高周波電界を印加する。 Then, applying a lower electrode substrate 1 is placed, it a high-frequency electric field, for example, 13.6MHz between the counter and are disposed upper electrode. 投入する電力は、例えば500〜1000Wの範囲に設定することができる。 Power applied can be set to, for example, a range of 500~1000W. プラズマ処理装置における上下の電極間に発生した酸素プラズマにより、Ti/Al積層体のうちレジストマスク8で覆われていない領域(側面部)が酸化され、その部分に厚さ5〜50nm(好ましくは10〜30nm)の絶縁性酸化物が成長し、それによって絶縁性保護層7が形成される。 By oxygen plasma generated between the upper and lower electrodes in the plasma processing apparatus, Ti / Al region not covered with the resist mask 8 of the laminate (side surface portion) is oxidized, the thickness 5~50nm to that part (preferably an insulating oxide is grown in the 10 to 30 nm), whereby the insulating protective layer 7 is formed. 本実施形態における絶縁性保護層7は、Al 23部分およびTiO x部分から構成されている。 Insulating protective layer 7 in this embodiment is made of Al 2 O 3 portions, and TiO x moiety. より詳細には、絶縁性保護層7のうちのAl 23部分は第1導電層2の側面を覆い、TiO x部分は第2導電層3の側面を覆っている。 More specifically, Al 2 O 3 portion of the insulating protective layer 7 covers the side surface of the first conductive layer 2, TiO x portion covers the side surface of the second conductive layer 3. AlとTiとでは酸化レートが異なるため、絶縁性保護層7のうちのAl 23部分とTiO x部分とでは厚さが異なり得る。 The oxidation rate is different between Al and Ti, may differ in thickness between the Al 2 O 3 portions and TiO x portion of the insulating protective layer 7.
【0061】 [0061]
絶縁性保護層7を窒化膜から形成することも可能である。 It is also possible to form the insulating protective layer 7 of a nitride film. プラズマ処理装置のチャンバー内に窒素を導入し、窒素プラズマでTi/Al積層体の露出した側面が窒化すればよい。 Nitrogen was introduced into the chamber of a plasma processing apparatus, the exposed side surfaces of the Ti / Al laminate nitrogen plasma may be nitride. Ti/Al積層体の側面を窒化する場合、絶縁性保護層7は、第1導電層2の側面に形成されるAlNから構成されることになる。 When nitriding the side surfaces of the Ti / Al laminated body, an insulating protective layer 7, will be composed of AlN is formed on the side surface of the first conductive layer 2. 第2導電層3の側面にはTiNが形成されるが、TiNは導電性を有するため、絶縁性保護層7としては機能しない。 While the side surface of the second conductive layer 3 TiN is formed, TiN since having conductivity, does not function as an insulating protective layer 7.
【0062】 [0062]
本実施形態では、プラズマを用いた酸化によって第1導電層2の側面に酸化物を形成したが、陽極酸化法によって、数十nm程度の酸化物を形成しても良い。 In the present embodiment has formed the oxide on the sides of the first conductive layer 2 by oxidation using plasma, by anodic oxidation, it may be formed of an oxide of several tens of nm. 陽極酸化は、化成液中に基板1を浸し、70〜100Vの化成電圧を印加することによって行うことができる。 Anodization, immersing the substrate 1 in the chemical conversion solution, can be carried out by applying a forming voltage of 70~100V. Alの陽極酸化を行う場合、化成液としては、エチレングリコールまたはプロピレングリコールで希釈した酒石酸(PH:7程度)を用いることが好ましい。 When performing anodic oxidation of Al, as the chemical conversion solution, tartaric acid diluted in ethylene glycol or propylene glycol (PH: about 7) is preferably used. このように、Alの陽極酸化にとって最適な条件を採用すると、Tiなどからなる第2導電層3の側面には陽極酸化膜が形成されにくくなる。 Thus, when employing the optimum conditions for the anodic oxidation of Al, the anodic oxide film is less likely to be formed on the side surface of the second conductive layer 3 made of Ti. 化成電圧が高くなりにくいため、ソース・ドレイン電極20a、20bにおける第1導電層2の側面に形成されるAl 23の成長レートも小さい。 Since formation voltage hardly increases, growth rate of Al 2 O 3 formed on the side surfaces of the source and drain electrodes 20a, first conductive layer in 20b 2 is also small. しかし、Al 23の厚さは数十nm程度もあれば、電蝕反応を抑制する効果は充分に発揮される。 However, if it is approximately several tens of nm is the thickness of the Al 2 O 3, the effect of suppressing the electric erosion reaction is sufficiently exhibited. また、第2導電層3の側面は酸化膜によって覆われている必要はないため、Tiの陽極酸化膜を形成できなくとも問題ない。 The side surface of the second conductive layer 3 because need not covered by the oxide film, no problem even impossible to form an anodic oxide film of Ti.
【0063】 [0063]
次に、CVD法やスパッタ法などの薄膜堆積技術により、ZnO膜(厚さ:例えば100nm)およびSiO 2膜(厚さ:例えば200nm)を基板1上に連続して堆積した後、スパッタ法により、Al膜(厚さ:例えば100nm)をSiO 2膜上に堆積する。 Then, by a thin film deposition technique such as CVD or sputtering, ZnO film (thickness: for example 100 nm) and SiO 2 film (thickness: for example 200 nm) and was continuously deposited on the substrate 1, by sputtering , Al film: depositing (thickness e.g. 100 nm) on the SiO 2 film. ZnO膜の堆積にスパッタ法を用いる場合、好ましくは、ZnOの焼結ターゲットを用い、基板温度を例えば250℃に保持しながら、ArおよびO 2の混合ガス雰囲気中(ガス流量はAr:O 2 =2:1)でZnOを堆積することができる。 When using the sputtering deposition of the ZnO film, preferably using a sintered target of ZnO, while maintaining the substrate temperature for example to 250 ° C., a mixed gas atmosphere of Ar and O 2 (gas flow rate Ar: O 2 = 2: 1) can be deposited ZnO with. この後、必要に応じて熱処理を行ってもよい。 After this, heat treatment may be performed if necessary.
【0064】 [0064]
次に、フォトリソグラフィ技術により、ゲート電極・配線のパターンを規定するレジストマスクを形成し、Al/SiO 2 /ZnO積層膜のうちレジストマスクで覆われてない部分を連続的にエッチングする。 Next, by photolithography, a resist mask defining the pattern of the gate electrode and wiring, continuously etching a portion not covered with the resist mask of the Al / SiO 2 / ZnO laminate film. このエッチングは、好ましくは、プラズマを用いた異方性の高いドライエッチング方法などを用いて実行する。 This etching is preferably performed by using a highly anisotropic dry etching method using plasma. この後、剥離洗浄工程を行い、レジストマスクを除去する。 Thereafter, disbonds washing step, the resist mask is removed. こうして、図2に示すように、半導体層4、ゲート絶縁膜5、およびゲート電極6を形成することができる。 Thus, as shown in FIG. 2, it is possible to form the semiconductor layer 4, the gate insulating film 5 and gate electrode 6,.
【0065】 [0065]
本実施形態の方法によれば、半導体層4、ゲート絶縁膜5、およびゲート電極6が同一の平面レイアウトを有しており、ゲート電極6の下方に半導体層4が存在している。 According to the method of the present embodiment, the semiconductor layer 4, the gate insulating film 5, and the gate electrode 6 has the same planar layout, the semiconductor layer 4 is present below the gate electrode 6. なお、トランジスタ毎に半導体層4を孤立させる場合、ゲート絶縁膜5およびゲート電極6のため膜を堆積する前に、半導体膜をパターニングしてアイランド状の半導体4を得てもよい。 In the case to isolate the semiconductor layer 4 for each transistor, before depositing the film for the gate insulating film 5 and gate electrode 6 may be obtained island-shaped semiconductor 4 by patterning the semiconductor film.
【0066】 [0066]
このようにして作製されたスタガ型薄膜トランジスタでは、AlとZnOとの接触が完全に避けることができるため、AlとZnOと間で電蝕反応が生じず、配線不良の発生を防止することができる。 In such staggered thin film transistor manufactured in the, the contact between the Al and ZnO can be avoided completely, does not occur electrolytic corrosion reaction between Al and ZnO, it is possible to prevent the occurrence of defective wiring .
【0067】 [0067]
(実施形態2) (Embodiment 2)
以下、図4を参照しながら、本発明による半導体装置の第2の実施形態を説明する。 Hereinafter, with reference to FIG. 4, illustrating a second embodiment of a semiconductor device according to the present invention.
【0068】 [0068]
本実施形態の半導体装置と、実施形態1における半導体装置との相違点は、ソース・ドレイン電極20a、20bの構成にあり、それ以外の点では同様であるため、以下、ソース・ドレイン電極20a、20bの構成およびその作製方法を詳しく説明する。 Differences of the semiconductor device of this embodiment, a semiconductor device of Embodiment 1, since in the configuration of the source and drain electrodes 20a, 20b, is similar in the other, hereinafter, the source and drain electrodes 20a, 20b will be described in detail a structure and a manufacturing method.
【0069】 [0069]
本実施形態におけるソース・ドレイン電極20a、20bは、図4に示すように、それぞれ。 Source and drain electrodes 20a in this embodiment, 20b, as shown in FIG. 4, respectively. Alから形成された第1導電層2と、Tiから形成された第2導電層3と、第1導電層2および第2導電層3の側面および基板表面を覆う絶縁性保護層7とを有している。 Yes a first conductive layer 2 formed of Al, the second conductive layer 3 formed from Ti, an insulating protective layer 7 covering the side surfaces and the substrate surface of the first conductive layer 2 and the second conductive layer 3 doing. 実施形態1と同様に、第1導電層2の上面と半導体層4との間には第2導電層3が配置され、第1導電層2の側面と半導体層4の下面との間には絶縁性保護層7が配置されているため、アルミニウムから形成された第1導電層2と半導体層4との直接的な接触が避けられている。 Similarly to Embodiment 1, between the upper surface and the semiconductor layer 4 of the first conductive layer 2 is disposed a second electrically conductive layer 3, between the lower surface of the first conductive layer 2 side and a semiconductor layer 4 is since the insulating protective layer 7 is arranged, direct contact between the first conductive layer 2 and the semiconductor layer 4 formed of aluminum is avoided.
【0070】 [0070]
本実施形態で特徴的な点のひとつは、絶縁性保護層7がソース電極20aとドレイン電極20bとの間で連続していることにある。 One characteristic feature in this embodiment is that the insulating protective layer 7 is continuous with the source electrode 20a and the drain electrode 20b.
【0071】 [0071]
以下、図5(a)および(b)を参照しながら、本実施形態の半導体装置の製造方法を説明する。 Hereinafter, with reference to FIGS. 5 (a) and (b), and a method of manufacturing a semiconductor device of the present embodiment.
【0072】 [0072]
まず、絶縁性基板1として、無アルカリガラス基板(コーニング社製1737ガラス)1を用意し、DCスパッタ成膜方法により、基板1上にAl膜(厚さ:例えば100nm)およびTi膜(厚さ:例えば50nm)を連続的に堆積する。 First, as the insulating substrate 1, to prepare a non-alkali glass substrate (Corning 1737 glass) by DC sputtering method, Al film on the substrate 1 (thickness: for example, 100 nm) and the Ti film (thickness : continuously depositing eg 50 nm). 次に、フォトリソグラフィ工程により、ソース・ドレイン電極20a、20bおよびソース・ドレイン電極20a、20bと一体的に連結された配線の形状を規定するレジストマスク8をTi/Al積層膜上に作製する。 Next, by photolithography, to produce the source and drain electrodes 20a, 20b and the source and drain electrodes 20a, 20b and the resist mask 8 a Ti / Al laminated film for defining the shape of the integrally linked wire.
【0073】 [0073]
次に、Ti/Al積層膜のうち、レジストマスク8によって覆われていない部分をエッチングし、ソース・ドレイン電極における第1導電層2および第2導電層3を形成する。 Next, of the Ti / Al laminated film, the portions not covered by the resist mask 8 is etched to form a first conductive layer 2 and the second conductive layer 3 in the source and drain electrodes. このエッチングは、好ましくは、反応性イオンエッチング(RIE)方式によって行う。 This etching is preferably carried out by reactive ion etching (RIE) method. 具体的には、Cl 2ガス(圧力:例えば10mTorr)でエッチング装置のチャンバーを満たし、電極間に5kW程度のRFを印加することによって行うことができる。 Specifically, Cl 2 gas (pressure: e.g. 10 mTorr) satisfies the chamber of the etching apparatus in can be performed by applying a RF of about 5kW between the electrodes.
【0074】 [0074]
以上の工程により、図5(a)に示す構造を得る。 Through the above steps, the structure shown in Figure 5 (a). 次に、レジストマスク8を除去することなく、RFスパッタリング法またはCVD法により、本実施形態ではSiO 2膜(厚さ:30nm程度)を基板1上に堆積する(図5(b))。 Then, without removing the resist mask 8, the RF sputtering method or the CVD method, SiO 2 film in the present embodiment (thickness: about 30 nm) and is deposited on the substrate 1 (Figure 5 (b)). レジストマスク8が基板1上に存在するため、SiO 2膜の堆積温度は200℃以下に設定することが好ましい。 Since the resist mask 8 is present on the substrate 1, it is preferable that the deposition temperature of SiO 2 film is set to 200 ° C. or less.
【0075】 [0075]
この後、レジストマスク8を剥離する工程を行うことにより、レジストマスク8上のSiO 2膜の一部をリフトオフで除去する。 Thereafter, by performing the step of removing the resist mask 8, a portion of the SiO 2 film on the resist mask 8 is removed by lift-off. このリフトオフにより、SiO 2膜のうち図5(b)の点線部よりも上に位置する部分がレジストマスク8とともに除去されるため、ソース・ドレイン電極20a、20bにおける第1および第2導電層2、3の側面および基板1の表面を覆うSiO 2膜が残置されることになる。 The lift-off, since the portion located above the dotted line portion of the inner view of the SiO 2 film 5 (b) is removed together with the resist mask 8, the source and drain electrodes 20a, first and second conductive layers in 20b 2 , so that the SiO 2 film covering the side surfaces and the surface of the substrate 1 of 3 is left. このようにして残ったSiO 2が絶縁性保護7として機能する。 In this way, the remaining SiO 2 functions as an insulating protective 7. このように本実施形態では、基板1の上面のうち、ソース・ドレイン電極20a、20bが形成されていない領域が絶縁性保護層7によって覆われている。 As described above, in this embodiment, the top surface of the substrate 1, source and drain electrodes 20a, the region where 20b is not formed is covered by an insulating protective layer 7.
【0076】 [0076]
次に、CVD法やスパッタ法などの薄膜堆積技術により、ZnO膜(厚さ:例えば100nm)およびSiO 2膜(厚さ:例えば200nm)を基板1上に連続して堆積した後、スパッタ法により、Al膜(厚さ:例えば100nm)をSiO 2膜上に堆積する。 Then, by a thin film deposition technique such as CVD or sputtering, ZnO film (thickness: for example 100 nm) and SiO 2 film (thickness: for example 200 nm) and was continuously deposited on the substrate 1, by sputtering , Al film: depositing (thickness e.g. 100 nm) on the SiO 2 film.
【0077】 [0077]
次に、フォトリソグラフィ技術により、ゲート電極・配線のパターンを規定するレジストマスク(不図示)を形成し、Al/SiO 2 /ZnO積層膜のうちレジストマスクで覆われてない部分を連続的にエッチングする。 Next, by photolithography, a pattern of the gate electrode and wiring resist to form a mask (not shown) which defines the portion which is not covered with the resist mask of the Al / SiO 2 / ZnO laminate film continuously etched to. このエッチングは、好ましくは、プラズマを用いた異方性の高いドライエッチング方法により実行する。 This etching is preferably performed by highly anisotropic dry etching method using plasma. この後、剥離洗浄工程を行い、レジストマスクを除去する。 Thereafter, disbonds washing step, the resist mask is removed. こうして、図4に示す半導体層4、ゲート絶縁膜5、およびゲート電極6を形成することができる。 Thus, it is possible to form the semiconductor layer 4, the gate insulating film 5 and gate electrode 6, as shown in FIG.
【0078】 [0078]
以上の方法で作製されたスタガ型薄膜トランジスタでは、AlとZnOとが接触していないため、AlとZnOとの間に電蝕反応が抑制される。 The staggered thin film transistor manufactured by the above method, for Al and the ZnO is not in contact, electrical corrosion reaction is suppressed between the Al and ZnO.
【0079】 [0079]
本実施形態では、絶縁性保護層7としてSiO 2の膜を用いているが、絶縁性保護層7の材料はSiO 2に限定されない。 In the present embodiment uses a SiO 2 film as an insulating protective layer 7, the material of the insulating protective layer 7 is not limited to SiO 2. 液晶表示装置の場合、絶縁性保護層7の上に画素電極が形成されるため、透過型の表示を行うには、絶縁性保護層7がバックライトからの光を高い効率で透過する性質を持つことが好ましい。 For the liquid crystal display device, since the pixel electrode is formed on the insulating protective layer 7, to perform transmissive display, the property of the insulating protective layer 7 transmits light from the backlight with high efficiency it is preferable to have.
【0080】 [0080]
また、本実施形態における絶縁性保護層7は、ソース電極とドレイン電極との間に連続して存在しているため、その絶縁性が充分に高いことが望まれる。 The insulating protective layer 7 in the present embodiment, since the continued presence between the source electrode and the drain electrode, the insulating property is desired that sufficiently high. 絶縁性保護層7の材料としては、SiNx、Al 23 、Ta 25などの材料が好適である。 As the material of the insulating protective layer 7, SiNx, materials such Al 2 O 3, Ta 2 O 5 is preferred.
【0081】 [0081]
上記の実施形態1および2における薄膜トランジスタを液晶表示装置の画像表示領域におけるスイッチング素子として使用する場合、ソース電極20aはソースバスライン(信号線)と接続され、ドレイン電極20bは、対応する画素電極に接続される。 When using a thin film transistor in Embodiment 1 and 2 above as switching elements in image display region of the liquid crystal display device, the source electrode 20a is connected to the source bus line (signal line), the drain electrode 20b is the corresponding pixel electrode It is connected. 好ましい態様では、ソースバスラインがソース電極20aと一体的に形成され、その場合には、ソースバスラインもソース・ドレイン電極20a、20bと同様の断面構成を有することになる。 In a preferred embodiment, the source bus lines are formed integrally with the source electrode 20a, the case will be the source bus line has a similar cross-sectional configuration and the source and drain electrodes 20a, 20b. 前述のように、アルミニウムはタンタルなどに比べて比抵抗が小さいため、タンタルからソースバスラインを形成した場合に比べてソースバスラインの配線抵抗を大きく低減することができる。 As described above, aluminum is because the specific resistance is smaller than are tantalum, it can greatly reduce the wiring resistance of the source bus lines as compared with the case of forming a source bus line of tantalum.
【0082】 [0082]
なお、上記の各実施形態におけるアクティブマトリクス基板を用いて液晶表示装置を作製する場合、公知の製造方法により、対向基板とアクティブマトリクス基板との間に液晶を封止することによって液晶パネルを形成すればよい。 In the case of manufacturing a liquid crystal display device using an active matrix substrate in the above embodiments, by a known manufacturing method, by forming a liquid crystal panel by sealing a liquid crystal between the counter substrate and the active matrix substrate Bayoi.
【0083】 [0083]
(実施形態3) (Embodiment 3)
次に、図6を参照しながら、本発明による半導体装置の第3の実施形態を説明する。 Next, referring to FIG. 6, illustrating a third embodiment of a semiconductor device according to the present invention.
【0084】 [0084]
本実施形態では、薄膜トランジスタではなく、薄膜ダイオードを基板上に形成している。 In this embodiment, rather than a thin film transistor, the thin film diode are formed on the substrate. 図6に示すように、本実施形態の半導体装置は、基板1と、基板1に支持された第1電極30と、第1電極30の上面の少なくとも一部に接触する半導体層4とを備えている。 As shown in FIG. 6, the semiconductor device of this embodiment includes a substrate 1, a first electrode 30 supported on the substrate 1, and a semiconductor layer 4 in contact with at least a portion of the upper surface of the first electrode 30 ing. 半導体層4の上には、第2電極12が配置されている。 On the semiconductor layer 4, the second electrode 12 is disposed. 第1電極30および第2電極12は、ダイオードのカソードまたはアノードとして機能する。 The first electrode 30 and the second electrode 12 serves as cathode or anode of the diode.
【0085】 [0085]
本実施形態では、半導体層4がZnOから形成されており、半導体層4の下方に位置する第1電極30が第1導電層10および第2導電層11を有し、かつ、側面が絶縁性保護層7によって覆われた構造を有している。 In the present embodiment, the semiconductor layer 4 is formed from ZnO, the first electrode 30 located under the semiconductor layer 4 has a first conductive layer 10 and the second conductive layer 11, and a side insulating properties It has been covered with a protective layer 7 structure.
【0086】 [0086]
以下、図6の半導体装置の製造方法を説明する。 Hereinafter, a method for manufacturing the semiconductor device in FIG.
【0087】 [0087]
まず、絶縁性基板1を用意し、その上に、DCスパッタ成膜方法によってAl膜(厚さ:例えば100nm)およびTi膜(厚さ:例えば50nm)を連続的に堆積する。 First, a dielectric substrate 1, on which, Al film by a DC sputtering method (thickness: for example 100 nm) and the Ti film: continuously depositing (thickness eg 50 nm). 次に、フォトリソグラフィ工程で、第1電極の形状を規定するレジストマスクをTi/Al積層膜上に作製する。 Next, a photolithography process, to form a resist mask defining the shape of the first electrode on the Ti / Al laminated film. Ti/Al積層膜のうち、レジストマスクで覆わていない部分をエッチングし、第1電極30の第1導電層10および第2導電層11を作製する。 Of Ti / Al laminated film, the portion which is not covered with the resist mask is etched to produce the first conductive layer 10 and the second conductive layer 11 of the first electrode 30. ドライエッチングは、反応性イオンエッチング(RIE)方式で行う。 Dry etching is performed by reactive ion etching (RIE) method. 具体的には、Cl 2ガス(圧力:10mTorr)でエッチング装置のチャンバーを満たし、電極間に5kW程度のRFを印加することによって行うことができる。 Specifically, Cl 2 gas (pressure: 10 mTorr) satisfies the chamber of the etching apparatus in can be performed by applying a RF of about 5kW between the electrodes.
【0088】 [0088]
次に、実施形態1と同様の方法で第1導電層10および第2導電像11の側面に絶縁性保護層7を形成する。 Next, an insulating protective layer 7 on the side surface of the first conductive layer 10 and the second Shirubedenzo 11 in the same manner as in Example 1. その後、CVD又はスパッタ法でZnOからなる半導体層(厚さ:100nm)4を堆積し、所定の形状にパターニングする。 Thereafter, the semiconductor layer made of ZnO in CVD or sputtering (thickness: 100 nm) 4 was deposited and patterned into a predetermined shape. その後、ZnOとの間でショットキー接合を形成し得る材料(金、白金、Niなど)からショットキー接合電極(第2電極)12を形成し、図6に示す薄膜ダイオードを得る。 Thereafter, the material capable of forming a Schottky junction with the ZnO (gold, platinum, Ni, etc.) to form a Schottky junction electrode (second electrode) 12, to obtain a thin film diode shown in FIG.
【0089】 [0089]
図6に示す薄膜ダイオードにおいても、AlとZnOとの接触が完全に避けられているため、AlとZnOとの間に電蝕反応が抑制されている。 Also in the thin-film diode shown in FIG. 6, the contact between Al and ZnO is completely avoided, electrolytic corrosion reaction is suppressed between the Al and ZnO.
【0090】 [0090]
(実施形態4) (Embodiment 4)
図7は、実施形態2で説明した方法で絶縁性保護層7を形成した点以外は、上記の実施形態3と同様の方法で作製した薄膜ダイオードの断面構成を示している。 7, except that the formation of the insulating protective layer 7 in the manner described in Embodiment 2, shows a cross-sectional structure of a thin film diode fabricated in the same manner as in Example 3 above. 本実施形態における薄膜ダイオードにおいても、AlとZnOとの接触が完全に避けられているため、AlとZnOとの間に電蝕反応が抑制されている。 Also in the thin-film diode according to this embodiment, since the contact between the Al and ZnO is completely avoided, electrolytic corrosion reaction is suppressed between the Al and ZnO.
【0091】 [0091]
以上説明してきた各実施形態では、いずれも、半導体層をZnOから形成しているが、本発明はこれに限定されない。 In each of the embodiments has been described above, both, although formed from ZnO semiconductor layer, the present invention is not limited thereto. ZnOを主成分とした化合物半導体から半導体層を形成する場合にも本発明の電蝕防止効果を発揮する。 Also exhibits corrosion preventing effect electrodeposition of the present invention in the case of forming a semiconductor layer of a compound semiconductor mainly composed of ZnO. また、半導体層としてシリコン層を用いる場合であっても、アルミニウムとシリコンとが直接接触しないことによる種々の効果を奏することができる。 Further, even in the case of using a silicon layer as the semiconductor layer, it is possible to achieve the various effects caused by the aluminum and silicon are not in direct contact. アルミニウムとシリコンとは相互拡散しやすく、直接接触した状態で高温の熱処理を行うと、アルミニウムがシリコン層の内部に深く拡散してしまうという問題がある。 Easily interdiffusion of aluminum and silicon, when the high temperature heat treatment while being in direct contact, aluminum is a problem that deeply diffused into the silicon layer. また、アルミニウムからは、熱処理によってはヒロックを成長しやすく、配線の短絡などを引き起こす可能性がある。 Further, the aluminum tends to grow the hillocks by heat treatment, which may cause short circuit of the wiring. しかし、上記実施形態の構成によれば、第1導電層の上面および側面をヒロックが発生しにくい材料から形成した層で覆っているため、第1導電層の材料としてアルミニウムのようにヒロックを発生しやすい材料を用いても、配線の短絡を防止することができる。 However, according to the above embodiment, since the covering with a layer of the upper surface and the side surface of the first conductive layer hillocks formed from material hardly occurs, hillocks such as aluminum as the material of the first conductive layer be used easily material, it is possible to prevent short-circuiting of the wiring. アルミニウムを主成分とする導電材料は、比抵抗の低い材料であり、電極・配線として好んで用いられる傾向にあるが、ヒロックを形成しやすいという欠点を有している。 Conductive material containing aluminum as its main component is a low resistivity material, tend to are preferably used as an electrode and wiring, have the disadvantage that tends to form a hillock. 本発明によれば、第2導電層が第1導電層の上面から延びるヒロックの発生を効果的に抑制する一方、絶縁性保護層が第1導電層の側面から延びるヒロックの発生を効果的に抑制する。 According to the present invention, while the second conductive layer to effectively suppress the generation of hillock extending from the top surface of the first conductive layer, generation of hillocks effectively an insulating protective layer extends from the side surface of the first conductive layer suppress. なお、第1導電層の厚さが比較的薄い場合は、第1導電層の側面から延びるヒロックの問題はさほど重要ではないが、今後、第1導電層の抵抗を低下させるために第1導電層を厚くしてゆくと、側面からのヒロックが重要な不良要因となり得る。 Incidentally, when the thickness of the first conductive layer is relatively thin, but not so important hillock problems extending from the side surface of the first conductive layer, next, the first conductive to lower the resistance of the first conductive layer When slide into thicker layers, hillock from the side may be an important failure factor. しかし、上記の各実施形態によれば、第1導電層と半導体層との間に配置した絶縁保護層によってこのような側面ヒロックの発生を効果的に抑制できる。 However, according to the above-described embodiments, it is possible to effectively suppress the occurrence of such side hillocks by an insulating protective layer disposed between the first conductive layer and the semiconductor layer.
【0092】 [0092]
第1導電層の材料(第1導電材料)は、アルミニウムに限定されない。 The material of the first conductive layer (first conductive material) is not limited to aluminum. アルミニウムに他の元素が添加された合金や複合材料であっても、ZnOまたはZnOを主成分とした化合物半導体との間で電蝕反応が生じると考えられるため、本発明の構成を採用することによる効果がある。 Because be an alloy or a composite material other element is added to the aluminum, it is considered by electrolytic corrosion reaction between the compound semiconductor whose main component is ZnO or ZnO occurs, adopting the structure of the present invention there is an effect due.
【0093】 [0093]
更に、アルミニウムを実質的に含有しない導電材料から第1導電層を形成する場合であっても、その側面が絶縁性保護層で覆われているため、少なくとも短絡や断線が生じにくいという効果が得られると考えられる。 Furthermore, since a conductive material not containing aluminum substantially even when forming a first conductive layer, the side surfaces are covered with an insulating protective layer, an effect that at least a short circuit or disconnection does not easily occur resulting It is considered to be. このため、本発明によれば、第1導電層の材料および半導体層の材料の組合せによらず、半導体装置の信頼性が向上すると考えられる。 Therefore, according to the present invention, regardless of the combination of the material of the first conductive layer and the semiconductor layer material, the reliability of the semiconductor device is improved.
【0094】 [0094]
(実施形態5) (Embodiment 5)
図8を参照しながら、本発明による半導体装置の第5の実施形態を説明する。 With reference to FIG. 8, a description will be given of a fifth embodiment of a semiconductor device according to the present invention.
【0095】 [0095]
本実施形態に特徴的な点は、ソース電極25aおよびドレイン電極25bの各々が第1導電層2および第2導電層3の積層構造を有しているが、第1導電層2の側面に絶縁性保護層が存在していない点にある。 Characteristic feature in this embodiment is each of the source electrode 25a and drain electrode 25b has a stacked structure of a first conductive layer 2 and the second conductive layer 3, an insulating a side surface of the first conductive layer 2 It lies in the fact that sex protective layer is not present.
【0096】 [0096]
本実施形態によれば、第1導電層2の上面と半導体層4の下面との直接的な接触が避けられるが、第1導電層2の側面と半導体層4の下面との間が直接接触している。 According to the present embodiment, although direct contact with the lower surface of the first conductive layer 2 of the top surface and the semiconductor layer 4 is avoided, the contact between the lower surface of the first conductive layer 2 side and the semiconductor layer 4 is directly doing. このため、第1導電層2の上面の面積に比べて第1導電層2の側面の面積が格段に小さい場合や、第1導電層2の側面に形成される自然酸化膜によって第1導電層2と半導体層4との間の電気的抵抗が充分に高い場合、局部電池反応による電蝕をある程度抑制することが可能である。 Therefore, when the area of ​​the first side surface of the conductive layer 2 than the area of ​​the upper surface of the first conductive layer 2 is much smaller and, first conductive layer by a natural oxide film formed on the side surface of the first conductive layer 2 If 2 and electrical resistance between the semiconductor layer 4 is sufficiently high, it is possible to some extent the electrolytic corrosion due to local cell reaction. また、本実施形態によれば、絶縁性保護層を形成する工程が不要になるため、製造工程を単純化できるという利点がある。 Further, according to this embodiment, since the step of forming an insulating protective layer is not required, there is an advantage of simplifying the manufacturing process.
【0097】 [0097]
(実施形態6) (Embodiment 6)
図9を参照しながら、本発明による半導体装置の第6の実施形態を説明する。 With reference to FIG. 9, illustrating a sixth embodiment of the semiconductor device according to the present invention.
【0098】 [0098]
本実施形態に特徴的な点は、ソース・ドレイン電極25a、25bが第1導電層2および第2導電層3の積層構造を有しており、しかも、第2導電層3が第1導電層2の側面をも覆っている点にある。 The characteristic feature in this embodiment, the source and drain electrodes 25a, 25b are a layered structure of a first conductive layer 2 and the second conductive layer 3, moreover, the second conductive layer 3 first conductive layer It lies in the fact that also covers the second side.
【0099】 [0099]
本実施形態によれば、第1導電層2の半導体層4との直接的な接触を避けることができるため、局部電池反応による電蝕をある充分に抑制することができる。 According to this embodiment, it is possible to avoid direct contact with the first semiconductor layer 4 of the conductive layer 2, it is possible to sufficiently suppress that the electrolytic corrosion due to local cell reaction. ただし、ソース電極25aとドレイン電極25bとの間において、第2導電層3を電気的に分離する必要がある。 However, in between the source electrode 25a and the drain electrode 25b, it is necessary to electrically isolate the second conductive layer 3. このため、第2導電層3を基板1の上面に堆積した後、フォトリソグラフィ工程およびエッチング工程により、第2導電層3をパターニングする工程が付加的に必要になる。 Therefore, after the second conductive layer 3 is deposited on the upper surface of the substrate 1, by a photolithography process and an etching process, a step of patterning the second conductive layer 3 is additionally required.
【0100】 [0100]
なお、選択成長法により、第1導電層2の上面および側面にのみに第2導電層3を選択的に成長させることができれば、上記のフォトリソグラフィ工程およびエッチング工程は不要である。 Note that, by selective growth method, if it is possible to the second conductive layer 3 selectively grown only on the upper surface and the side surface of the first conductive layer 2, the above-mentioned photolithography process and an etching step is unnecessary.
【0101】 [0101]
【発明の効果】 【Effect of the invention】
本発明によれば、第1導電層の上面と半導体層との間に第2導電層を配置しているため、第1導電層の材料として半導体層との間で電蝕しやすい材料を用いたとしても、局部電池反応を抑制し、それによって電蝕を抑制することが可能である。 According to the present invention, since the arrangement of the second conductive layer between the top surface and the semiconductor layer of the first conductive layer, use the Shokushi easy material collector with the semiconductor layer as the material of the first conductive layer even had to suppress the local cell reaction, it is possible to suppress it by electrolytic corrosion. 更に、第1半導体層の側面と半導体層との間に絶縁性保護層を設けることにより、電蝕防止効果を更に高めるとともに、第1導電層の側面から延びるヒックに起因した断線などを効果的に防止することが可能になる。 Further, by providing the insulating protective layer between the side surface and the semiconductor layer of the first semiconductor layer, with further enhance the galvanic corrosion prevention effect, effectively breaking the like due to Hick extending from the side surface of the first conductive layer it is possible to prevent the.
【0102】 [0102]
本発明によれば、透明半導体として注目されているZnOやZnOを主成分とする化合物半導体から半導体層を形成し、かつ、電極・配線材料として低抵抗であるが電蝕反応を引き起こしやすいアルミニウムまたはアルミニウム合金を用いることが可能になる。 According to the present invention, the ZnO and ZnO has attracted attention as a transparent semiconductor forming the semiconductor layer of a compound semiconductor as a main component, and the electrode-but as the wiring material is a low-resistance electrolytic corrosion reaction easily causes aluminum or it is possible to use an aluminum alloy.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】従来の半導体装置を示す断面図である。 1 is a cross-sectional view showing a conventional semiconductor device.
【図2】本発明による半導体装置の第1の実施形態を示す断面図である。 It is a sectional view showing a first embodiment of a semiconductor device according to the invention, FIG.
【図3】(a)および(b)は、本発明による半導体装置の第1の実施形態の製造方法を示す工程断面図である。 3 (a) and (b) are process sectional views showing a manufacturing method of a first embodiment of a semiconductor device according to the present invention.
【図4】本発明による半導体装置の第2の実施形態を示す断面図である。 Is a sectional view showing a second embodiment of a semiconductor device according to the invention; FIG.
【図5】(a)および(b)は、本発明による半導体装置の第2の実施形態の製造方法を示す工程断面図である。 5 (a) and (b) are process sectional views showing a manufacturing method of the second embodiment of the semiconductor device according to the present invention.
【図6】本発明による半導体装置の第3の実施形態を示す断面図である。 Is a sectional view showing a third embodiment of a semiconductor device according to the present invention; FIG.
【図7】本発明による半導体装置の第4の実施形態を示す断面図である。 Is a sectional view showing a fourth embodiment of a semiconductor device according to the present invention; FIG.
【図8】本発明による半導体装置の第5の実施形態を示す断面図である。 Is a sectional view showing a fifth embodiment of a semiconductor device according to the present invention; FIG.
【図9】本発明による半導体装置の第6の実施形態を示す断面図である。 Is a sectional view showing a sixth embodiment of the semiconductor device according to the present invention; FIG.
【符号の説明】 DESCRIPTION OF SYMBOLS
1 ・・・ 基板2 ・・・ ソース・ドレイン電極の第1導電層3 ・・・ ソース・ドレイン電極の第2導電層4 ・・・ 半導体層5 ・・・ ゲート絶縁層6 ・・・ ゲート電極7 ・・・ 絶縁性保護層8 ・・・ レジストマスク10・・・ 第1電極の第1導電層11・・・ 第1電極の第2導電層12・・・ 第2電極20a・・・ソース電極20b・・・ドレイン電極25a・・・ソース電極25b・・・ドレイン電極30・・・ 第1電極 1 ... substrate 2 ... drain second conductive layer 4 ... semiconductor layer 5 ... gate insulating layer 6 ... gate electrode of the first conductive layer 3 ··· source and drain electrodes of the electrode 7 ... insulating protective layer 8 ... resist mask 10 ... second conductive layer 12 ... second electrode 20a.. the source of the first conductive layer 11 ... first electrode of the first electrode electrode 20b ... drain electrode 25a ... source electrode 25b ... drain electrode 30 ... first electrode

Claims (24)

  1. 基板と、 And the substrate,
    前記基板に支持されている少なくとも1つの電極と、 At least one electrode supported on said substrate,
    前記電極の上面の少なくとも一部に接触する半導体層と、 A semiconductor layer in contact with at least a portion of the upper surface of the electrode,
    を備えた半導体装置であって、 A semiconductor device provided with,
    前記半導体層は、ZnOまたはZnOを主成分とした化合物半導体から形成されており、 The semiconductor layer is formed of a compound semiconductor whose main component is ZnO or ZnO,
    前記電極は、 The electrodes,
    アルミニウムを主成分とする第1導電材料から形成された第1導電層と、 A first conductive layer formed of a first conductive material mainly composed of aluminum,
    前記第1導電層の上面と前記半導体層との間に配置され、前記第1導電材料とは異なる第2導電材料から形成された第2導電層と、 Is disposed between the semiconductor layer and the upper surface of the first conductive layer, a second conductive layer formed from a different second conductive material than the first conductive material,
    前記半導体層の下面と前記第1導電層の側面との間に位置する絶縁性保護層と、 An insulating protective layer located between the side surface of the lower surface and the first conductive layer of the semiconductor layer,
    を有しており、 A has,
    前記第2導電材料は、前記第1導電材料に比べて局部電池反応による腐食が生じにくい半導体装置。 The second conductive material, the corrosion hardly occurs semiconductor device according to a local cell reaction as compared to the first conductive material.
  2. 前記半導体層は、バンドギャップが3eV以上の半導体から形成されている請求項1に記載の半導体装置。 The semiconductor layer, the semiconductor device according to claim 1 in which the band gap is formed from the above semiconductor 3 eV.
  3. 前記絶縁性保護層は、前記第1導電材料の酸化物および/または窒化物から形成されている請求項1 または2に記載の半導体装置。 The insulating protective layer, the semiconductor device according to claim 1 or 2 is formed from an oxide and / or nitride of the first conductive material.
  4. 前記第1導電材料の比抵抗は、前記第2導電材料の比抵抗よりも低い請求項1からのいずれかに記載の半導体装置。 The resistivity of the first conductive material, a semiconductor device according to any one of 3 from lower claims 1 than the resistivity of the second conductive material.
  5. 前記第2導電材料と前記半導体層との間でオーミック性を有する接触が生じている請求項1からのいずれかに記載の半導体装置。 The semiconductor device according to any one of 4 claims 1 contact occurs with an ohmic resistance between the semiconductor layer and the second conductive material.
  6. 前記第2導電材料は、第IV族、第V族、もしくは第VI族の金属またはこれらの金属の窒化物である請求項に記載の半導体装置。 The second conductive material, the Group IV, semiconductor device according to claim 5 group V, or is a metal or a nitride of these metals of Group VI.
  7. 前記金属は、Ti、Ta、およびMoからなる群から選択された少なくとも1つの金属である請求項に記載の半導体装置。 It said metals, Ti, Ta, and a semiconductor device according to claim 6, from the group consisting of Mo is at least one metal selected.
  8. 前記少なくとも1つの電極は、前記基板上において離れた位置に形成された2つの電極を含んでいる請求項1からのいずれかに記載の半導体装置。 Wherein the at least one electrode, the semiconductor device according to any one of claims 1 to 7 which contains two electrodes formed at a position apart in the substrate.
  9. 前記2つの電極の各々における前記絶縁性保護層は、前記基板上において連続している請求項に記載の半導体装置。 Wherein the insulating protective layer in each of the two electrodes, the semiconductor device according to claim 8 which is continuous in the substrate.
  10. 前記絶縁性保護層は、可視光を透過する材料から形成されている請求項に記載の半導体装置。 The insulating protective layer, the semiconductor device according to claim 9, which is formed from a material which transmits visible light.
  11. 前記絶縁性保護層は、SiO 2 、Al 23 、Ta 23 、およびSiNx(0≦x<3)からなる群から選択された少なくとも1つの絶縁材料から形成されている請求項10に記載の半導体装置。 The insulating protective layer, the SiO 2, Al 2 O 3, Ta 2 O 3, and SiNx (0 ≦ x <3) according to claim 10, which is formed from at least one insulating material selected from the group consisting of the semiconductor device according.
  12. 前記半導体層の上面側に配置され、前記半導体層と接触する第2の電極を更に有している請求項1からのいずれかに記載の半導体装置。 Wherein disposed on the upper surface side of the semiconductor layer, a semiconductor device according to any one of the second electrode further from claim 1 has a 7 in contact with the semiconductor layer.
  13. 前記2つの電極は、それぞれ、ソース電極およびドレイン電極であり、 The two electrodes are, respectively, a source electrode and a drain electrode,
    前記半導体層の上面に形成されたゲート絶縁膜を介して前記半導体層に対向するゲート電極を有する請求項または10に記載の半導体装置。 The semiconductor device according to claim 9 or 10 having opposite gate electrode on the semiconductor layer via a gate insulating film formed on the upper surface of the semiconductor layer.
  14. 請求項1から13のいずれかに記載の半導体装置を備えた表示装置。 Display device comprising the semiconductor device according to any one of claims 1 13.
  15. 少なくとも1つの電極を基板上に形成する工程と、 Forming on a substrate at least one electrode,
    前記電極を覆うように、ZnOまたはZnOを主成分とした化合物半導体から半導体層を形成する工程とを含む半導体装置の製造方法であって、 To cover the electrode, a manufacturing method of a semiconductor device and forming a semiconductor layer of a compound semiconductor whose main component is ZnO or ZnO,
    前記電極を形成する工程は、 The step of forming the electrode,
    アルミニウムを主成分とする第1導電材料の膜を形成する工程と、 Forming a film of a first conductive material containing aluminum as its main component,
    前記第1導電材料に比べて局部電池反応による腐食が生じにくい第2導電材料の膜を前記第1導電材料の膜の上に堆積する工程と、 Depositing a film of the second conductive material less likely to occur corrosion due to a local cell reaction as compared to the first conductive material over the first conductive material film,
    前記2つの膜をパターニングすることにより、前記第1導電材料から形成された第1導電層と、前記第2導電材料から形成された第2導電層とを含む積層構造を形成する工程と、 By patterning the two film to form a laminated structure comprising a first conductive layer formed from the first conductive material and a second conductive layer formed from the second conductive material,
    前記第1導電層の側面を覆う絶縁性保護層を形成する工程とを含む、製造方法。 And forming an insulating protective layer covering the side surface of the first conductive layer, the manufacturing method.
  16. 前記2つの膜をパターニングする工程は、 Patterning the two film,
    前記2つの膜の上にレジストマスクを堆積する工程と、 Depositing a resist mask on the two films,
    前記2つの膜のうちレジストマスクで覆われてない部分をエッチングする工程とを含む請求項15に記載の製造方法。 The method according to claim 15 including the step of etching the portion not covered with the resist mask of the two films.
  17. 前記絶縁性保護層を形成する工程は、前記第1導電層の側面を酸化および/または窒する工程を含む、請求項15または16に記載の製造方法。 Wherein the step of forming the insulating protective layer comprises a step of oxidizing and / or nitriding the side of the first conductive layer, the manufacturing method according to claim 15 or 16.
  18. 前記絶縁性保護層を形成する工程は、 The step of forming the insulating protective layer,
    前記レジストマスクを除去する前に、絶縁膜を基板上に堆積する工程と、 Before removing the resist mask, depositing an insulating film on a substrate,
    前記レジストマスクを除去することにより、前記絶縁膜の不要部分のリフトオフを行い、前記絶縁膜の一部を前記第1導電層の側面に残置する工程と、 By removing the resist mask, a lift-off of the unnecessary portion of the insulating film, a step of leaving a portion of the insulating film on the side surface of the first conductive layer,
    を含む請求項16に記載の製造方法。 The method according to claim 16 comprising a.
  19. 基板と、 And the substrate,
    前記基板に支持されている少なくとも1つの電極と、 At least one electrode supported on said substrate,
    前記電極の上面の少なくとも一部に接触する半導体層と、 A semiconductor layer in contact with at least a portion of the upper surface of the electrode,
    を備えた半導体装置であって、 A semiconductor device provided with,
    前記半導体層は、ZnOまたはZnOを主成分とした化合物半導体から形成されており、 The semiconductor layer is formed of a compound semiconductor whose main component is ZnO or ZnO,
    前記電極は、 The electrodes,
    アルミニウムを主成分とする第1導電材料から形成された第1導電層と、 A first conductive layer formed of a first conductive material mainly composed of aluminum,
    前記第1導電層の上面と前記半導体層との間に配置され、前記第1導電材料とは異なる第2導電材料から形成された第2導電層と、 Is disposed between the semiconductor layer and the upper surface of the first conductive layer, a second conductive layer formed from a different second conductive material than the first conductive material,
    を有しており、 A has,
    前記第2導電材料は、前記第1導電材料に比べて局部電池反応による腐食が生じにくい半導体装置。 The second conductive material, the corrosion hardly occurs semiconductor device according to a local cell reaction as compared to the first conductive material.
  20. 前記第2導電層は、前記第1導電層の上面および側面の両方を覆っている、請求項19に記載の半導体装置。 It said second conductive layer covers both the top and side surfaces of the first conductive layer, a semiconductor device according to claim 19.
  21. 前記少なくとも1つの電極は、前記基板上において離れた位置に形成された2つの電極を含んでおり、前記2つの電極の各々における前記第2導電層は、前記基板上において電気的に分離されている請求項20に記載の半導体装置。 Wherein the at least one electrode includes two electrodes formed at separate positions in the substrate, the second conductive layer in each of the two electrodes are electrically isolated in the substrate the semiconductor device of claim 20 are.
  22. 前記第2導電材料と前記半導体層との間でオーミック性を有する接触が生じている請求項21に記載の半導体装置。 The semiconductor device of claim 21, contact having ohmic properties between the semiconductor layer and the second conductive material has occurred.
  23. 前記第2導電材料は、第IV族、第V族、もしくは第VI族の金属またはこれらの金属の窒化物である請求項22に記載の半導体装置。 The second conductive material, the Group IV, semiconductor device according to claim 22 Group V, or a metal or a nitride of these metals of Group VI.
  24. 前記金属は、Ti、Ta、およびMoからなる群から選択された少なくとも1つの金属である請求項23に記載の半導体装置。 It said metals, Ti, Ta, and a semiconductor device of claim 23, from the group consisting of Mo is at least one metal selected.
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